JPH10189819A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To hermetically seal a semiconductor integrated circuit chip without using a lid made of ceramic or the like. The present invention relates to a hermetically sealed semiconductor device. In the present invention, the semiconductor integrated circuit chip 2 is mounted on the insulating substrate 3 by a so-called flip chip method with its circuit forming surface side facing downward. A conductive bump 8 made of gold, solder or the like is provided on the electrode pad 2a formed on the circuit forming surface of the semiconductor integrated circuit chip, and this is joined to the conductor pattern 6 on the insulating substrate.
Further, a barrier bump 7 made of gold, solder or the like is formed on the circuit forming surface of the integrated circuit chip so as to surround the row of the electrode pads. The barrier bump 7 is joined to the surface of the insulating substrate 3 when the integrated circuit chip is mounted on the substrate, and the electrode pad 2
The space between the chip including the row a and the substrate is isolated from the external atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hermetically sealed type semiconductor integrated circuit package technology, and more particularly to a self-sealing type integrated circuit package that does not use a sealing lid.

[0002]

2. Description of the Related Art Advances in microfabrication technology have resulted in design rules reaching 0.35 to 0.18 μm, and the number of elements that can be formed on a single semiconductor integrated circuit chip has been increasing. High speed and low cost. On the other hand, integrated circuit chips are very sensitive to the influence of the external atmosphere. A hermetically sealed integrated circuit package encloses a semiconductor integrated circuit chip in a closed container and completely shuts off the chip from the external atmosphere. This is an important technique for protecting the chip from the adhesion of impurities to the circuit forming surface of the integrated circuit chip and moisture and maintaining the reliability of the chip.

FIG. 10 shows a hermetically sealed integrated circuit package using a conventional ceramic substrate. The semiconductor integrated circuit chip 15 is provided with a concave portion 16 a of a multilayer ceramic substrate 16.
It is fixed with an adhesive 17 with the circuit forming surface facing upward. After wire-bonding the wiring pattern 16b on the substrate and the electrode pad of the chip 15, a lid 18 made of ceramic, metal, or the like is attached onto the substrate 16 with a sealing material 19 made of glass, a solder alloy, or the like so as to cover the recess 16a. .

However, in the above-mentioned conventional hermetically sealed type integrated circuit package, a lid 18 made of ceramic, metal or the like is required to hermetically seal the integrated circuit chip 15, and a process for mounting the same is required. Is required.
Ultimately, this contributes to increasing package manufacturing costs. Also, by attaching the lid 18 on the substrate, the height of the entire package is increased. Further, the planar dimension of the package becomes large because it is necessary to secure a space for mounting the lid 18 on the outer periphery of the concave portion of the substrate. In mounting an integrated circuit package on a device that requires miniaturization, it is important to reduce the size and thickness of the package, and a package having a large planar dimension and a height is an obstacle.

Further, in the conventional package, heat generated from the integrated circuit chip 15 is trapped in the recess 16a which is completely sealed by the lid 18 from the outside atmosphere, and hardly radiates to the outside. Due to the low heat generation efficiency, a malfunction occurs in the integrated circuit chip, and the reliability of the device is reduced.

[0006]

SUMMARY OF THE INVENTION The present invention provides a semiconductor device which realizes a reduction in manufacturing man-hours and a reduction in cost by hermetically sealing a semiconductor integrated circuit chip without using the above-mentioned lid made of ceramic or the like. It is intended to be.

Another object of the present invention is to provide a self-sealing type semiconductor device suitable for realizing miniaturization.

Another object of the present invention is to provide a hermetically sealed semiconductor device having good heat generation efficiency.

Further, the present invention relates to a so-called bare chip mounting in which an integrated circuit chip is mounted directly on an external substrate,
It is intended to achieve hermetic sealing of the chip.

[0010]

SUMMARY OF THE INVENTION The present invention relates to a hermetically sealed semiconductor device. In the present invention, the semiconductor integrated circuit chip has its circuit forming surface side facing down,
It is mounted on an insulating substrate by a so-called flip chip method. A conductive bump is provided on an electrode pad formed on a circuit forming surface of a semiconductor integrated circuit chip, and this is bonded to a conductor pattern on an insulating substrate. Further, a barrier is formed on the circuit forming surface of the integrated circuit chip so as to surround the row of the electrode pads. The barrier is bonded to the substrate surface when the integrated circuit chip is mounted on the substrate, and blocks a space between the chip and the substrate including the row of electrode pads from the external atmosphere. Ideally, it is preferable that the barrier be formed along the periphery of the chip in order to isolate almost the entire circuit forming surface of the chip from the external atmosphere.

In order to facilitate the manufacture of the semiconductor device, the barrier is preferably formed of a solder or gold bump made of the same material as the conductive bump for bonding the electrode pad to the substrate. In this case, a metal pattern is formed on the circuit forming surface of the integrated circuit chip, and a barrier is bonded thereon. A metal pattern is also formed on the insulating substrate at the corresponding position. Then, after mounting the integrated circuit chip on the insulating substrate, the above-mentioned conductive bumps and barriers are melted by batch reflow or thermocompression bonding, and each is joined to the pattern on the insulating substrate, which is advantageous in manufacturing. However, even when the barrier and the conductive bumps are formed of a conductive or non-conductive adhesive resin (for example, a resin such as epoxy) without depending on such a solder or gold bump, the object of the present invention is also provided. Is achieved.

The scope of the present invention is not limited by the shape and material of the insulating substrate of the semiconductor device. As the material of the insulating substrate, multilayer ceramic, glass, metal, glass / epoxy resin, and others can be adopted. The insulating substrate may or may not have a recess at the position where the integrated circuit chip is mounted. The conductor pattern on the insulating substrate has pads connected to the mounting terminals on the side opposite to the chip mounting surface via via holes for the purpose of positioning the terminals for mounting on the external substrate outside the barrier. A structure with a positioned structure is better.

The present invention also realizes hermetic sealing of a chip in a so-called bare chip mounting in which an integrated circuit chip is mounted directly on an external substrate. Each electrode pad of the integrated circuit chip is electrically connected to the conductor pattern of the external substrate by a conductive bump formed on each electrode pad. A barrier is formed on the circuit forming surface side of the integrated circuit chip so as to surround the row of the electrode pads, and is joined to an external substrate when the chip is mounted. The space between the chip including the row of electrode pads and the external substrate is shielded from the external atmosphere by a barrier and protected.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. As shown in FIGS. 1 and 2, the semiconductor device 1 has an insulating substrate 3 made of a multilayer ceramic. One end of each wiring pattern formed on the insulating substrate 3 is a bump bonding pad 4a, and is exposed on the upper surface of the insulating substrate 3. The electrode pads 2a of the integrated circuit chip 2 described later and the bump bonding pads 4a are electrically connected at the time of chip mounting. The other end of each wiring pattern is a mounting terminal connection pad 4b, which is exposed on the lower surface side of the insulating substrate 3.
A terminal 5 for mounting the semiconductor device 1 on an external substrate is
It is connected to this mounting terminal connection pad 4b. The bump bonding pad 4a and the mounting terminal connection pad 4b are electrically connected through a pattern 4c formed between layers of the multilayer ceramic substrate 3 and via holes 4d.

A metal pattern 6 is formed on the upper surface of the insulating substrate 3 so as to surround a row of bump bonding pads 4a of the wiring pattern. The metal pattern 6 is for facilitating the bonding of a barrier bump 7 described later on the insulating substrate, and does not work electrically. However, since the metal pattern 6 can be formed together with the wiring pattern in the step of forming the wiring pattern on the insulating substrate, it is advantageous in manufacturing.

The integrated circuit chip 2 is mounted on the insulating substrate 3 with its circuit forming surface facing down, that is, in a flip-chip manner. 3 and 4 show the integrated circuit chip 2
Of the circuit formation surface is well represented. Electrode pads 2a made of aluminum or the like along the four sides of the integrated circuit chip
Are formed. Some of the electrode pads 2a are for supplying a power supply potential or a ground potential to the circuits in the chip, and others are for transferring signals between the circuits in the chip and the outside. In the final step of the integrated circuit chip, conductive bumps 8 made of gold or solder are formed on the electrode pads 2a. Conductive bump 8 when mounting chip
Are placed on the bump bonding pads 4a of the insulating substrate 3 and are melted in the subsequent step to bond with the bump bonding pads. The surface of the conductive bump 8 formed of solder can be subjected to electrolytic plating of gold or the like in order to improve its electrical characteristics.

Further, a pattern 9 made of aluminum or the like is formed between the row of the electrode pads and the edge of the chip so as to surround the row of the electrode pads 2a on the circuit forming surface of the integrated circuit chip 2. When the electrode pads 2a are formed, a metal film is also deposited on the integrated circuit chip 2 at a position corresponding to the pattern 9, whereby the pattern 9 can be formed. Except for the region where the electrode pad and the barrier pattern are formed, the circuit formation surface is covered with a layer 10 of a silicon nitride film (or a silicon oxide film).

As shown in FIG. 4, a continuous barrier bump 7 is formed on the pattern 9 along the pattern 9.
In the embodiment, the barrier bump 7 is formed of the same gold or solder as the conductive bump 8 on the electrode pad 2a. The height of the barrier bump 7 from the circuit formation surface is the same as that of the conductive bump 8, and when the integrated circuit chip 2 is mounted on the insulating substrate 3, its tip contacts the pattern 6 on the substrate. In one embodiment, the height of bumps 7 and 8 is about 20 μm.
m. With the barrier bump 7 in contact with the pattern 6, the barrier bump 7 is melted and joined to the pattern 6. The barrier bumps 7 are joined to the pattern 6 to function as walls that block the space between the circuit forming surface of the chip 2 including the rows of the electrode pads 2a and the insulating substrate 3 from the external atmosphere. Therefore, external moisture and impurities are blocked by the barrier bumps 7 and cannot reach the circuit forming surface of the chip, especially the conductive bumps 8 on the electrode pads 2a.

FIG. 5 is a sectional view of a semiconductor device according to another embodiment. This embodiment is different from the previous embodiment in that an insulating substrate 3 ′ made of a ceramic substrate is configured to have substantially the same planar dimensions as the integrated circuit chip 2. Other configurations are the same as those of the previous embodiment shown in FIGS. In the present embodiment, the structure for chip sealing can be achieved only by the barrier bumps 7, so that no sealing member for covering the integrated circuit chip is required. Therefore, by arranging the barrier bumps 7 near the outer periphery of the chip 2, a package having almost the same size as the integrated circuit chip can be formed, and a so-called chip size package can be achieved with a simple structure.

FIG. 6 is a sectional view of a semiconductor device according to another embodiment. This embodiment is different from the previous embodiment in that a concave portion 3a is formed in the insulating substrate 3 and this concave portion 3a is formed.
This is the point that the integrated circuit chip 2 is placed in a. The method of mounting the integrated circuit chip 2 on the substrate is the same as in the previous embodiment. That is, the bump bonding pad 4a of the wiring pattern and the metal pattern 6 are formed on the substrate surface in the recess 3a. The conductive bumps 8 formed on the respective electrode pads 2a of the integrated circuit chip 2 and the barrier bumps 7 formed on the patterns 9 are placed on the bump bonding pads 4a or the metal patterns 6 when the chip is mounted. After chip mounting, the conductive bumps 8 and the barrier bumps 7 are melted and bonded to the insulating substrate 3 side.

The advantage of the package having this structure is as follows.
The point that the relatively fragile integrated circuit chip 2 is not protruded from the substrate surface can be protected from the outside. However, since the upper part of the integrated circuit chip 2 is completely exposed, a protective member may be provided so as to cover the chip 2 and the package may be configured to avoid physical damage to the chip. Even in such a case, it is not necessary to consider the airtightness when attaching the protection member, so that the selection and attachment of the member is easy.

FIG. 7 shows an embodiment of the present invention in the case of so-called bare chip mounting, in which the integrated circuit chip 2 provided with the barrier bumps 7 shown in FIGS. 3 and 4 is directly mounted on an external substrate. Insulating substrate 3 in previous embodiment
Similarly to the above, on the upper surface side of the external substrate 11, a bump bonding pad 4a and a pattern 6 are formed so as to surround the bump bonding pad 4a. The bump bonding pad 4a is connected to the wiring pattern 4 on the opposite side of the substrate 11 via a via hole 4d. The integrated circuit chip 2 is mounted on the external substrate 11 in the same manner as the mounting method of the integrated circuit chip 2 on the insulating substrate 3 in the previous embodiment.

FIG. 8 shows a step of mounting an integrated circuit chip having barrier bumps on an insulating substrate. FIG.
It will be apparent that the process of mounting the integrated circuit chip on the external substrate 11 in the bare chip mounting shown in (1) is substantially the same as this process. The solder bumps 12 are fused on the bump bonding pads 4a and the pattern 6 of the insulating substrate 3 (step (A)). The upper part of the solder bump 12 is crushed and smoothed so that the integrated circuit chip 2 can be mounted stably (step (B)). The integrated circuit chip 2 on which the conductive bumps 8 and the barrier bumps 7 are formed in another step is mounted on the flux-coated insulating substrate 3 (step (C)). At this time, the conductive bumps 8 on the chip side are placed on the bump bonding pads 4a, and the barrier bumps 7 are placed on the pattern 6. With the chip 2 mounted on the insulating substrate, the conductive bumps 8 and the barrier bumps 7 are formed by high-temperature reflow.
Then, the solder bumps 12 are melted (step (D)). After a predetermined time, these bumps are solidified and the integrated circuit chip 2
Is fixed on the insulating substrate 3. The solder bumps 12 provided on the insulating substrate 3 are not necessarily required, and the barrier bumps 7 and the conductive bumps 8 may be directly mounted on the patterns 6 and the bump bonding pads 4a.

FIG. 9 shows a method of mounting an integrated circuit chip on an insulating substrate by thermocompression bonding. The integrated circuit chip 2 is mounted on the insulating substrate 3 fixed to the base 13, and the heater 14 heated to the solder melting temperature from above is pressed. The barrier bumps 7 and the conductive bumps 8 are melted by the heat of the heater 14 and are bonded to the pattern 6 on the insulating substrate 3 and the bump bonding pads 4a. The heater 14 is removed from the integrated circuit chip 2 and the mounting of the chip on the insulating substrate 3 is completed.

The embodiments of the semiconductor device according to the present invention have been described with reference to the drawings. Obviously, the present invention is not limited to the range shown in the above embodiment. In the embodiment, the present invention is applied to a PGA (Pin Grid Array) type semiconductor package having a pin type connection terminal on the lower surface of an insulating substrate. However, various types of semiconductor devices such as QFP (Quad Flat Package) and BGA (Ball G
The present invention is applicable to packages such as rid Array).
Further, the present invention can be applied to an integrated circuit chip having a row of electrode pads in the center of a circuit formation surface.

[0026]

According to the present invention, a semiconductor integrated circuit chip can be hermetically sealed without using a lid made of ceramic or the like, so that the number of steps for manufacturing a semiconductor device and the cost can be reduced.

Further, the semiconductor device manufactured according to the present invention can be made smaller and thinner than a conventional semiconductor device, and can be widely used for electronic communication devices which are being miniaturized.

Further, in the semiconductor device according to the present invention,
Since the back surface of the integrated circuit chip is exposed without being covered by the package, heat generated from the integrated circuit chip is efficiently dissipated, and the reliability of the device can be improved.

The present invention also relates to a so-called bare chip mounting in which an integrated circuit chip is directly mounted on an external substrate,
Hermetic sealing of the chip can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment in which the present invention is applied to a PGA type semiconductor device.

FIG. 2 is an enlarged view of a main part of FIG. 1;

FIG. 3 is a plan view showing a state on a circuit forming surface side of an integrated circuit chip before a conductive bump and a barrier bump are mounted.

4 is a cross-sectional view taken along line AA of FIG. 3 in a state where a conductive bump and a barrier bump are mounted.

FIG. 5 is a sectional view showing an embodiment in which the present invention is applied to a so-called chip size package.

FIG. 6 is a cross-sectional view of another embodiment of the present invention in which an integrated circuit chip is mounted on an insulating substrate having a recess.

FIG. 7 is a cross-sectional view in a state where the integrated circuit chip according to the present invention is directly mounted on an external substrate.

FIG. 8 is a view showing a step of mounting an integrated circuit chip on an insulating substrate.

FIG. 9 is a diagram showing a method for mounting an integrated circuit chip on an insulating substrate by thermocompression bonding.

FIG. 10 is a cross-sectional view showing a hermetically sealed integrated circuit package using a conventional ceramic substrate.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor device 2 integrated circuit chip 2 a electrode pad 3 insulating substrate 3 a recess 4 wiring pattern 4 a bump bonding pad 4 b mounting terminal connection pad 4 c pattern 4 d via hole 5 terminal 6 metal pattern 7 barrier bump 8 conductive bump 9 pattern 10 Oxide film layer 11 External substrate 12 Solder bump 13 Base 14 Heater

Claims (11)

[Claims] 1. An integrated circuit board comprising: an insulating substrate provided with a conductive pattern; and a row of electrode pads on a circuit forming surface, wherein the circuit forming surface is mounted on the insulating substrate with the circuit forming surface facing the insulating substrate. A circuit chip, a conductive bump provided on each electrode pad of the semiconductor integrated circuit chip, and bonded to a conductor pattern of the insulating substrate, and a circuit of the semiconductor integrated circuit chip surrounding the row of the electrode pads. And a barrier provided on the formation surface side and joined to the insulating substrate to seal the row of the electrode pads from the outside air. 2. A pattern formed of a metal film on a circuit forming surface side of the semiconductor integrated circuit chip so as to surround the row of the electrode pads, and the barrier is joined on the pattern.
13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein a metal pattern for joining said barrier is formed on said insulating substrate. 4. The semiconductor device according to claim 3, wherein said conductive bump and said barrier are solder or gold bumps. 5. The semiconductor device according to claim 1, wherein said semiconductor integrated circuit chip has said barrier along its periphery. 6. The mounting substrate according to claim 1, wherein the insulating substrate has mounting terminals connected to the conductor pattern on a surface opposite to a mounting surface of the semiconductor integrated circuit chip. Semiconductor device. 7. A mounting structure of a semiconductor device in which a semiconductor integrated circuit chip having a row of electrode pads on a circuit forming surface is mounted on an external substrate with the circuit forming surface facing down, wherein each of the semiconductor integrated circuit chips The electrode pads and the conductor pattern of the external substrate are electrically connected by conductive bumps formed on each of the electrode pads, and are formed on the circuit forming surface side of the semiconductor integrated circuit chip so as to surround the rows of the electrode pads. The mounting structure of a semiconductor device in which the rows of the electrode pads are sealed from the outside air by joining the formed barrier to the external substrate. 8. A step of forming a semiconductor integrated circuit chip having a row of electrode pads and a pattern of a metal film disposed around the row of electrode pads on a circuit forming surface; To form a conductive bump,
Forming a bump for a barrier continuous along the pattern on the pattern, and a conductor pattern for electrically connecting each of the electrode pads to an external substrate, and at a position of the bump for the barrier. Preparing an insulating substrate having a correspondingly formed metal pattern, and mounting the semiconductor integrated circuit chip on the insulating substrate so that the circuit forming surface faces the insulating substrate;
Bonding a conductive bump on the electrode pad to a conductor pattern on the insulating substrate and bonding the barrier bump to a metal pattern on the insulating substrate. 9. The conductive bumps and the barrier bumps are made of gold or solder, and after mounting the semiconductor integrated circuit chip on the insulating substrate, the conductive bumps and the barriers are subjected to batch reflow or thermocompression bonding. 9. The method of manufacturing a semiconductor device according to claim 8, wherein a bump for bonding is bonded to the conductor pattern and the metal pattern on the insulating substrate. 10. A step of forming a semiconductor integrated circuit chip having a row of electrode pads and a pattern of a metal film disposed around the row of electrode pads on a circuit forming surface; To form a conductive bump,
Forming a bump for a barrier continuous along the pattern on the pattern; and a conductor pattern formed corresponding to the position of each of the electrode pads, and corresponding to the position of the bump for the barrier. Preparing an external substrate on which the semiconductor integrated circuit chip having the metal pattern formed by mounting the semiconductor integrated circuit chip is mounted; and mounting the semiconductor integrated circuit chip on the external substrate so that the circuit formation surface faces the external substrate. Along with
Bonding a conductive bump on the electrode pad to a conductor pattern on the external substrate, and bonding the barrier bump to a metal pattern on the external substrate. 11. The conductive bumps and the barrier bumps are made of gold or solder. After the semiconductor integrated circuit chip is mounted on the external substrate, the conductive bumps and the barriers are subjected to collective reflow or thermocompression bonding. The method for mounting a semiconductor device according to claim 10, wherein a bump for bonding is bonded to the conductor pattern and the metal pattern on the external substrate.