JPH10173200A - Manufacture or semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the manufacturing cost of a semiconductor device, by forming a low-concentration impurity area by using a simple means. SOLUTION: An aluminum pattern 107 and a gate insulating film 108 are formed by a dry etching method by using a resist mask 106 as a mask. Then, an aluminum pattern 107' having a width narrower than that of the resist mask 106 is formed by only selectively etching the side face of the aluminum pattern 107. Finally, a lowly concentrated impurity area is formed in a self-aligning way by performing ion implantation by using the gate insulating film 108 and a gate electrode 110 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a method for manufacturing a semiconductor device using a thin film semiconductor. In particular, the present invention relates to a method for manufacturing a planar thin film transistor.

[0002]

2. Description of the Related Art Field effect transistors (FETs) and thin film transistors (TFTs) are used as insulated gate semiconductor devices.
It has been known. These insulated gate type transistors include an active layer composed of a source region, a channel forming region, and a drain region, a gate insulating film in contact with the active layer, and a gate in contact with the gate insulating film and disposed on the opposite side of the active layer. And electrodes.

As a means for improving the reliability of the insulated gate transistor, there is known a technique of providing a low-concentration impurity region having a lower impurity concentration than the drain region between the channel formation region and the drain region. Such a low concentration impurity region is also called an LDD (Lightly Doped Drain) region.

The present inventors have disclosed a technique described in Japanese Patent Application Laid-Open No. Hei 7-135318, for example, as means for forming such a low-concentration impurity region. According to the technique described in this publication, an anodic oxide film is formed on a side wall of a gate electrode by using an anodic oxidation method, and a high resistance drain (HRD: High Res.
This is a technique for forming an istive drain region. Hereinafter, the technique will be briefly described.

In FIG. 3A, 301 is a glass substrate, 302 is a base film, 303 is an active layer made of a crystalline silicon film, 304 is a first insulating film to be a gate insulating film later, and 3
05 is an aluminum film serving as a prototype of a gate electrode, 306
Is a thin anodic oxide film formed by the first anodic oxidation, 30
7 is a resist mask.

Next, a second anodic oxidation is performed in the state shown in FIG. 3A to form a porous anodic oxide film 308 on the side surface of the aluminum film 305. In the anodic oxidation step shown in FIG. 3B, the thin anodic oxide film 306 functions as an adhesive layer for preventing the resist mask 307 from peeling off.

Next, after removing the resist mask 307, a third anodic oxidation is performed to form a dense anodic oxide film 309.
To form At this time, since the electrolytic solution penetrates into the inside of the porous anodic oxide film 308, the anodic oxide film 309 is formed in a state as shown in FIG. At this time, the gate electrode 310 is defined.

Next, in the state shown in FIG. 3C, the first insulating film 304 is etched by a dry etching method.
After this etching step, a gate insulating film 311 is defined while remaining under the anodic oxide film 309 and the gate electrode 310. (FIG. 3 (D))

Next, after removing the porous anodic oxide film 308, an impurity ion for imparting one conductivity to the active layer 303 is added to the source layer 312 and the drain region 3.
13, low-concentration impurity regions 314 and 315 and a channel formation region 316 are formed. The low concentration impurity region 315 is particularly called an LDD region. (FIG. 3 (E))

Although not shown here, the anodic oxide film 3
Immediately below 09 is a substantially intrinsic region where the gate voltage is not applied, and is an offset region that works as a resistance component. The present inventors have proposed an offset region and an LDD region 315.
Is defined as the HRD area, and the conventional LRD
It is distinguished from the DD region.

The above is a brief description of the technique described in Japanese Patent Application Laid-Open No. Hei 7-135318. Steps subsequent to the state shown in FIG. 3E may be performed in accordance with a normal TFT manufacturing process, and a description thereof will be omitted. As described above, the technique described in Japanese Patent Application Laid-Open No. Hei 7-135318 is to produce an HRD structure through three anodic oxidation steps.

[0012]

SUMMARY OF THE INVENTION The present invention relates to
A low-concentration impurity region is formed by a simpler means than the technique described in JP-A-7-135318, and an LDD structure or HR is formed.
It is an object to reduce the manufacturing cost of a semiconductor device having a D structure.

[0013]

Means for Solving the Problems The structure of the invention disclosed in the present specification is a first method for forming an active layer and a silicon-based insulating film covering the active layer on a substrate having an insulating surface. A second step of forming a metal film made of aluminum or a material mainly containing aluminum on the insulating film containing silicon as a main component, and selectively forming a resist mask on the metal film. A third step, a fourth step of etching the metal film by a dry etching method, a fifth step of etching the insulating film containing silicon as a main component by a dry etching method, and only a side surface of the metal film. A step of isotropically etching the active layer, and a step of adding an impurity ion imparting one conductivity to the active layer after removing the resist mask. And butterflies.

According to another aspect of the present invention, a first step of forming an active layer and an insulating film containing silicon as a main component covering the active layer on a substrate having an insulating surface, A second step of forming a metal film made of aluminum or a material containing aluminum as a main component on an insulating film to be formed, a third step of selectively forming a resist mask on the metal film, A fourth step of etching the film by dry etching, a fifth step of etching the insulating film containing silicon as a main component by dry etching, and a fifth step of isotropically etching only the side surface of the metal film. A sixth step of forming an oxide film on the exposed surface of the metal film by anodic oxidation or plasma oxidation after removing the resist mask; and imparting one conductivity to the active layer. An eighth step of adding impurity ions that are characterized by having at least a.

That is, the present invention is characterized in that the LDD structure (or HRD structure) conventionally manufactured through a plurality of anodic oxidation steps can be manufactured by simpler means. Therefore, a significant improvement in throughput is realized.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An active layer 103, an insulating film 104 containing silicon as a main component, and a metal film 105 containing aluminum or aluminum as a main component are formed on a substrate (glass substrate) 101 having an insulating surface. Then, a resist mask 106 is selectively disposed, and the metal film 1 is used as a mask.
05, the insulating film 104 containing silicon as a main component is etched by a dry etching method. At this time, the metal film 105,
An etching gas having selectivity is used for the insulating film 104 containing silicon as a main component.

Next, only the side surface of the aluminum pattern 107 is selectively etched by a wet etching method to form an aluminum pattern 10 serving as a prototype of a gate electrode.
7 'is formed. Then, the aluminum pattern 10
7 ′ is subjected to anodic oxidation to form a dense anodic oxide film 109 and a gate electrode 110 functioning as a protective layer.

When the structure shown in FIG. 1D is obtained through the above steps, the gate electrode 11
0 (including the anodic oxide film 109 strictly) and the gate insulating film 108 as masks to add impurity ions in a self-aligned manner to form a source region 113, a drain region 114, and low-concentration impurity regions 115 and 116. Implement an HRD structure.

[0019]

【Example】

[Embodiment 1] HRD is used as a semiconductor device utilizing the present invention.
A manufacturing process of a thin film transistor (TFT) having a structure will be described with reference to FIGS. This embodiment is an embodiment of the present invention, and the present invention is not limited to this embodiment.

First, a substrate having an insulating surface is prepared by forming a silicon oxide film as a base film 102 on a glass substrate 101 to a thickness of 2000 mm. A quartz substrate, a silicon substrate, or the like may be used instead of the glass substrate.

Next, a crystalline silicon film (not shown) is formed on the base film 102 to a thickness of 500 下地, and the crystalline silicon film is processed into an island shape to form an active layer 103. The crystalline silicon film may be formed directly or may be obtained by crystallizing an amorphous silicon film. Further, the active layer 103
Can be made of an amorphous silicon film.

After forming the active layer 103, a silicon oxide film 104 to be a gate insulating film later is formed to a thickness of 1200 °. In addition to a silicon oxide film, an insulating film containing silicon as a main component such as a silicon oxynitride film or a silicon nitride film can be used. Further, a laminated structure of them can also be used.

Next, a metal film 105 containing scandium at 0.2 wt% with respect to aluminum is formed to a thickness of 2500 °. Scandium suppresses the generation of hillocks and whiskers on the aluminum surface. (Fig. 1 (A))

When the state shown in FIG. 1A is obtained, a resist mask 106 is selectively disposed on a region to be a gate electrode, and the metal film 105 is etched. At this time, in the present invention, since the anodic oxidation is not performed with the resist mask 106 attached, the metal film 105 and the resist mask 10
It is not necessary to provide an adhesive layer (thin anodic oxide film) as in the prior art between the first and second substrates.

The etching of the metal film 105 is performed by an anisotropic dry etching method, and Si is used as an etching gas.
A mixed gas of Cl ₄ and Cl ₂ is used. Such a chlorine-based gas is characterized in that the silicon oxide film 104 serving as a base is hardly etched. Thus, an aluminum pattern 107 serving as a prototype of the gate electrode is formed.

Next, the silicon oxide film 104 is etched by switching the etching gas to a fluorine-based gas such as CHF ₃ to form a gate insulating film 108. In this embodiment, switching of the etching gas and etching conditions (applied power,
Gas pressure, etc.) without changing the metal film 105 to the atmosphere.
Thus, the throughput is high because the silicon oxide film 104 is etched. At this time, since the fluorine-based gas hardly etches the aluminum pattern 107, the silicon oxide film 104
Only one can be selectively etched.

Thus, the state shown in FIG. 1B is obtained. In this embodiment, since the selective etching gas is selectively used, the shapes of the aluminum pattern 107 and the gate insulating film 108 can be made substantially the same. This is a possible configuration because a metal film containing aluminum as a main component is not etched with a fluorine-based gas, and a thin film containing silicon, tantalum, tungsten, molybdenum, or the like as a main component is easily etched with a fluorine-based gas. I will.

When the state shown in FIG. 1 (B) is obtained, phosphoric acid,
The aluminum pattern 107 is etched using a mixed acid solution in which acetic acid and nitric acid are mixed (hereinafter, this step is referred to as a side etching step). At this time, since the etching proceeds isotropically only on the side surfaces of the aluminum pattern 107, an aluminum pattern 107 'as shown in FIG. 1C is obtained.

In this embodiment, the temperature of the mixed acid solution is 35 ° C.
A process of about 40 seconds is performed to etch a distance of 0.7 μm. This distance will later determine the length of the low concentration impurity region. The length of the low-concentration impurity region can be freely set by the practitioner experimentally determining the optimum value and adjusting the etching time.

The side etching step of the aluminum pattern as shown in FIG. 1C can also be performed by an isotropic dry etching method. In that case, the steps shown in FIGS. 1B and 1C can be performed continuously, but care must be taken not to cause excessive plasma damage to the active layer.

As another means of the side etching step, the aluminum surface can be electrolytically etched. In that case, a solution that does not form an oxide film on the aluminum surface as an electrolytic solution (preferably an alkaline solution)
Is used. In electrolytic etching, high reproducibility can be expected since the amount of etching can be controlled by the amount of charge.

Next, the resist mask 106 is removed with a dedicated stripper, and an oxide film functioning as a protective film is formed on the exposed surface of the aluminum pattern 107 'by anodic oxidation. In the case where an aluminum film having high heat resistance is used so as not to generate hillocks even when heated to about 400 to 500 ° C., it is possible to omit the oxide film formation here.

The anodic oxidation step is performed using an ethylene glycol solution containing 3% tartaric acid as an electrolytic solution, and a dense anodic oxide film 10 is formed on the surface of the aluminum pattern 107 '.
9 is formed. Further, the gate electrode 110 is thus defined.

At this time, the anodic oxide film 109 has a thickness of 100 to 500 Å.
It is desirable to form it with a thickness of preferably 150 to 300 mm. If the thickness is less than this, the function of protecting the gate electrode 110 (including hillock prevention) may be lost. On the other hand, if the thickness is more than this, it will be difficult to remove the anodic oxide film 109 when forming a contact hole above the gate electrode later.

The state shown in FIG. 1D is obtained as described above. Next, impurity ions imparting one conductivity type (phosphorus in the case of an N-channel TFT, boron in the case of a P-channel TFT) are added to the active layer. The impurity region to which the impurity ions are added is formed in a self-aligned manner using the gate electrode 110 and the gate insulating film 108 as a mask.

First, as shown in FIG. 2A, the first ion implantation is performed by increasing the acceleration voltage to about 80 kV to form impurity regions 111 and 112. In this ion implantation, the range of the impurity ions is long because the acceleration voltage is high, and the impurity ions are added to the inside of the active layer 103 through the gate insulating film 108.

Next, the acceleration voltage is set to about 10 kV, which is lower than the first time, and the second ion implantation is performed. In this ion implantation, the range of the impurity ions is short because the acceleration voltage is low, and is not added below the gate insulating film 108. (FIG. 2 (B))

The source region 113 and the drain region 114 are formed by the two ion implantation steps as described above. The concentration of the regions 115 and 116 is determined by the first ion implantation, and the regions are low-concentration impurity regions having a lower concentration than the source / drain regions. Further, a channel formation region 117 to which impurity ions are not added (substantially intrinsic) is formed immediately below the gate electrode 110.
Strictly, an offset region (not shown) is formed between the low-concentration impurity regions 115 and 116 and the channel formation region 117.

When the state shown in FIG. 2B is obtained, the added impurity ions are activated by thermal annealing, laser annealing, or a combination of both. At this time, damage to the active layer 103 caused by the ion implantation is repaired.

After the interlayer insulating film 118 is formed, a contact hole is formed, and a source wiring 119, a drain wiring 120, and a gate wiring 121 are formed. Finally, the whole is subjected to a hydrogenation treatment to complete the semiconductor device shown in FIG.

The most significant feature of this embodiment is that the HRD structure which has conventionally been manufactured through three anodic oxidation steps can be realized by one anodic oxidation step. This means that the throughput is greatly improved. Moreover,
There is no need to increase the number of masks used.

In the case of the conventional example described with reference to FIG. 3, the dense anodic oxide film 309 is formed of the porous anodic oxide film 3.
Since the etching is carried out at the same time as the removal of 08, it is necessary to form a film having a thickness of about 800 to 1000 mm with a margin for the set film thickness. Therefore, the final film thickness is often at least 500 mm or more, and it has been difficult to quickly remove the contact hole when forming a contact hole above the gate electrode.

However, according to the present invention, the thickness of the dense anodic oxide film 109 can be reduced to the minimum (typically 150 to 300 °) only by preventing hillocks or the like. It can be easily removed when the holes are formed. Further, easy division is possible in the wiring division step.

[Embodiment 2] In this embodiment, an example in which the order of the steps of adding impurity ions in Embodiment 1 is changed will be described. FIG. 4 is used for the description, and the same reference numerals as those used in FIGS.

First, the procedure shown in FIG.
The state shown in (C) is obtained. That is, the resist mask 106 is placed on the aluminum pattern 107 'in a state like an umbrella after the side etching process is completed.
(FIG. 4 (A))

Then, a first ion implantation step is performed in the state shown in FIG. Note that if the acceleration voltage is high, the resist mask 106 is deteriorated and becomes difficult to remove, so it is preferable to implant the resist mask at a low acceleration voltage. In the state of FIG. 4A, since the resist mask 106 exists,
An impurity is added to a region indicated by reference numerals 1 and 402.

Next, the resist mask 106 is removed, and an anodic oxidation step is performed under the same conditions as in the first embodiment. In this step, a dense anodic oxide film 109 is formed, and a gate electrode 110 is formed.
Is defined. (FIG. 4 (B))

Next, a second ion implantation step is performed at an acceleration voltage higher than the first, and low concentration impurity regions 405 and 406 are formed under the gate insulating film 108. At this time, impurity ions are also added to the exposed portion of the active layer.
The regions denoted by reference numerals 1 and 402 are a source region 401 'and a drain region 402' to which impurity ions are added at a high concentration. A region indicated by 407 is a channel formation region.

After the above steps are completed, activation of impurity ions is performed, an interlayer insulating film 118 is formed, and a contact hole is formed. Then, a source wiring 119, a drain wiring 120, and a gate wiring 121 are formed and subjected to hydrogenation treatment, so that the thin film transistor illustrated in FIG. 4D is completed.

With the structure shown in this embodiment, the concentration of impurity ions remaining in the gate insulating film 108 and the trap level due to damage at the time of ion implantation can be reduced, so that the reliability of the thin film transistor is improved. be able to.

It is also possible to adopt a configuration in which the second ion implantation step as shown in FIG. 4C is not performed. In this case, the offset region is immediately below the dense anodic oxide film and the exposed gate insulating film 108. Such a configuration reduces the field-effect mobility of the thin film transistor,
Off current and leak current are extremely small.

[Embodiment 3] This embodiment shows an example in which the oxide film forming step by anodic oxidation in Embodiment 1 is performed by a plasma oxidation method. In this case, the state shown in FIG. 1D can be obtained by oxidizing the aluminum pattern 107 ′ in a plasma atmosphere using oxygen gas.

Since the plasma oxidation can be carried out by a usual dry etching apparatus, the etching of the metal film 107 and the insulating film 108 containing silicon as a main component as shown in FIG. All of the steps can be performed by a dry process similarly to the side etching step shown in FIG.

[Embodiment 4] As shown in Embodiment 1, when an aluminum film having high heat resistance is used as a gate electrode, an oxide film functioning as a protective layer on the surface of the gate electrode is not necessarily required. This is advantageous in that the oxide film is not removed when a contact hole is formed above the gate electrode later.

However, when manufacturing a semiconductor device having an HRD region (LDD region + offset region),
It is necessary to form an offset region by adding an impurity ion after forming an oxide film on at least the side surface of the gate electrode.

In such a case, an oxide film is formed in the state shown in FIG. 1C, that is, with the resist mask 106 left over the aluminum pattern 107 ', and the oxide film (protection) is formed only on the side surfaces of the gate electrode. Layer) may be formed. As an oxide film forming method, an anodic oxidation method or a plasma oxidation method may be used. In this case, it is preferable to use a plasma oxidation method.

In the case of using the plasma oxidation method, the processes up to the etching process of the metal film, the etching process of the insulating film containing silicon as a main component, the side etching process, and the oxide film forming process are all continuously performed in the dry etching apparatus. It is possible to do. Therefore, the manufacturing process can be simplified. In the case of a single-chamber apparatus, gas exchange is required. In the case of a multi-chamber apparatus, each process may be performed in each processing chamber.

Fifth Embodiment In the first embodiment, an example in which a substrate having an insulating film provided on a glass substrate, a quartz substrate, or the like is used as a substrate having an insulating surface. However, the present invention can be applied to a semiconductor device formed on a silicon substrate or a silicon wafer.

The present invention can be easily applied to an insulated gate field effect transistor (IGFET) formed on a silicon wafer using a normal IC process. Therefore, an IC chip or a VLSI circuit in which the IC chip is integrated can be configured. Further, for example, the TFT of the present invention can be used as a load element of an SRAM. Also, power MOSFET
It is also possible to apply the present invention to a high-power type semiconductor device as described above.

Further, the present invention relates to SOS (Silicon On Sapph).
ire) substrate, SIMOX (Separation by Implanted Ox)
ygen) It can be applied to an SOI substrate represented by a substrate or the like.

When an SOI substrate is used, single crystal silicon can be used as a semiconductor material for forming an active layer, so that a semiconductor device having excellent electric characteristics can be realized.

Such a semiconductor device (thin film transistor)
Since the active layer is made of single crystal silicon, the field effect mobility is extremely large, and the amount of flowing current is large. Therefore, a structure that suppresses deterioration like the HRD structure shown in the present invention is effective.

[Embodiment 6] A semiconductor device utilizing the present invention can be integrated on a glass substrate to produce an active matrix electro-optical device in which a drive circuit and a pixel matrix circuit are integrally formed on the same substrate. it can.

Examples of the electro-optical device include a transmission type or reflection type liquid crystal display device, an EL display device, and an EC display device. A semiconductor device using the present invention can be used as a switching element in a pixel region arranged in a matrix or can constitute a driving circuit for driving the switching element.

[Embodiment 7] In this specification, the term "semiconductor device" refers to "a device driven by using a semiconductor" in general, and the electro-optical device described in the fourth embodiment is also a "semiconductor device". Shall be included in the category.

Therefore, applied products (electronic devices) manufactured using the electro-optical device shown in the fourth embodiment and the integrated circuit (IC circuit, VLSI circuit) shown in the third embodiment are also “semiconductor devices”. It is included in the category.

Such applied products include a wide variety of electronic devices such as video cameras, still cameras, projections, portable information terminals (mobile computers, mobile phones, handy terminals, etc.), car navigation systems, and the like. In addition, it can also be used for head-mounted displays that attract attention in virtual reality.

As described above, the applicable range to which the present invention can be applied is extremely wide, and the effect of the present invention for simplifying the manufacturing process of those semiconductor devices and improving the production yield is very economically advantageous. Things.

[0069]

According to the present invention, the manufacturing process of a semiconductor device having an LDD structure or an HRD structure can be greatly simplified. Further, the production yield can be improved by reducing the number of manufacturing steps.

Further, since an oxide film for protecting the gate electrode (or the gate line) can be easily removed, it is possible to secure a reliable ohmic contact between the gate electrode and a gate wiring serving as an external terminal. . That is, a highly reliable semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a thin film transistor.

FIG. 2 illustrates a manufacturing process of a thin film transistor.

FIG. 3 is a diagram showing a manufacturing process of a conventional HRD structure.

FIG. 4 illustrates a manufacturing process of a thin film transistor.

[Explanation of symbols]

Reference Signs List 101 glass substrate 102 base film 103 active layer 104 insulating film containing silicon as a main component 105 aluminum or metal film containing aluminum as a main component 106 resist mask 107 aluminum pattern 108 gate insulating film 109 dense anodic oxide film 110 gate electrode 111, 112 Impurity region 113 Source region 114 Drain region 115, 116 Low concentration impurity region 117 Channel formation region 118 Interlayer insulating film 119 Source wiring 120 Drain wiring 121 Gate wiring

Claims (6)

[Claims] A first step of forming an active layer and a silicon-based insulating film covering the active layer on a substrate having an insulating surface; and forming an aluminum film on the silicon-based insulating film. A second step of forming a metal film made of a material containing aluminum as a main component; and a third step of selectively forming a resist mask on the metal film.
A fourth step of etching the metal film by a dry etching method; a fifth step of etching the insulating film containing silicon as a main component by a dry etching method; A sixth step of anisotropically etching; and a seventh step of adding an impurity ion imparting one conductivity to the active layer after removing the resist mask. A method for manufacturing a semiconductor device. 2. A first step of forming an active layer on a substrate having an insulating surface and an insulating film containing silicon as a main component and covering the active layer, and forming aluminum on the insulating film containing silicon as a main component. A second step of forming a metal film made of a material containing aluminum as a main component; and a third step of selectively forming a resist mask on the metal film.
A fourth step of etching the metal film by a dry etching method; a fifth step of etching the insulating film containing silicon as a main component by a dry etching method; A sixth step of anisotropically etching; a seventh step of forming an oxide film on the exposed surface of the metal film by anodic oxidation or plasma oxidation after removing the resist mask; An eighth step of adding an impurity ion imparting one conductivity by using a method for manufacturing a semiconductor device. 3. The method according to claim 2, wherein the oxide film formed in the seventh step has a thickness of 100 to 500 膜厚. 4. The method according to claim 1, wherein the fourth step is performed by a dry etching method using a chlorine-based gas, and the fifth step is performed by a dry etching method using a fluorine-based gas. A method for manufacturing a semiconductor device, comprising: 5. The method for manufacturing a semiconductor device according to claim 1, wherein the fourth and fifth steps are performed continuously without opening to the atmosphere. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the sixth step is performed by a wet etching method using a phosphoric acid-based solution.