JPH10173192A - Thin film transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce capacitance between a pair of gate electrodes and source/ drain regions, by forming the pair of gate electrodes on the top and bottom surfaces of a semiconductor thin film to sandwich a channel region comprising the semiconductor thin film between them, and by making their positions and shapes overlap with the position and shape of the channel region in plan view. SOLUTION: Forming a first gate electrode 12a on an insulation substrate 11, a first gate insulation film 13a such as a silicon oxide film is formed on the whole surfaces of the gate electrode 12a and insulation substrate 11. Forming thereon a semiconductor thin film, source/drain regions 15, 16 are formed in both side end regions of the semiconductor thin film to form a channel region 17 between the regions 15, 16. Further, forming a second insulation film 13b on the whole surface of the region including the semiconductor thin film, a second gate electrode 12b is formed thereon. Hereupon, the positions and shapes of the first and second gate electrodes 12a, 12b are made to overlap with the position and shape of the channel region 17 in plan view.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, an image sensor, a three-dimensional integrated circuit, and a thin film transistor (hereinafter, referred to as a TF) used for others.
In particular, the present invention relates to a TFT having a double gate structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art A TFT having a so-called double gate structure in which gate electrodes are provided on the upper and lower surfaces of a semiconductor thin film forming a channel region in order to increase the driving capability of the TFT is known. This double gate structure TFT will be described below with reference to the sectional view shown in FIG. In FIG. 5, a first gate electrode 2a made of a conductive material such as tantalum is formed in a predetermined shape on the surface of an insulating substrate 1 such as glass, quartz, or sapphire. A first gate insulating film 3a made of a silicon oxide film on the entire surface of the gate electrode 2a and the insulating substrate 1.
Is formed thereon, and a semiconductor thin film 4 such as amorphous silicon or polysilicon is formed in a predetermined shape at a location where the TFT is to be formed. Further, a second gate insulating film 3b made of a silicon oxide film is formed on the entire surface including the semiconductor thin film 4. A second gate electrode 2b made of aluminum is formed in a predetermined shape on the second gate insulating film 3b. After that, using the second gate electrode 2b as a mask, an impurity serving as a donor or an acceptor is doped with the semiconductor thin film 4.
To form a source region 5 and a drain region 6. The region immediately below the gate electrode where no impurity is added becomes the channel region 7. Since the structure of FIG. 5 includes gate electrodes on the upper and lower surfaces of the semiconductor thin film forming the channel region,
Inversion layers are formed on the upper and lower surfaces of the semiconductor thin film, and the space charge in the semiconductor thin film can be greatly reduced.
Can be increased when the transistor is turned on.

[0003]

SUMMARY OF THE INVENTION Double gate structure TF
In order to maximize the charge transport efficiency between the source and the drain, T needs to be arranged so that the gate electrode faces the entire channel region. Further, the gate electrodes formed on the upper and lower surfaces of the semiconductor thin film forming the channel region need to be arranged symmetrically with respect to the channel region and aligned. However, in practice, the first gate electrode formed below the semiconductor thin film must be formed before the semiconductor thin film is formed, assuming the TFT arrangement. Therefore, the first gate electrode is formed larger than the actual gate electrode and larger than the channel region. For this reason, the first gate electrode has a shape that partially overlaps the source region and the drain region, and a capacitance is generated in a portion where the first gate electrode overlaps the source region and the drain region, causing a delay. In addition, the deviation of the overlapping size between the first gate electrode and the source region and the drain region causes variation in characteristics between the elements, and slightly increases the alignment margin of the first gate electrode, the channel region, and the second gate electrode. There is a need. This hinders miniaturization of the TFT.

[0004]

According to the present invention, there is provided a thin film transistor according to the present invention, comprising: a source region and a drain region formed of a semiconductor thin film doped with an impurity serving as a donor or an acceptor; A channel region formed of a semiconductor thin film formed between the semiconductor thin film, a gate insulating film formed on upper and lower surfaces of the semiconductor thin film in contact with the semiconductor thin film, and sandwiching the semiconductor thin film via the gate insulating film. Wherein the position and shape of the pair of gate electrodes and the channel region overlap in plan view.

According to a second aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: forming a first gate electrode made of a material that does not transmit a light beam of a light source for resist exposure on a transparent insulating substrate; Forming a first gate insulating film made of a material that transmits the light beam on an insulating substrate, and forming a semiconductor thin film made of a material that transmits the light beam on the first gate insulating film; Forming a second gate insulating film made of a material that transmits the light beam on the semiconductor thin film, and forming a conductive film made of a material that transmits the light beam on the second gate insulating film; Exposing from the back surface of the insulating substrate to form a second gate electrode on the conductive film using the first gate electrode as a mask; and forming the semiconductor thin film using the second gate electrode as a mask. Characterized in that comprising the step of ion-implanting an impurity into.

According to a third aspect of the present invention, in the method of manufacturing a thin film transistor, after forming a sidewall on the side surface of the second gate electrode, an impurity is ion-implanted into the semiconductor thin film using the second gate electrode and the sidewall as a mask. Characterized by a step of performing

According to a fourth aspect of the present invention, in the method of manufacturing a thin film transistor, after forming the first gate insulating film, a source electrode and a drain electrode made of a material that transmits light or a material that does not transmit light are formed. Forming a semiconductor thin film, a second gate insulating film, and a second gate electrode sequentially;
Next, a step of ion-implanting impurities into the semiconductor thin film using the second gate electrode as a mask is provided.

According to the present invention, the position and shape of the pair of gate electrodes formed on the upper and lower surfaces of the semiconductor thin film so as to sandwich the channel region overlap the channel region in plan view. And the positions are aligned symmetrically, so that there is no need to provide an alignment margin between the first and second gate electrodes and the channel region. In addition, there is no portion where the first and second gate electrodes partially overlap the source region and the drain region, and the capacitance generated between the first and second gate electrodes and the source and drain regions can be reduced.
Therefore, the TFT can be miniaturized, the aperture ratio can be improved in the application to the active matrix type liquid crystal display device, the definition can be increased in the application to the image sensor, and the integration can be performed in the application to the three-dimensional integrated circuit. The degree can be improved.

Further, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
The second gate electrode is formed on the conductive film by self-alignment by exposing using the gate electrode as a mask, so that the first gate electrode and the second gate electrode can be formed at the same position and in the same shape.

Further, according to the present invention, since impurities are ion-implanted into the semiconductor thin film using the second gate electrode as a mask, the gate electrode and the channel region can be formed by so-called self-alignment. Since the second gate electrode is aligned, the first gate electrode, the second gate electrode, and the channel region can be formed so that their positions and shapes overlap in plan view.

Further, according to the present invention, a sidewall is formed on the side surface of the second gate electrode, and ions are implanted using the second gate electrode and the sidewall as a mask, so that a so-called LDD (Lightly Doped Drain) structure is formed. be able to.

[0012]

FIG. 1 shows a sectional structure of a double gate TFT according to an embodiment of the present invention. In FIG.
A base coat film made of an insulating film such as silicon nitride or tantalum oxide is formed on the surface of a transparent or translucent insulating substrate 11 made of glass, quartz, sapphire, or the like for the purpose of preventing impurities from the insulating substrate from being mixed. I do.
This base coat film may be formed as needed, and is not shown in FIG. On this insulating substrate, tantalum,
The first gate electrode 12a is formed by forming a metal conductive material such as chrome which does not transmit a light beam from the light source for exposure, into a predetermined shape. On the entire surface of the gate electrode 12a and the insulating substrate 11, a first gate insulating film 13a having a film thickness of 20 to 500 nm which transmits light of an exposure light source such as a silicon oxide film is formed, and amorphous silicon or polysilicon is formed thereon. A transparent or translucent semiconductor thin film 14 such as silicon or compound semiconductor having a thickness of 10 to 100 nm
It is formed in a predetermined shape at a portion where the FT is formed. Impurities serving as donors or acceptors are added to both side regions of the semiconductor thin film 14 to form a source region 15 and a drain region 16, and a channel region 17 is formed between the source region and the drain region. Further, a second gate insulating film 13b made of a silicon oxide film or the like which transmits light of an exposure light source and has a film thickness of 20 to 2
000 nm. This second gate insulating film 13
A transparent or translucent conductive film of ITO or the like having a thickness of 100 to 500 nm is deposited on the substrate b and formed into a predetermined shape to form a second gate electrode 12b. Here, the first gate electrode 12a and the second gate electrode 12b are formed such that the position and shape of the channel region overlap in plan view, and the center of the channel region coincides with the centers of the first and second gate electrodes. You. The control by two kinds of signals by applying different signals to the first and second gate electrodes may be performed by short-circuiting the first gate electrode and the second gate electrode as necessary and applying the same signal. May be. As described above, since the first gate electrode, the second gate electrode, and the channel region are formed so as to overlap in a plan view, the TFT can be miniaturized.

(Embodiment 1) Next, a manufacturing process of a double gate TFT of the present invention will be described with reference to FIG. First, a base coat film made of an insulating film such as silicon nitride or tantalum oxide is formed on the glass substrate 11 in order to prevent impurities from the glass substrate from being mixed. This base coat film may be formed as needed, and is not shown in FIG. On this glass substrate, a conductive film that does not transmit light from a light source for exposing the resist,
For example, a metal film such as tantalum or chromium is deposited to a thickness of 100 to 500 nm by a CVD method. This metal film is formed in a predetermined shape at the position of the lower gate electrode 12a by photolithography. This lower gate electrode 12a
And, on the entire surface of the glass substrate 11, a first gate insulating film 13a that transmits the light source of the exposure light source is formed. The first gate insulating film 13a has a thickness of 20 to 50 by a CVD method.
A silicon oxide film having a thickness of 0 nm is preferable (FIG. 2A).

An amorphous silicon film having a thickness of 10 to 100 nm is deposited thereon by using the CVD method. When a high-speed response of the TFT is required, the amorphous silicon film is irradiated with an excimer laser by sequential scanning to be crystallized to obtain polysilicon. Instead of using an excimer laser, heat treatment such as baking may be performed, or a combination of laser irradiation and heat treatment such as baking may be performed. Next, an amorphous silicon film or a polysilicon film is formed by photolithography at a position where a switching element of a pixel electrode is formed, a size necessary for forming a TFT,
The island-shaped semiconductor region 14a is patterned into a shape. FIG. 2B shows the entire surface including the island-shaped semiconductor region 14a.
As shown in (2), a second gate insulating film 13b that transmits light from the light source for exposure is formed. Second gate insulating film 13b
Is preferably a silicon oxide film having a thickness of 20 to 200 nm deposited by the CVD method. Silicon nitride can be used for the gate insulating film.

A transparent or translucent metal such as ITO, a transparent conductive film or a semiconductor thin film 12 such as amorphous silicon or polysilicon is formed on the entire surface, and a resist 18 is applied thereon. Then, exposure 19 is performed using the gate electrode 12a below the back surface of the glass substrate 11 as a photomask (FIG. 2C). Since the lower gate electrode 12a is made of a material that is opaque to the light of the light source for exposure, only the portion of the resist that does not have the lower gate electrode 12a is exposed and developed to develop the lower gate electrode 12a. The resist mask can be formed at the same position and shape in plan view. Dry etching or wet etching using this mask
The upper gate electrode 12b is formed as shown in FIG.
In order to apply the same signal by short-circuiting the lower gate electrode 12a and the upper gate electrode 12b, through holes are formed in the first and second gate insulating films 13a and 13b before forming the upper gate electrode. May be.

Next, using the upper gate electrode 12b as a mask, as shown in FIG. 2D, an impurity such as phosphorus or boron is selectively ion-added 20 by self-alignment using an ion doping method or the like. This is activated to form a source region 15 and a drain region 16. A channel region 17 is formed between the source region and the drain region that have not been ion-doped.

Thereafter, as shown in FIG. 2E, an insulating protective film 23 is formed, and aluminum, tantalum, titanium, chromium, molybdenum, copper, doped silicon, ITO, and alloys thereof are formed through contact holes. As a result, the source electrode 21 and the drain electrode 22 are led out. The insulating protective film may be an interlayer insulating film made of an organic material such as acrylic, polyimide, or polyimide amide, or an inorganic insulating film such as a silicon oxide film may be used.

(Embodiment 2) FIG. 3 shows another manufacturing method of the present invention. In FIG. 3, the lower gate electrode 12a and the first
Gate insulating film 13a, island-shaped semiconductor region 14a, second
Steps up to the formation of the gate insulating film 13b and the upper gate electrode 12b are omitted because they are the same as those in FIG. After the upper gate insulating film 12b is formed, as shown in FIG. 3A, a silicon oxide film is formed from TEOS (Tetra Ethoxy Ortho Silicate) as a raw material to a thickness of 20 to 150 nm, here 100 nm, by a method having good step coverage such as a CVD method. Is deposited. The thickness of the insulating film determines the width of the LDD structure. Thereafter, as shown in FIG. 3B, only the insulating film on the side surface of the upper gate electrode 12b is left by anisotropic etching. A so-called sidewall 24 is formed.

Thereafter, using the upper gate electrode 12b and the side wall 22 as a mask, as shown in FIG. 3B, an impurity such as phosphorus or boron is selectively ion-added 25 by self-alignment using an ion doping method or the like. Then, this is activated to form a source region 15a and a drain region 16a. A channel region 17a is formed between the source region and the drain region that have not been ion-doped. An LDD (Lightly Doped Drain) structure is formed between the source region 15a, the drain region 16a, and the channel region 17a immediately below the sidewall 22.

Thereafter, an insulating protective film is formed, and a source electrode and a drain electrode are formed of a conductive material such as aluminum through a contact hole.

(Embodiment 3) FIG. 4 shows still another manufacturing method of the present invention. In FIG. 4, the lower gate electrode 12
a, the steps up to the formation of the first gate insulating film 13a are the same as those in FIG. After forming the first gate insulating film 13a, as shown in FIG. 4A, the source electrode 21a and the drain electrode 22a are patterned with an opaque conductive material such as tantalum or titanium.
Then, a semiconductor thin film of silicon or the like is deposited thereon by using the CVD method, and the island-shaped semiconductor region 14a is formed by patterning. Subsequent steps are the same as those of the first and second embodiments. A second gate insulating film 13b is formed, a transparent or translucent conductive film is formed thereon, and a gate lower than the back surface of the glass substrate 11 is formed. Exposure, development, and etching are performed using the electrode 12a as a photomask to form the upper gate electrode 12b. After that, using the upper gate electrode 12b as a mask, impurities are added by ions to form the source region 15 and the drain region 16. The channel region 17 is between the source region and the drain region that have not been ion-doped.
This structure is shown in FIG.

In FIG. 4A, when the source electrode 21a and the drain electrode 22b are formed using a transparent material such as ITO or a translucent material such as amorphous silicon, FIG. The structure shown is obtained.

[0023]

According to the present invention, the position and the shape of the pair of gate electrodes formed on the upper and lower surfaces of the semiconductor thin film so as to sandwich the channel region overlap the channel region in plan view. And the positions are aligned symmetrically with respect to, so that there is no need to provide an alignment margin between the first and second gate electrodes and the channel region. In addition, there is no portion where the first and second gate electrodes partially overlap the source region and the drain region, and the capacitance generated between the first and second gate electrodes and the source and drain regions can be reduced. Therefore, the TFT can be miniaturized, the aperture ratio can be improved in the application to the active matrix type liquid crystal display device, the definition can be increased in the application to the image sensor, and the integration can be performed in the application to the three-dimensional integrated circuit. The degree can be improved.

Also, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
The second gate electrode is formed on the conductive film by self-alignment by exposing using the gate electrode as a mask, so that the first gate electrode and the second gate electrode can be formed at the same position and in the same shape.

Further, according to the present invention, since impurities are ion-implanted into the semiconductor thin film using the second gate electrode as a mask, the gate electrode and the channel region can be formed by so-called self-alignment. Since the second gate electrode is aligned, the first gate electrode, the second gate electrode, and the channel region can be formed so that their positions and shapes overlap in plan view.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a thin film transistor of the present invention.

FIG. 2 is a diagram for explaining a method of manufacturing a thin film transistor according to the present invention in the order of steps.

FIG. 3 is a diagram for explaining a manufacturing method according to another embodiment of the present invention in the order of steps.

FIG. 4 is a view for explaining a manufacturing method according to still another embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the structure of a conventional thin film transistor.

[Explanation of symbols]

 Reference Signs List 11 insulated (glass) substrate 12a first (lower) gate electrode 13 first gate insulating film 14 semiconductor thin film 15 source region 16 drain region 17 channel region 13b second gate insulating film 12b second (upper) gate electrode 18 Resist 19 Exposure 20, 25 Ion implantation 21 Source electrode 22 Drain electrode 23 Insulating film 24 Side wall 26 Insulating protective film

(72) Inventor Hiromi Nishino 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation

Claims (4)

[Claims] A source region and a drain region formed of a semiconductor thin film to which an impurity serving as a donor or an acceptor is added; a channel region formed of the semiconductor thin film formed between the source region and the drain region; A thin film transistor comprising a gate insulating film formed on the upper and lower surfaces of the semiconductor thin film, and a pair of gate electrodes formed so as to sandwich the semiconductor thin film with the gate insulating film interposed therebetween. A liquid crystal display device wherein the positions and the shapes of the liquid crystal display overlap in a plan view. 2. A step of forming a first gate electrode made of a material that does not transmit a light beam of a light source for resist exposure on a transparent insulating substrate, and a material including the first gate electrode and transmitting the light beam on an insulating substrate. Forming a first gate insulating film comprising: forming a semiconductor thin film made of a material that transmits the light beam on the first gate insulating film; and forming a material transmitting the light beam on the semiconductor thin film. Forming a second gate insulating film comprising: forming a conductive film made of a material that transmits the light beam on the second gate insulating film; exposing the back surface of the insulating substrate to light; Forming a second gate electrode on the conductive film using the one gate electrode as a mask; and ion-implanting impurities into the semiconductor thin film using the second gate electrode as a mask. A method for manufacturing a thin film transistor. 3. The method according to claim 1, further comprising, after forming a sidewall on a side surface of the second gate electrode, implanting impurities into the semiconductor thin film using the second gate electrode and the sidewall as a mask. Item 3. A method for manufacturing a thin film transistor according to Item 2. 4. After forming the first gate insulating film, a source electrode and a drain electrode made of a material that transmits or does not transmit the light beam are formed, and thereafter, the semiconductor thin film, the second gate insulating film, and the second electrode are formed. 3. The method of manufacturing a thin film transistor according to claim 2, further comprising the step of sequentially forming a gate electrode, and then ion-implanting an impurity into the semiconductor thin film using the second gate electrode as a mask.