JPH10173190A - Thin film transistor and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To provide a thin film transistor having a low OFF current, a small variation in element characteristics, and high reproducibility. SOLUTION: A gate electrode 8 is formed on a polysilicon thin film 50 having a channel region 56 and a source / drain region 55 via first and second gate insulating films 60, 70.
0, the first gate insulating film 60 is not provided on the central portion of the channel region 56 except for the vicinity of the source / drain region 55, and the thickness of the gate insulating film is set to be larger than that on the central portion of the channel region 56. The vicinity of the source / drain region 55 is thickened. As a result, the capacitance per unit area of the gate insulating film becomes smaller in the vicinity of the source / drain region 55 than in the central portion on the channel region 56, and an excessive gate electric field is not applied in the vicinity of the source / drain region 55. , The OFF current is reduced. Further, by a simple method of removing the first gate insulating film 60 on the central portion of the channel region 56,
The thickness of the gate insulating film can be adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for a liquid crystal display or an image sensor, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In order to reduce the OFF current of a thin film transistor (TFT), which is one unit of a thin film transistor array used for a liquid crystal display device or an image sensor, a thin film transistor having an LDD structure or an offset structure has been conventionally proposed. (JP-A-5-136417 and JP-A-5-136418). The LDD structure is an abbreviation of Lightly Doped Drain, which is provided with a region with a low concentration around the diffusion layer to reduce the electric field at the source and drain ends. In the thin film transistor having the offset structure, a certain distance is provided between the end of the gate electrode and the source / drain region as a planar structure, and a similar effect is obtained.

[0003]

In the conventional thin film transistor having the LDD structure and the offset structure, it is necessary to use another photolithography process separately from the formation of the diffusion region in order to form the LDD region and the offset region. Yes, photolithography accuracy (mask alignment accuracy +
(Etching accuracy), the TFT characteristics changed greatly, the device characteristics varied widely, and the reproducibility was poor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor having a low OFF current, a small variation in element characteristics and a high reproducibility, and a method for manufacturing the same.

[0005]

According to a first aspect of the present invention, there is provided a thin film transistor comprising: a semiconductor layer having a channel region and a source / drain region formed on an insulating substrate; and a gate electrode formed on the semiconductor layer via a gate insulating film. Wherein the thickness of the gate insulating film is greater in the vicinity of the source / drain region than in the center of the channel region.

According to this structure, the thickness of the gate insulating film is made thicker in the vicinity of the source / drain region than on the central part of the channel region, so that the capacitance per unit area of the gate insulating film is reduced. From the center on the channel area
The area near the drain region is smaller, and an excessive gate electric field is not applied near the source / drain region, and the OFF current is lower. In addition, since the thickness of the gate insulating film is merely adjusted as described above, a thin film transistor with little variation in element characteristics and high reproducibility can be realized, and the manufacturing yield can be improved.

According to a second aspect of the present invention, in the thin film transistor according to the first aspect, the gate insulating film includes a first gate insulating film formed on the semiconductor layer and a first gate insulating film formed on the first gate insulating film. And a portion where the first gate insulating film or the second gate insulating film is not formed is provided over the central portion of the channel region of the semiconductor layer.

According to this structure, the thickness of the gate insulating film can be easily increased in the vicinity of the source / drain region than in the central portion of the channel region. The thin film transistor according to claim 3, wherein a semiconductor layer having a channel region and a source / drain region is formed on an insulating substrate, and a gate electrode is formed on the semiconductor layer via a gate insulating film. The dielectric constant of the insulating film
The present invention is characterized in that the vicinity of the source / drain region is made smaller than the upper part of the channel region.

According to this structure, the dielectric constant of the gate insulating film is made smaller in the vicinity of the source / drain region than on the central portion of the channel region, so that the capacitance per unit area of the gate insulating film is reduced. Source from the center of the area
The area near the drain region is smaller, and an excessive gate electric field is not applied near the source / drain region, and the OFF current is lower. In addition, since the dielectric constant of the gate insulating film is merely adjusted as described above, a thin film transistor with little variation in element characteristics and high reproducibility can be realized, and the manufacturing yield can be improved.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: forming a semiconductor layer to be a channel region and a source / drain region on an insulating substrate; Forming a first gate insulating film, forming a second gate insulating film on the first gate insulating film and the semiconductor layer, and forming first and second gate insulating films on a channel region of the semiconductor layer And a step of introducing impurities into the source / drain regions of the semiconductor layer using the gate electrode as a mask.

According to this manufacturing method, the first gate insulating film is formed on the semiconductor layer except for the central portion of the channel region, and the second gate insulating film is formed on the first gate insulating film and the semiconductor layer. The gate insulating film can be made thicker in the vicinity of the source / drain region than in the central part of the channel region, the OFF current is low, and the variation in device characteristics is small and the reproducibility Thin film transistor can be realized, and the manufacturing yield can be improved.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, wherein a semiconductor layer serving as a channel region and a source / drain region is formed on an insulating substrate, and a first gate insulating film is formed on the semiconductor layer. Forming a second gate insulating film on a region of the semiconductor layer of the first gate insulating film other than a central portion of the channel region; and forming first and second gate insulating films on the channel region of the semiconductor layer. The method includes a step of forming a gate electrode through a film, and a step of introducing impurities into source / drain regions of the semiconductor layer using the gate electrode as a mask.

According to this manufacturing method, the first layer is formed on the semiconductor layer.
Of the gate insulating film by a simple method of forming a second gate insulating film on a region of the semiconductor layer of the first gate insulating film other than the central part of the channel region. Can be made thicker in the vicinity of the source / drain regions than above the central part of the channel region, and a thin film transistor with low OFF current, small variation in element characteristics and high reproducibility can be realized, and the production yield can be improved.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: forming a semiconductor layer serving as a channel region and a source / drain region on an insulating substrate; forming a gate insulating film on the semiconductor layer; A step of etching the gate insulating film on the central portion of the channel region of the layer to reduce the thickness, a step of forming a gate electrode on the channel region of the semiconductor layer via the gate insulating film, and using the gate electrode as a mask. Introducing an impurity into the source / drain regions of the semiconductor layer.

According to this manufacturing method, the thickness of the gate insulating film is reduced by etching the gate insulating film on the central portion of the channel region of the semiconductor layer. The vicinity of the source / drain region can be made thicker than above, a thin film transistor with low OFF current, small variation in element characteristics, and high reproducibility can be realized, and the manufacturing yield can be improved.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: forming a semiconductor layer to be a channel region and a source / drain region on an insulating substrate; 1st with low rate
Forming a second gate insulating film having a large dielectric constant on the central portion of the channel region of the semiconductor layer; and forming first and second gate insulating films on the channel region of the semiconductor layer. The method includes a step of forming a gate electrode via an insulating film and a step of introducing impurities into source / drain regions of the semiconductor layer using the gate electrode as a mask.

According to this manufacturing method, the first gate insulating film having a small dielectric constant is formed on a region other than the central portion of the channel region of the semiconductor layer, and the first gate insulating film is formed on the central portion of the channel region of the semiconductor layer. By a simple method of forming a large second gate insulating film, the dielectric constant of the gate insulating film can be made smaller in the vicinity of the source / drain region than above the central part of the channel region, so that the OFF current is low and the device characteristics are reduced. And a highly reproducible thin film transistor can be realized, and the manufacturing yield can be improved.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a process sectional view showing a method of manufacturing a thin film transistor according to a first embodiment of the present invention.

As shown in FIG. 1E, the thin film transistor according to the first embodiment has a polycrystalline structure having a channel region 56 and a source / drain region 55 on an insulating film 20 formed on the surface of a glass substrate 10. A silicon thin film (semiconductor layer) 50 is provided.
A gate electrode 80 is provided via the second gate insulating films 60 and 70, and a source / drain electrode 95 connected to the source / drain region 55 via a contact hole is provided on the insulating film 90 formed on the entire surface. . The first gate insulating film 60 is not provided on the central portion of the channel region 56 except for the vicinity of the source / drain region 55, that is, on the central portion of the channel region 56, where the first gate insulating film 60 is not formed. The gate insulating film (60, 70)
Is thicker in the vicinity of the source / drain region 55 than on the central portion of the channel region 56.

A method for manufacturing the thin film transistor having the above structure will be described below. First, an insulating film 20 such as silicon oxide is formed on a low alkali glass substrate 10 such as 7059 or 1737 by Corning Co., Ltd.
Deposit 00 nm. An amorphous silicon thin film 30 is formed thereon by plasma CVD or sputtering to a thickness of 30 nm to 8 nm.
Deposit 5 nm (FIG. 1A).

Thereafter, the amorphous silicon thin film 30 is crystallized by an excimer laser or an argon laser, and is patterned into an island-shaped polysilicon thin film 50. A silicon oxide film is formed thereon as a first gate insulating film 60 by CVD.
Deposit 100 to 200 nm by the method (Fig. 1
(B)). Next, the first gate insulating film 60 on the central portion of the polysilicon thin film 50 except for the vicinity of the source / drain regions 55 of the channel region 56 is removed by etching, and a second gate insulating film 70 is formed thereon (FIG. FIG. 1 (c)). As the second gate insulating film 70, silicon oxide, tantalum oxide, aluminum oxide (alumina), silicon nitride, or the like is used.

Then, aluminum or an aluminum alloy is formed as the gate electrode 80 by sputtering at a thickness of 3000.
Deposit to a degree and pattern. Then, the gate electrode 8
Using 0 as a mask, an impurity such as phosphorus or boron is introduced into a part of the polysilicon thin film 50 by an ion implantation method to form a source / drain region 55, and a region immediately below the gate electrode 80 where the impurity is not introduced is a channel region. 56 (FIG. 1D).

Next, for example, a silicon oxide film having a thickness of 200 nm or more is deposited as the insulating film 90, and after forming a contact hole, a source / drain electrode 95 is formed of aluminum or an aluminum alloy (FIG. 1E). As described above, according to this embodiment, the gate insulating film (6
0, 70) is made thicker in the vicinity of the source / drain region 55 than in the center of the channel region 56,
The capacitance per unit area of the gate insulating film (60, 70) is smaller in the vicinity of the source / drain region 55 than in the central portion on the channel region 56, and an excessive gate electric field is generated in the vicinity of the source / drain region 55. , And the OFF current is reduced. Further, the first gate insulating film 60 on the central portion of the channel region 56 except for the vicinity of the source / drain regions 55 is removed by etching, and the second gate insulating film 70 is formed thereon, so that the gate can be easily formed. Insulating film (60, 7
0), the film thickness of the source
Since the vicinity of the drain region 55 can be thickened,
It is possible to realize a thin film transistor with small variation in element characteristics and high reproducibility, and it is possible to improve the production yield.

In this embodiment, the first gate insulating film 60 is provided with a non-formed portion where the upper part of the channel region 56 is removed, but the first gate insulating film 60 is provided with a non-formed portion. The same effect can be obtained by providing the second gate insulating film 70 with a non-formed portion where the upper part of the channel region 56 is removed without providing the second gate insulating film 70. [Second Embodiment] FIG. 2 is a process sectional view showing a method of manufacturing a thin film transistor according to a second embodiment of the present invention.

As shown in FIG. 2D, the thin film transistor according to the second embodiment has a poly-channel having a channel region 156 and a source / drain region 155 on an insulating film 120 formed on the surface of a glass substrate 110. A silicon thin film (semiconductor layer) 150 is provided.
A gate electrode 180 is formed on the gate electrode 180 via a gate insulating film 160.
And a source / drain electrode 195 connected to the source / drain region 155 via a contact hole is provided on the insulating film 190 formed on the entire surface. The thickness of the gate insulating film 160 is reduced above the central portion of the channel region 156 and is increased near the source / drain region 155.

A method for manufacturing the thin film transistor having the above structure will be described below. First, an insulating film 120 made of silicon oxide or the like is deposited to a thickness of 100 nm to 200 nm on a low alkali glass substrate 110 such as 7059 or 1737 manufactured by Corning, using a CVD method as an undercoating film. Amorphous silicon thin film 1
30 to 30 nm using a plasma CVD method or a sputtering method.
Is deposited to a thickness of 85 nm (FIG. 2A).

After that, the amorphous silicon thin film 130 is crystallized by an excimer laser or an argon laser, and is patterned into an island-shaped polysilicon thin film 150. A silicon oxide, tantalum oxide, aluminum oxide or silicon nitride film is formed thereon as a gate insulating film 160 by CV.
200 by D method, plasma CVD method or sputtering method
Deposited by about nm (FIG. 2B).

Next, a portion of the gate insulating film 160, that is, a portion on the central portion of the polysilicon thin film 150 except for the vicinity of the source / drain region 155 of the channel region 156 is etched to reduce the thickness of the portion. . Thereafter, aluminum or an aluminum alloy is deposited as a gate electrode 180 by sputtering at about 3000 ° and patterned. Thereafter, using the gate electrode 180 as a mask, an impurity such as phosphorus or boron is introduced into a part of the polysilicon thin film 150 by an ion implantation method to form a source / drain region 155. The impurity immediately below the gate electrode 180 is not introduced. The region becomes the channel region 156 (FIG. 1)
(C)).

Next, a silicon oxide film, for example, having a thickness of 200 nm or more is deposited as the insulating film 190, and after forming a contact hole, a source / drain electrode 195 is formed of aluminum or an aluminum alloy (FIG. 1D).
As described above, according to this embodiment, the gate insulating film 160 on the central portion of the channel region 156 of the polysilicon thin film 150 is etched to reduce the film thickness. Channel region 1 thickness
The vicinity of the source / drain region 155 can be made thicker than the upper part of the center 56, and the same effect as in the first embodiment can be obtained.

In this embodiment, the gate insulating film 160 is formed of a single-layer insulating film. However, the gate insulating film 160 may be formed of a plurality of types of multilayer insulating films. [Third Embodiment] FIG. 3 is a process sectional view showing a method of manufacturing a thin film transistor according to a third embodiment of the present invention.

As shown in FIG. 3E, the thin film transistor according to the third embodiment has a polycrystalline structure having a channel region 256 and a source / drain region 255 on an insulating film 220 formed on the surface of a glass substrate 210. A silicon thin film (semiconductor layer) 250 is provided.
First and second gate insulating films 260 and 270 on
, And a source / drain electrode 295 connected to the source / drain region 255 via a contact hole is provided on an insulating film 290 formed on the entire surface. A second gate insulating film 270 is formed on the central portion of the channel region 256 except for the vicinity of the source / drain region 255.
Is provided, and the first gate insulating film 260 is provided in the other region. When the dielectric constant of the first gate insulating film 260 is ε ₁ and the dielectric constant of the second gate insulating film 270 is ε ₂ , Ε ₁ <ε ₂ , the permittivity of the gate insulating film in the vicinity of the source / drain region 255 is reduced from above the central portion of the channel region 256.

A method for manufacturing the thin film transistor having the above structure will be described below. First, an insulating film 220 made of silicon oxide or the like is formed on a low alkali glass substrate 210 such as 7059 or 1737 manufactured by Corning Inc. by using a CVD method as an undercoating film.
Deposit 00 nm. An amorphous silicon thin film 230 is formed thereon.
Is deposited to a thickness of 30 nm to 85 nm using a plasma CVD method or a sputtering method (FIG. 3A).

After that, the amorphous silicon thin film 230 is crystallized by an excimer laser or an argon laser, and is patterned to form an island-shaped polysilicon thin film 250. On this, a silicon oxide film is deposited as a first gate insulating film 260 from 100 nm to 200 nm. Thereafter, the first gate insulating film 2 on the central portion of the polysilicon thin film 250 except for the vicinity of the source / drain region 255 of the channel region 256 is formed.
60 is removed by etching (FIG. 3B).

Next, a second gate insulating film 270 is formed. At this time, as the second gate insulating film 270, silicon oxide, tantalum oxide, aluminum oxide (alumina), silicon nitride, or the like is formed on the entire surface, and then, for example, is etched back to remove the first gate insulating film 260 at the removed portion. The second gate insulating film 270 is left over the central part of a certain channel region 256 (FIG. 3C).

Next, aluminum or an aluminum alloy is used as the gate electrode
Deposit about Å and pattern. Then, using the gate electrode 280 as a mask, an impurity such as phosphorus or boron is introduced into a partial region of the polysilicon thin film 250 by an ion implantation method to form a source / drain region 255.
A region immediately below 80 where the impurity is not introduced becomes the channel region 256 (FIG. 3D).

Next, as the insulating film 290, for example, silicon oxide
Recon film is deposited over 200nm and contact hole is
After forming, it is made of aluminum or aluminum alloy.
The source / drain electrode 295 is formed (see FIG.
(E)). Note that as the first gate insulating film 260,
For example, the dielectric constant ε₁Thermal oxide film or sputtering method
And TEOS-CVD SiO_Two(Eg ε₁But
3.7), and as the second gate insulating film 270,
For example, the dielectric constant ε_TwoSiO by atmospheric pressure CVD method
_Two(Eg ε_TwoUses 4.6). In addition, the first and second
Gate insulating films 260 and 270 having a dielectric constant of 3.7 to
4.6 SiO_TwoAnd ε₁<Ε_TwoShould be fine. Ma
The dielectric constant ε is used as the first gate insulating film 260. ₁Is 3.
7-4.6 SiO_Two, The second gate insulating film 27
0, TaO_X(Ε_Two= 23), Al_TwoO_Three(Ε_Two
= 9-10) or SiN_X(Ε_Two= 6-7.5)
May be used.

As described above, according to this embodiment, the second gate insulating film 270 is formed on the central portion of the channel region 256.
Is provided, and a first gate insulating film 260 is provided in other regions, and a second gate insulating film 260 provided on a central portion of the channel region 256 is provided.
By making the dielectric constant of the first gate insulating film 260 near the source / drain region 255 smaller than the dielectric constant of the gate insulating film 270, the gate insulating films (260, 27
0) is the capacitance per unit area of the channel region 256.
The vicinity of the source / drain region 255 is smaller than the upper central portion, and an excessive gate electric field is not applied near the source / drain region 255, and the OFF current is reduced. Also,
First and second gate insulating films 26 made of materials having different dielectric constants
By forming 0, 270, the dielectric constant of the gate insulating film (260, 270) can be easily made smaller in the vicinity of the source / drain region 255 than in the central part of the channel region 256. And a highly reproducible thin film transistor can be realized, and the manufacturing yield can be improved.

In this embodiment, the order of forming the first gate insulating film 260 and the second gate insulating film 270 may be reversed. The processing method may be a normal photolithography and etching technique, or may be a flattening technique such as an etch-back method using a photoresist and a dry etching apparatus or a CMP (chemical mechanical polish).

[0039]

According to the present invention, the thickness of the gate insulating film is made thicker in the vicinity of the source / drain region than on the central portion of the channel region, or the dielectric constant of the gate insulating film is made larger in the channel region. By making the vicinity of the source / drain region smaller than on the central portion, the capacitance per unit area of the gate insulating film becomes larger than the source / drain region on the channel region.
The area near the drain region is smaller, and an excessive gate electric field is not applied near the source / drain region, and the OFF current is lower. Further, since only the thickness or the dielectric constant of the gate insulating film is adjusted as described above, a thin film transistor with little variation in element characteristics and high reproducibility can be realized, and the production yield can be improved.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a process sectional view illustrating a method for manufacturing a thin film transistor according to a second embodiment of the present invention.

FIG. 3 is a process sectional view illustrating a method for manufacturing a thin film transistor according to a third embodiment of the present invention.

[Explanation of symbols]

 10, 110, 210 Glass substrate 20, 120, 220 Insulating film 30, 130, 230 Amorphous silicon thin film 50, 150, 250 Polysilicon thin film (semiconductor layer) 55, 155, 255 Source / drain region 56, 156, 256 Channel region 60, 260 First gate insulating film 70, 270 Second gate insulating film 160 Gate insulating film 80, 180, 280 Gate electrode 90, 190, 290 Insulating film 95, 195, 295 Source / drain electrode

Claims (7)

[Claims] 1. A thin film transistor comprising: a semiconductor layer having a channel region and a source / drain region formed on an insulating substrate; and a gate electrode formed on the semiconductor layer via a gate insulating film. A thickness of the thin film transistor in the vicinity of the source / drain region is larger than that in a central portion of the channel region. 2. The semiconductor device according to claim 1, wherein the gate insulating film includes a first gate insulating film formed on the semiconductor layer, and a second gate insulating film formed on the first gate insulating film. 2. The thin film transistor according to claim 1, wherein a portion where the first gate insulating film or the second gate insulating film is not formed is provided on a central portion of the region. 3. A thin film transistor comprising: a semiconductor layer having a channel region and a source / drain region formed on an insulating substrate; and a gate electrode formed on the semiconductor layer via a gate insulating film. Wherein the dielectric constant of the thin film transistor is smaller in the vicinity of the source / drain region than in the center of the channel region. 4. A step of forming a semiconductor layer serving as a channel region and a source / drain region on an insulating substrate, and a first step on a region of the semiconductor layer excluding a central portion of the channel region.
Forming a second gate insulating film on the first gate insulating film and the semiconductor layer; forming the first and second gate insulating films on a channel region of the semiconductor layer; Forming a gate electrode via a gate insulating film; and forming a source electrode of the semiconductor layer using the gate electrode as a mask.
Introducing an impurity into the drain region. 5. A step of forming a semiconductor layer to be a channel region and a source / drain region on an insulating substrate; a step of forming a first gate insulating film on the semiconductor layer; Forming a second gate insulating film on a region of the film except for a central portion of the channel region of the semiconductor layer; and forming the second gate insulating film on the channel region of the semiconductor layer via the first and second gate insulating films. Forming a gate electrode, and using the gate electrode as a mask, a source electrode of the semiconductor layer.
Introducing an impurity into the drain region. 6. A step of forming a semiconductor layer to be a channel region and a source / drain region on an insulating substrate; a step of forming a gate insulating film on the semiconductor layer; and a central part of the channel region of the semiconductor layer. Etching the gate insulating film thereon to reduce the film thickness, forming a gate electrode on the channel region of the semiconductor layer via the gate insulating film, and forming the semiconductor layer using the gate electrode as a mask. Source
Introducing an impurity into the drain region. 7. A step of forming a semiconductor layer to be a channel region and a source / drain region on an insulating substrate; and a first gate insulating film having a small dielectric constant on a region of the semiconductor layer excluding a central portion of the channel region. Forming a film; forming a second gate insulating film having a large dielectric constant on a central portion of the channel region of the semiconductor layer; and forming the first and second gates on the channel region of the semiconductor layer. Forming a gate electrode via an insulating film; and using the gate electrode as a mask to form a source electrode of the semiconductor layer.
Introducing an impurity into the drain region.