JPH10172294A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with a column redundancy system with a high failure rescue efficiency without increasing a chip size drastically. SOLUTION: In a overlaid DQ bus type DRAM, a group of eight cell array blocks located at the upper side of a row decoder 24 are set to be a group of cell array blocks 10-1 and a group of eight cell array blocks located at the lower part of the row decoder are set to be a group of cell any blocks 10-2. A group of spare columns 11-1 and 11-2 are provided adjacent to each of a group of cell array blocks 10-1 and 10-2. Each of 64 multiplexers that receives each of the output of DQ buffer 13-1 (13-1 (0) to (31), 13-2 (13-2 (0) to (31)) are constituted of a three versus one multiplexer 34 (34-0 to 63) and the failed column of a group of cell any blocks 10-1 can be substituted with either of a group of spare columns 11-1 and 11-2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory architecture, and more particularly to an overlaid D memory.
Multi-bit output D with Q bus (overlaid-DQ bus)
The present invention relates to a semiconductor memory circuit applied to a RAM.

[0002]

2. Description of the Related Art FIG. 12 is a circuit block diagram showing a main part of an overlaid DQ bus type 4M bit DRAM. In this example, by arranging 16 memory cell arrays consisting of 256 rows and 1024 columns in a block unit (referred to as a cell array block), a 4-Mbit D
It constitutes a RAM. Of the 16 cell array blocks, two cell array blocks (for example, hatched) separated by the row decoder 24 are simultaneously activated. The selection of the cell array to be activated is performed by the upper three bits (AR8 to 10) of the row address signal input (11 bits of AR0 to AR10).

In FIG. 12, the eight cell array block groups above the row decoder 24 are referred to as a cell array block group 10-1, and the eight cell array block groups below the row decoder are referred to as a cell array block group 10-2. I do. Spare column group 11 composed of four columns in which spare memory cell columns are arranged adjacent to cell array block group 10-1
-1 is provided. A spare column group 11-2 including four spare columns in which spare memory cell columns are arranged is provided adjacent to the cell array block group 10-2.

The spare column group 11-1 is a column redundancy selected when a defective column exists in the cell array block group 10-1 instead of the defective column. The spare column group 11-2 is a column redundancy selected when a defective column exists in the cell array block group 10-2, instead of the defective column.

[0005] 256 pairs of DQ buses (regular DQ bus: D
Q0 to 255, / DQ0 to 255 and DQ256 to 511, / D
Q256-511 (The leading / means a complementary signal with a bar on the top in the figure, and thereafter, the leading / also has a bar on the top in the figure for other signals as well.) , Above each of the cell array block groups 10-1 and 10-2,
It is provided along the column direction. Spare column group
Above each of 11-1 and 11-2, a pair of spare DQ buses (S1DQ, / S1DQ and S2DQ, / S2
DQ) is provided along the column direction. These DQs
The bus is electrically connected to a column of each cell array block via a column switch described later in order to read column data according to a column address signal input.

As described above, the DQ is overlapped with the cell array.
The configuration in which the buses are arranged is called an overlaid DQ bus architecture. This overlaid DQ bus architecture has a configuration in which the chip size does not increase as much as possible and can connect a large number of DQ buses to the activated cell array block. Bit output D
Suitable for RAM.

The DQ bus (512 pairs in total) is connected to multiplexers 12-1 and 12-2 (8-to-1 multiplexers 12-1 (0) to 12-1).
(31), 12-2 (0) to (31)) and DQ buffers 13-1, 13-2
(13-1 (0) to (31), 13-2 (0) to (31)), and further, a two-to-one multiplexer 14-1 (0) to (31), 14-2 (0) to (31) Are connected to 64 pairs of RWD buses. This RWD bus is
64-bit input / output data is exchanged with the outside of the memory via the data input / output buffer 15.

On the other hand, spare DQ buses S1DQ, / S1D
Q is connected in parallel via the spare DQ buffer 16-1 to be one input of each of the two-to-one multiplexers 14-1 (0) to (31). Spare DQ bus S2DQ, / S2DQ
Are connected in parallel via a spare DQ buffer 16-2 to be one input of each of the two-to-one multiplexers 14-2 (0) to (31).

The two-to-one multiplexers 14-1 (0) to (3)
1), 14-2 (0) to (31) are spare column hit determination circuits 17
64-bit signals SH1 (0) to SH (31), SH
2 (0) to (31) control whether to select a proper DQ bus and DQ buffer or to select a spare DQ bus and spare DQ buffer. Spare column hit judgment circuit
17 is an input column address signal (AC0-4)
Performs the above-described control depending on whether or not the address matches a pre-programmed defective column address.

FIG. 13 is a circuit block diagram showing in more detail the portion from the cell array block of FIG. 12 to the RWD bus on the data input / output side.
The 10-1 side (including the spare column group 11-1) is shown as a representative.
In FIG. 13, a spare column group 11-1 includes four spare column pairs (S1BL (0) to (3), / S1BL (0) to (3)) to which a plurality of memory cells (not shown) are connected. ), Which are connected via a column switch to a pair of spare DQs.
It is connected to the bus (S1DQ, / S1DQ). The four spare column pairs have spare column switch selection signals (S
1SW (0) to (3)). S / A is a sense amplifier.

In a normal cell array block, a DQ bus is provided at a ratio of one pair for four column pairs. That is, 256 pairs of DQ buses are arranged corresponding to 1024 column pairs in the cell array block. A pair of D
A Q bus (for example, DQ0, / DQ0) has four column pairs (BL0-3, / BL0-3) via column switches.
) Is connected.

The four column pairs are selected by column switch selection signals SW0 to SW3. As shown in FIG. 13, the column switch selection signals SW0 to SW3 include two least significant bits AC0 and AC1 (internal column address signals AC0I and AC1I) of a column address signal and three bits for selecting a cell array block. The row address signals AR8, AR9, AR10 are decoded by the logical product of the internal row address signals AR8I, AR9I, AR10I. Note that ACiI, / ACiI (i
= 0, 1), ACRjI, / ARjI (j = 8, 9, 1)
0) are the column address signals AC0 to AC0 shown in FIG.
Part of the complementary signal generated by the column address buffer 25 from the input of AC4, and part of the complementary signal generated by the row address buffer 22 from the input of the row address signals AR0 to AR10.

The 256 pairs of DQ buses on the cell array block are multiplexed every 8 pairs by an 8: 1 multiplexer. For example, the DQ bus DQ in FIG.
0 to 7 and / DQ0 to 7 are output from the 8: 1 multiplexer 12-1.
Multiplexed by (0).

The 8-to-1 multiplexer 12 (12-1 (0) to (3
1), 12-2 (0) to (31)), a 3-bit selection signal DQM
UX0 to UX2 determine which of the eight DQ bus pairs to select. Here, DQMUX0 to DQMUX2 have upper 3 bits (AC2 to AC2) in 5 bits of the column address signal.
4) is assigned. That is, DQMUX0 to DQMUX2 correspond to internal column address signals AC2I to AC4I, respectively. For example, the output D of the 8-to-1 multiplexer 12-1 (0)
QIN0 and / DQIN0 are input to a DQ buffer 13-1 (0), and the output DQOUT0 is a two-to-one multiplexer.
Input to 14-2 (0). 2: 1 multiplexer 14-2 (0)
Is the spare DQ when the selection signal SH1 (0) is at a high level.
The output S1DQOUT of the buffer 16-1 is selectively output, and when it is at the low level, DQOUT0 is selectively output and transmitted to the RWD bus.

The above configuration is similarly applied to the cell array block group 10-2 side (including the spare column group 11-2), and a total of 64 cells array block groups 10-1 and 10-2 are included.
A bit signal is transmitted to the RWD bus (see FIG. 12).

FIG. 14 is a circuit block diagram showing a configuration of spare column hit determination circuit 17 in FIG. Eight address hit determination circuits 171 (171-1 (0) to (3)) corresponding to a total of eight spare columns of the spare column groups 11-1 and 11-2.
, 171-2 (0) to (3)) and 64 multiplexer control signal generation circuits 172 (172-1 (0) to (31), 172-2 (172-2 (1)) corresponding to a total of 64 2: 1 multiplexers. 0) to (31)).

FIGS. 15 and 16 show the spare DQ in FIG.
DQ for generating an activation signal to a buffer and a DQ buffer
FIG. 3 is a circuit diagram showing a buffer / spare DQ buffer selection circuit 28. FIG. 15 shows an OR gate configuration. When at least one of S1SW (0) to (3) goes high (spare column hit), the signal RES1 rises and the spare DQ buffer 16-1 is activated. Also,
When at least one of S2SW (0) to (3) goes high (spare column hit), the signal RES2 rises,
Spare DQ buffer 16-2 is activated.

FIG. 16 shows a 2-to-1 multiplexer 14 (14-1).
(0)-(31), 14-2 (0)-(31)) control signals SH1 (0)
To (31), SH2 (0) to (31) are inverted, and active-high DQ buffer activation signals RE1 (0) to RE1 (31),
In this configuration, RE2 (0) to RE2 (31) are phase-generated. For example, if SH1 (0) is at a high level, SH1 (1) to SH3 (3
1) is low level, so RE1 (0) is low level,
1 (1) to RE1 (31) become high level. This allows
Only the DQ buffer 13-1 (0) in FIG. 13 becomes inactive,
Unnecessary increase in current consumption due to unnecessary DQ buffer activation can be prevented.

As described above, the spare column hit determination circuit, the DQ buffer, and the spare DQ buffer generation circuit activate the spare column and the spare DQ buffer only when a defective column address is input, and operate the 2: 1 multiplexer. Controlled DQ corresponding to output line of bad column
By replacing only the buffer output with the spare DQ buffer output, a memory circuit having a defective column can be rescued. In the above description, the cell array block group 10-1 (output numbers 0 to 31 as corresponding input / output paths)
Is replaced by the spare column of the spare column group 11-1. However, the defective column of the cell array block group 10-2 (having output numbers 32 to 63 as corresponding input / output paths) is replaced with a spare column. The same applies to the configuration where the column group 11-2 is replaced with a spare column.

The above configuration has the following problems.
The spare column group 11-1 can only replace a defective column related to only the cell array block group 10-1. Further, the spare column group 11-2 can only replace a defective column related to only the cell array block group 10-2. Therefore, when a defect concentrates on a specific cell array block group, there is a concern that the spare column prepared for the cell array block group cannot be completely replaced.

In the above example, although eight spare columns are prepared for the spare column groups 11-1 and 11-2, for example, there are more than four defective columns in the spare column group 11-1. Then it becomes impossible to remedy.

[0022]

As described above, in the conventional column redundancy technology, a spare column group that can function for each cell array block group is individually determined, and a spare column group corresponding to one cell array block group is provided. The group is, with respect to other adjacent cell array block groups,
It has a configuration that cannot be shared. As a result, there is a problem that the defect remedy efficiency due to the column redundancy is low.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory circuit having a column redundancy system with a high defect relief efficiency without causing a significant increase in chip size. Is to provide.

[0024]

A semiconductor memory circuit according to the present invention comprises a first memory cell array in which memory cells are arranged in rows and columns in a matrix,
A second memory cell array arranged in a matrix in the column direction and activated simultaneously with the first memory cell array; and first and second spares respectively adjacent to the first and second memory cell arrays A memory cell column group, a plurality of data lines provided in the column direction corresponding to the first and second memory cell arrays, and a column direction corresponding to the first and second spare memory cell column groups, respectively. At least one of the first and second spare data lines replaced with the data line;
And an address of a data line corresponding to a defective memory cell in the second memory cell array. When an external address signal is input, the data line corresponding to the external address signal is stored in the first or second spare. A control circuit for transmitting a control signal for selectively controlling a data line, a data line corresponding to the external address and not replacing the first or second spare data line based on the control signal; A selection control circuit that selects a data line corresponding to the external address and a replaced first or second spare data line and sends out data of a memory cell according to the external address signal; The data line can be replaced with any of the first and second spare data lines.

[0025]

FIG. 1 is a circuit block diagram showing a main part of an overlaid DQ bus type 4M bit DRAM according to an embodiment of the present invention. In such a configuration, similarly to FIG. 12, a 4-Mbit DRAM is configured by arranging 16 cell array blocks each having 256 rows and 1024 columns. Of the 16 cell array blocks, two cells separated by a row decoder are activated simultaneously. The selection of the cell array to be activated is performed by the upper 3 bits (AR8 to 10) of the input row address (11 bits of AR0 to AR10). The same parts as those in FIG. 12 are denoted by the same reference numerals. In the text, the leading / is provided with a bar above in the figure as described above.

FIG. 1 is different from FIG. 12 in the following configuration. DQ buffer 13-1 (13-1 (0)
~ (31)), 13-2 (13-2 (0) ~ (31)) corresponding to the 64 multiplexers each consisting of a 3 to 1 multiplexer 34 (34-0 to 63) ing. The three input terminals of such a multiplexer 34 have a regular DQ buffer (13-1 or 13-1) connecting each corresponding regular data line.
13-2), the output of the first spare DQ buffer (16-1) connecting the first spare data line, and the second spare DQ buffer (16-2) connecting the second spare data line Input each output.

The spare column hit determination circuit 37
Signals necessary for controlling the DQ buffer and the multiplexer 34 (SSW0-7, SH-0-63, SHA-0-63, SH
B-0 to 63). The configuration will also be described later.

Conventionally, the cell array block group 10-1
The defective column in can be replaced only by the spare column in the spare column group 11-1, and the defect remedy efficiency has been reduced. On the other hand, the circuit configuration with the multiplexer 34 according to the present invention has The defective column of the block group 10-1 can be replaced with any of the spare column groups 11-1 and 11-2. Also, of course, cell array blocks
The defective column 10-2 can be replaced by any of the spare column groups 11-1 and 11-2. As a result, the efficiency of repairing a defective memory is greatly improved. Further, even with such a configuration, the number of spare columns increases, so that the advantage of not significantly increasing the chip size as in FIG. 12 is inherited.

FIG. 2 is a circuit block diagram showing a main part of the present invention, which shows a portion from the cell array block of FIG. 1 to the RWD bus on the data input / output side in more detail. Spare column group 11-1). 3: 1 multiplexer 34 (34-0 ~
63) are SH-i, SHA-i, SHB-i (i = 0 to 3).
It is controlled by the three signals of 1). Although the configuration of the multiplexer 34 will be described later, these control signals SH
-i, SHA-i, and SHB-i,
One input terminal, regular DQ buffer (13-1 or 13-2)
, The output of the first spare DQ buffer (16-1), or the output of the second spare DQ buffer (16-2).

The other configuration is basically the same as that of FIG. 13 only by slightly different signal names. The spare column group 11-1 includes four spare column pairs (SBL0 to
, / SBL0 to / SBL0), which are selection signals (SBL
The switches are connected to a pair of spare DQ buses (SDQ, / SDQ) via column switches controlled by SW0 to SW3). The spare column group 11-2 has four spare column pairs (SB
L4-7, / SBL4-7), which are connected to a pair of spare DQ buses (SDQ, / SDQ) via column switches controlled by selection signals (SSW4-7).

In a normal cell array block, a DQ bus is provided at a ratio of one pair for four column pairs. That is, 256 pairs of DQ buses are arranged corresponding to 1024 column pairs in the cell array block. A pair of D
A Q bus (for example, DQ0, / DQ0) has four column pairs (BL0-3, / BL0-3) via column switches.
) Is connected.

Here, the four column pairs are selected by column switch selection signals SW0 to SW3. As shown in FIG. 2, the column switch selection signals SW0 to SW3 include the least significant two bits AC0 and AC1 (internal column address signals AC0I and AC1I) of the column address signal and a three-bit row address signal for selecting a cell array block. AR
8, AR9, AR10 (internal row address signal AR8
I, AR9I, AR10I).

The 256 pairs of DQ buses on the cell array block are multiplexed every 8 pairs by an 8: 1 multiplexer. For example, the DQ bus DQ0 in FIG.
7, / DQ0 to 7 are 8 to 1 multiplexers 12-1 (0)
Is multiplexed.

The 8 to 1 multiplexer 12 (12-1 (0) to (3
1), 12-2 (0) to (31)), a 3-bit selection signal DQM
UX0 to UX2 determine which of the eight DQ bus pairs to select. Here, DQMUX0 to DQMUX2 include upper 3 bits (AC2 to 4) of 5 bits of the column address signal.
(DQMUXs 0 to 2 correspond to internal column address signals AC2I to AC4I, respectively).

The output of the 8-to-1 multiplexer is input to the DQ buffers 13 (13-1 (0) to (31), 13-2 (0) to (31)), and each output is output to the corresponding 3-to-1 pair. 1 multiplexer 34
(34-0 to 63) are supplied to one input terminal. A 64-bit signal is transmitted to the RWD bus in the cell array block groups 10-1 and 10-2.

FIGS. 3A, 3B and 3C are circuit block diagrams showing the configuration of the spare column hit determination circuit 37. Eight address hit determination circuits 371 (371-) corresponding to a total of eight spare columns of the spare column groups 11-1 and 11-2.
0 to 7), and 128 multiplexer control signal generation circuits 372 provided for associating the SHA and SHB signals with the 64 two-to-one multiplexers 34 in total.
(372-1 (0) to (63), 372-2 (0) to (63)) and another control signal generated from the output SHA-0 to 63 of the multiplexer control signal generation circuit 372. Gate 373 (373-0 to 63).

FIGS. 4 and 5 show the configurations of the address hit judging circuit 371 of FIG. 3A and the multiplexer control signal generating circuit 372 of FIG. 3B in the spare column hit judging circuit 37 of FIG. 1, respectively. FIG. Eight address hit judging circuits in FIG. 4 are provided for the signal outputs SSW0 to SSW7. Here, the signal output SSW0 is shown as a representative. The configuration is such that the corresponding fuse FS is cut and programmed in advance so that the ground path is eliminated only when the column address signal corresponding to the defective column is input.

Further, 128 multiplexer control signal generating circuits of FIG. 5 are provided for the signal outputs SHA-0 to 63 and SHB-0 to 63. Here, the signal output SHA-0
Are representatively shown. Each bit program circuit BP
C, each output and spare column hit determination circuit
37 (here, SSW0 to SSW3, signal output S
SSW4 to SSW7 for HB-0 to 63). When a column address signal corresponding to a defective column is input, SHA-i goes low when a hit occurs in the bit program circuit that has blown the fuse.

FIGS. 6 and 7 show a spare DQ buffer in FIG. 1 and a selection circuit 38 for generating an activation signal for the DQ buffer.
FIG. 3 is a circuit diagram showing the configuration of FIG. FIG. 5 has an OR gate configuration. When at least one of the SSW0 to SSW3 becomes a high level (spare column hit), the signal RES is output.
1 rises, and spare DQ buffer 16-1 is activated. When at least one of the SSW4 to SSW7 becomes high level (spare column hit), the signal RES2 rises and the spare DQ buffer 16-2 is activated.

FIG. 8 shows the three-to-one relationship shown in FIG. 1 (or FIG. 2).
FIG. 3 is a circuit diagram showing a multiplexer 34. The pass gates PG1 to PG3 controlled by the control signals SH-i, SHA-i, and SHB-i (i = 0 to 63) respectively output the normal DQ buffer (13-1 or 13-2), One of the output of the spare DQ buffer (16-1) and the output of the second spare DQ buffer (16-2) is selected and output.

Referring to FIGS. 3 to 5, the multiplexer of FIG. 8 selects the output from the normal DQ buffer i when SH-i is at a low level and SHA-i and SHB-i are at a high level. Also, when SH-i and SHB-i are high level,
When HA-i is at low level, the output of spare DQ buffer 16-1 is selected. When SH-i and SHA-i are at the high level and SHB-i is at the low level, the spare DQ buffer
Select the output of 16-2.

Next, the operation of replacing a defective column with a spare column according to the present invention will be described. For example, the bit line BL1 of the cell array block group 10-1 in FIG.
Is a bad column. The column address of BL1 is 00001 (AC0 = 1, AC1 to AC1).
4 = 0). The spare column SB replaces this defective BL1.
L0, / SBL0 is programmed to be replaced to provide normal function.

That is, the address hit determination circuit shown in FIG.
At 371-0, AC0I, / AC1I ~ / shown in FIG.
The fuse corresponding to AC4I is cut and the defective column address is programmed. Also, the defective BL1
Corresponds to the DQ buffer of output number 0 as the corresponding input / output path, so that the multiplexer control signal generation circuit of FIG.
At 372-1 (0), the fuse FS of the bit program circuit corresponding to the spare column switch selection signal SSW0 shown in FIG. 5 is cut to program an output number corresponding to the corresponding input / output path of the defective column.

The operation of the address hit judging circuit shown in FIG. 4 will be described with reference to FIGS. First, FIG. 9 shows an operation when the input address signal (00000 in this example) does not match the programmed defective address signal (00001). After the inversion signal CASint of / CAS rises, the node NA in FIG. 4 is lowered from the initial high level to the low level by the NMOS transistor (NMOS) having / AC0I input to the gate, and the SSW0 also outputs the low level. I do. SSW0 is the column switch signal of the spare column (active high)
In this case, no spare column is selected.

As a result, the signal SAH from the multiplexer control signal generation circuits (shown in FIG. 3) 372-1 (0), 372-2 (0) via the corresponding bit program circuit BPC (shown in FIG. 5) is obtained. -0, SBH-0 goes high, and the multiplexer selects the normal DQOUT0.

Next, consider the case where the same address signal as the programmed defective address signal (00001) is input (FIG. 10). At this time, after CASint rises, AC0I and / AC1I to / AC4I go to high level. However, due to the blown fuse, the node NA in FIG. 4 is not pulled down to low level, and SSW0 outputs high level. I do. Thereby, the spare column S in FIG.
The column switches BL0 and / SBL0 are selected.

Next, the multiplexer control signal generating circuit of FIG. 3 will be described with reference to FIGS. FIG.
1 is an operation waveform diagram of the multiplexer control signal generation circuit 372-1 (0) in which the fuse has been cut. After CASint rises from low to high level, the fuse is blown, so that node NB in the bit program circuit of FIG.
Keeps a high level, and since SSW0 is a high level output, the node NC changes from low to high level. Therefore, SHA-0 falls.

Here, in FIG. 3, since the fuses of the multiplexer control signal generation circuits 372-1 (1) to (31) and 372-2 (0) to (31) are not blown, they are not shown in FIG. Node NB is pulled low. Therefore, SHA-1
To 63 and SHB-0 to 63 are at low level. Therefore, FIG.
In the 2: 1 multiplexer 34, the spare column output SDQOUT from the spare DQ buffer 16-1 is transmitted to the RWD bus in place of DQOUT0 connected to the defective column.

As shown in FIG. 6, when SSW0 is at a high level, RES1 is at a high level, and the spare DQ buffer 16-1 is in an active state. In addition, from FIG.
Only A-0 is at a low level, only SH-0 is at a high level. As a result, from FIG. 7, only the signal RE0 is at a low level.
13-0 becomes inactive. Thus, it is possible to prevent an increase in current consumption due to unnecessary activation of the DQ buffer. If there are no other bad columns, 2: 1
Each of the multiplexers 34-1 to 63 selects an output connected to a normal normal column and transmits the output to the RWD bus.

Next, a case will be described where BL0 shown in FIG. 2 is a defective column and is replaced with SBL4 of the spare column group 11-2. At this time, the column address corresponding to the defective BL0 is programmed in the address hit determination circuit 371-4 of FIG. 3 by the method described above. further,
The fuse of the bit program circuit corresponding to SSW4 of the multiplexer control signal generation circuit 372-2 (0) may be cut off.

With this setting, when a bad column address is input from the outside, the signal SSW4 goes high when the address hit determination circuit 371 of FIG. 3 operates. As shown in FIG. 5, when SSW4 is at a high level, RES2
Goes high, and spare DQ buffer 16-2 is active. Thereby, the column S of the spare column group 11-2
BL4 and / SBL4 are selected.

Also, at the high level of SSW4, the output SHB-0 of the multiplexer control signal generation circuit 372-2 (0) that has blown the fuse of the bit program circuit becomes low level. From FIG. 3C, only SHB-0 is at the low level and only SH-0 is at the high level. As a result, as shown in FIG. 7, only the signal RE0 becomes low level, and the DQ buffer 13-1 (0) connected to the defective column in FIG. 2 becomes inactive (an increase in current consumption due to unnecessary DQ buffer activation). Contribute to prevention).

As a result, the DQO connected to the defective column
Spare column output SDQOUT from spare DQ buffer 16-2 is transmitted to RWD bus in place of UT0. Assuming that there are no other defective columns, the two-to-one multiplexers 34-1 to 63-3 select the output connected to the normal normal column and transmit it to the RWD bus.

According to the above configuration, even if the address signal input from the outside corresponds to any of the defective memory cell columns in the cell array block groups 10-1 and 10-2, the spare memory cell column groups 11-1 and 11-2. -2 Since the circuit is configured so that it can be replaced with either, the defect relief efficiency is improved. Further, although the defect relief efficiency is improved, the number of circuits such as spare columns directly related to the column redundancy does not necessarily need to be increased, so that the chip size does not increase significantly.

[0055]

As described above, according to the present invention,
Spare column groups that can function for each cell array block group are not determined individually, and a highly flexible column redundancy technology that can be shared with other cell array block groups is provided. It is possible to provide a semiconductor memory device having a high efficiency of repairing a defective memory without causing a large increase in the number of memory cells.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a main part of an overlaid DQ bus type 4M bit DRAM according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a main part of the present invention, showing in more detail a portion from the cell array block of FIG. 1 to an RWD bus on the data input / output side.

3A, 3B, and 3C are circuit block diagrams illustrating a configuration of a spare column hit determination circuit in FIG. 1;

FIG. 4 is a circuit diagram showing an address hit determination circuit of FIG.

FIG. 5 is a circuit diagram showing a configuration of a multiplexer control signal generation circuit of FIG. 3 (b).

FIG. 6 is a circuit diagram showing a configuration of an activation signal control circuit for a spare DQ buffer in FIG. 1;

FIG. 7 is a circuit diagram showing a configuration of an activation signal control circuit for a DQ buffer in FIG. 1;

FIG. 8 is a circuit diagram showing the 3: 1 multiplexer shown in FIG. 1 (or FIG. 2).

FIG. 9 is a first waveform diagram for explaining the operation of the address hit determination circuit of FIG. 4;

FIG. 10 is a second waveform diagram for explaining the operation of the address hit determination circuit of FIG. 4;

FIG. 11 is an operation waveform diagram of a multiplexer control signal generation circuit in which a fuse is cut.

FIG. 12 shows a 4-Mbit D of an overlaid DQ bus type.
FIG. 2 is a circuit block diagram illustrating a main part of a RAM.

FIG. 13 is a circuit block diagram showing a portion from the cell array block of FIG. 11 to the RWD bus on the data input / output side in further detail.

FIG. 14 is a circuit block diagram showing a configuration of a spare column hit determination circuit in FIG. 11;

FIG. 15 is a circuit diagram showing a configuration of an activation signal control circuit for a spare DQ buffer in FIG. 11;

16 is a circuit diagram showing a configuration of an activation signal control circuit for a DQ buffer in FIG. 11;

[Explanation of symbols]

 10-1, 10-2: cell array block group 11-1, 11-2: spare column group 12-1, 12-2: multiplexer (8: 1 multiplexer) 13-1, 13-2: DQ buffer 15: data I / O buffers 16-1, 16-2 ... spare DQ buffers 21 ... row control circuits 22 ... row address buffers 23 ... row predecoders 24 ... row decoders 25 ... column address buffers 26 ... column control circuits 27 ... column predecoders 34-0 to 63: Multiplexer (3: 1 multiplexer) 37: Spare column hit determination circuit 38: DQ buffer / spare DQ buffer selection circuit

Claims (6)

[Claims] 1. A first memory cell array in which memory cells are arranged in rows and columns in a matrix, and memory cells are arranged in a matrix in rows and columns. A second memory cell array activated simultaneously; a first and a second spare memory cell column group respectively adjacent to the first and second memory cell arrays; and a first memory cell array corresponding to the first and second memory cell arrays. A plurality of data lines provided in the column direction, and at least one of the first and second data lines provided in the column direction and replaced with the data lines corresponding to the first and second spare memory cell column groups, respectively. 2 spare data lines and an address of a data line corresponding to a defective memory cell in the first and second memory cell arrays, and an external address signal is inputted. A control circuit for transmitting a control signal for selectively controlling the data line corresponding to the external address signal and the first or second spare data line; and a control circuit corresponding to the external address based on the control signal. And selecting a data line that has not been replaced with the first or second spare data line and a first or second spare data line that has been replaced with a data line corresponding to the external address. A selection control circuit for transmitting data of a memory cell in accordance with an address signal, wherein the data line is replaceable with any of the first and second spare data lines. 2. The semiconductor memory device according to claim 1, wherein said selection control circuit includes a signal for selecting at least said first spare data line and a signal for selectively controlling said second spare data line. And a signal for selectively controlling the data line, the data line and the first and second
And a multiplexer circuit for selecting one of the spare data lines. 3. The semiconductor memory device according to claim 1, wherein said selection control circuit selects a data line corresponding to said external address from a plurality of data lines provided in said first and second memory cell arrays. Circuit, a first spare buffer circuit for selecting the first spare data line, a second spare buffer circuit for selecting the second spare data line, and selection control of at least the first spare data line , A signal for selectively controlling the second spare data line, and a signal for selectively controlling the data line, the buffer circuit and the first and second spare buffer circuits are selected. A data line and a multiplexer circuit for selecting one of the first and second spare data lines. 4. The semiconductor memory device according to claim 1, wherein the first and second memory cell arrays each form a plurality of memory cell array block groups. 5. The semiconductor memory device according to claim 1, wherein said memory cells constitute DRAM memory cells. 6. A first memory cell array in which memory cells are arranged in a matrix in the row and column directions, and a first memory cell array in which memory cells are arranged in a matrix in the row and column directions. Activated second
A first and a second spare memory cell column group provided apart from each other; a plurality of data lines provided in the column direction corresponding to the first and second memory cell arrays; At least one first and second spare data lines provided in the column direction and corresponding to the data lines, respectively, corresponding to the first and second spare memory cell column groups; 2 stores the address of the data line corresponding to the defective memory cell in the memory cell array, and when an external address signal is inputted, the data line corresponding to the external address signal and the first or second spare data line are stored. And a control circuit for transmitting a control signal for selectively controlling the first or second spare data corresponding to the external address based on the control signal. And a data line corresponding to the external address and a data line corresponding to the external address and a replaced first or second spare data line, and transmitting data of a memory cell corresponding to the external address signal. A semiconductor memory device, wherein the data line is replaceable with any of the first and second spare data lines.