JP4693197B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides a redundancy system for relieving defective memory cells. Include The present invention relates to a semiconductor memory device.
[0002]
[Prior art]
A redundancy system is employed in the semiconductor memory device. In the redundancy system, if some of the memory cells are defective, the defective cells are repaired by replacing them with redundant cells, thereby improving the product yield. Currently, the most commonly used redundancy system is a cell array unit replacement, in which a plurality of rows or a plurality of columns (in some cases, one column or one row) of a memory cell array are replaced as a unit. That is, as a result of testing the memory cell array, if there is a defective cell, the cell array including the cell is replaced with a redundant cell array (spare element) having the same size.
Address information in cell array units including defective cells is stored in a nonvolatile storage element. Currently, a fuse is generally used as the memory element. Since address information is usually composed of a plurality of bits, a fuse set including a plurality of fuses corresponding thereto is a unit of redundancy. Normally, spare elements and fuse sets are in one-to-one correspondence, and the same number of fuse sets as spare elements are provided in the chip. When a spare element is used, the fuse in the corresponding fuse set is cut according to the address. This method has a simple structure and is currently widely used.
[0003]
On the other hand, since the redundancy system requires a spare element and a fuse set in addition to a normal circuit, the area of the memory chip increases. Since the number of repairable defects and the area of the redundant circuit are in a trade-off relationship, various redundancy systems that improve the area efficiency have been proposed. For example, there is a flexible redundancy system proposed by Kirihata et al. In this method, since one spare element covers a wide cell array region, even when defective cells are biased to a part of the chip, they are relieved as in the case where defects are evenly distributed in the cell array. it can. For this reason, the area efficiency of the redundancy circuit can be increased by reducing the number of spare elements.
Thus, when the number of defects per chip is known or can be predicted, it is effective to improve the area efficiency by relieving defects with a small number of spare elements. In particular, the above method is effective when one spare element can cover a wide cell array region.
[0004]
However, recently, a memory chip in which a memory cell array is divided into a plurality of parts has been developed. For example, there is a memory chip that has a plurality of banks inside the chip and these banks are activated simultaneously. Such a memory chip cannot have a spare element for repairing a defective cell in another bank. As the number of banks increases, the number of divided memory cell arrays in the chip increases, and the cell array area that can be covered by one spare element becomes narrower. This is mainly a problem with the row spare element, but the same problem occurs with the column spare element. That is, as the speed of the memory device increases, if the position of the memory cell before and after replacement with the spare element is physically separated, the propagation delay of the signal or data increases and the high-speed performance is impaired. If high speed performance is to be maintained, only physically close positions can be replaced. As a result, the column spare element cannot cover a wide cell array region.
[0005]
[Problems to be solved by the invention]
As described above, due to restrictions on the number of banks, high-speed operation, etc., when the spare element can cover only a narrow range, it is narrow in order to be able to repair the defective cell even when the defect is unevenly distributed in a part of the memory cell array. Spare elements must be provided for each cell array region. When this is viewed as a whole chip, the number of spare elements, which greatly exceeds the average number of defects per chip, is incorporated into the chip, which deteriorates the area efficiency. Further, in the conventional method in which the spare elements and the fuse sets are in one-to-one correspondence, the number of fuse sets increases as the number of spare elements increases. In general, a fuse requires a larger area than a spare element. Therefore, in a system in which a spare element and a fuse set are in a one-to-one correspondence, the area efficiency of the redundancy circuit is greatly reduced.
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and an object of the present invention is to eliminate the number of nonvolatile memory elements necessary for defect relief and to improve the area efficiency of the redundancy circuit for the chip, and to provide high relief. It is an object to provide a semiconductor memory device capable of obtaining a rate
[Means for Solving the Problems]
A first semiconductor memory device according to the present invention includes a memory cell array in which memory cells divided into a plurality of sub-cell arrays are arranged in rows and columns, a redundant cell array disposed corresponding to each sub-cell array, and an input A row decoder for selecting a row of the memory cell array according to the inputted address; a column decoder for selecting a column of the memory cell array according to the inputted address; an address of a defective memory cell included in the memory cell array; Mapping information indicating a correspondence relationship with the redundant cell array is stored, and if the address of the defective memory cell matches the input address, a replacement control signal for the defective memory cell is determined based on the match result and the mapping information And a replacement control signal supplied from the memory circuit Is activated in response, characterized by comprising a spare decoder for selecting said redundant cell array.
[0006]
A second semiconductor memory device according to the present invention includes a memory cell array in which memory cells divided into a plurality of sub-cell arrays are arranged in rows and columns, a redundant cell array disposed corresponding to each sub-cell array, A row decoder that selects a row of the memory cell array according to an input address, a column decoder that selects a column of the memory cell array according to an input address, and an address of a defective memory cell included in the memory cell array A plurality of first storage elements for storing, and the redundant cell array And each A plurality of second storage elements that store mapping information indicating the correspondence relationship of fuse sets, and the addresses of the defective memory cells stored in the plurality of first storage elements are compared with the input addresses, A plurality of comparators that output a coincidence output signal when the stored address of the defective memory cell coincides with an inputted address, and when the coincidence output signal is output from each of the comparators, A plurality of storage circuits including a decoder that decodes mapping information stored in the two storage elements; and a spare decoder that is activated according to an output signal of the decoder and selects the redundant cell array. And
[0007]
In the present invention Affect A third semiconductor memory device includes a first memory cell array in which a plurality of memory cells are arranged in rows and columns, a second memory cell array in which a plurality of memory cells are arranged in rows and columns, and the first memory cell array A plurality of first redundant units for replacing first defective memory cells in the memory cell array; a plurality of second redundant units for replacing second defective memory cells in the second memory cell array; and a defective memory Mapping information indicating the correspondence between the cell address and the first and second redundant units is stored, and if the address of the defective memory cell matches the input address, a failure is determined based on the mapping information. A plurality of memory circuits for outputting a memory cell replacement control signal; The number of the memory circuits is less than or equal to the number of the first and second redundant units, The first memory cell array includes a first bank, the second memory cell array includes a second bank, and each of the plurality of storage circuits includes a defective memory cell and the first memory cell in the first memory cell array. One of the defective memory cells of the memory cell array of 2 is replaced.
In the present invention Affect A fourth semiconductor memory device includes a memory cell array in which memory cells divided into a plurality of banks are arranged in rows and columns, a redundant cell array for replacing defective memory cells in the memory cell array, and the memory cell array Mapping information indicating a correspondence relationship between the address of the defective memory cell and the redundant cell array, address information for selecting the bank, and when the address of the defective memory cell matches the input address, A plurality of memory circuits for outputting replacement control signals for defective memory cells based on the mapping information and address information; And the number of the memory circuits is less than or equal to the number of the redundant cell arrays. It is characterized by that.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a structure of a main part of a DRAM according to an embodiment of the present invention. The memory cell array 1 is divided into M-row × N-column matrix sub-cell arrays 11 (m, n). Specifically, the memory cell array 1 has a total of 8 × 16 = 128 sub-cell arrays 11 (m, n), where M = 8 in the horizontal direction (row direction) and N = 16 in the vertical direction (column direction). (M = 0 to 7, n = 0 to 15). The division unit of the sub-cell array 11 is determined by, for example, the number of columns that can simultaneously transfer data to the data lines and the number of rows (number of word lines) included in the range of consecutive bit lines connected to one sense amplifier column. The In this embodiment, this division unit is also a repair unit for repairing a defect by one spare element (redundant cell array). However, it is possible to remedy defects in a plurality of subarrays with one spare element.
The eight sub cell arrays 11 arranged in the row direction constitute one bank, and in this embodiment, 16 banks Bn (n = 0 to 15) are arranged. Further, the 16 subarrays arranged in the column direction constitute a subarray column. In the case of FIG. 1, eight subcell array columns Cm (m = 0 to 7) are arranged. A row decoder circuit 3 for decoding a row address RA supplied from the outside is arranged at the end of the memory cell array 1 in the row direction. sub A column decoder circuit 2m for decoding a column address CA supplied from the outside is arranged in each cell array column Cm. A memory cell is selected by the row decoder circuit 3 and the column decoder circuit 2m.
[0009]
As shown in FIG. 2, each sub-cell array 11 includes a plurality of word lines WL and dummy word lines DWL, and a plurality of column selection lines CSL orthogonal thereto. Although the capacity of the sub-cell array 11 is arbitrary, in this embodiment, it is assumed that there are 16 column selection lines CSL for each sub-cell array 11. Although omitted in FIG. 1, as shown in FIG. 2, on both sides of the sub-cell array 11, sense amplifier rows 6 for reading data of bit lines selected by the column selection line CSL are arranged. These sense amplifier arrays 6 are of a so-called shared sense amplifier system shared by adjacent sub cell arrays. However, the configuration is not limited to the shared sense amplifier system, and a configuration in which a sense amplifier array is provided independently for each sub-cell array may be employed.
A spare element 12 (m, n) is arranged as a redundant cell array at the end in the row direction of each sub-cell array 11, and a spare column selection line SCSLm (m = 0) for selecting the spare element 12 is provided in this spare element 12. ˜7) are arranged in parallel with the column selection line CSL.
FIG. 3 specifically shows FIG. In FIG. 3, the spare element 12 has a pair of redundant bit lines BL, bBL (hereinafter, b represents an inverted signal). However, the present invention is not limited to this, and a spare element having a plurality of redundant bit line pairs may be used. In the redundant bit line pair BL, bBL constituting the spare element 12, the same memory cell MC and dummy cell DMC as the sub cell array 11 are arranged. These memory cells MC and dummy cells DMC are selected by a word line WL and a dummy word line DWL extended from the sub-cell array 11.
[0010]
As shown in FIG. 1, the column selection line CSL and the spare column selection line SCSL are continuously arranged in N = 16 sub cell arrays 11 and spare elements 12 arranged in the column direction. A column decoder circuit (CD) 2 for selectively driving the column selection line CSL is provided in common for N = 16 sub-cell arrays 12 arranged in the column direction. Spare column decoder (SCD) 9 m is arranged adjacent to each column decoder circuit 2. The spare column decoder (SCD) 9m drives a spare column selection line SCSL connected in common to N = 16 spare elements 12 arranged in the column direction at the time of defect repair.
As shown in FIG. sub The bit line pairs BL and bBL of the cell array 11 and spare element 12 are respectively connected to sense amplifiers (SA) constituting the sense amplifier array 6. A column selection switch circuit (SW) 7 is connected between the sense amplifier (SA) and the data line pair DQ, bDQ. These column selection switch circuits (SW) 7 are connected to a column selection line CSL and a spare column selection line SCSL, and these column selection switch circuits (SW) 7 are selectively selected by signals from the column selection line CSL and the spare column selection line SCSL. ON / OFF controlled. At the time of data reading, data propagating through the bit line pair BL, bBL is amplified by the sense amplifier (SA) and output to the data line pair DQ, bDQ via the switch circuit 7 turned on.
[0011]
As shown in FIG. 1, in this embodiment, N = 16 fuse sets 5n (n = 0 to 15) equal to the number of sub-cell arrays 11 in the row direction (that is, the number of banks) are provided. Each fuse set 50 to 515 stores an address (defective address) of a defective memory cell, and compares an externally supplied address with the defective address. As a result of this comparison, if they match, the spare element 12 outputs a signal for replacing the defective column. This signal is supplied to the spare column decoder of the corresponding sub cell array, and an inverted signal of this signal is supplied to the column decoder of the corresponding sub cell array. In this embodiment, each fuse set 50 to 515 stores correspondence information (mapping information) with eight spare column selection lines SCSL0 to SCSL15. Details thereof will be described later.
In this embodiment, M × N spare elements 12 are arranged corresponding to M × N sub-cell arrays 11, and fuse sets 5 corresponding to the number of sub-cell arrays 11 in the column direction are provided. However, the present invention is not limited to this configuration. That is, in the present invention, the fuse set is different from the conventional one, and has mapping information indicating the correspondence relationship with the spare element. The conventional fuse set is in one-to-one correspondence with the spare element. On the other hand, the fuse set of this embodiment is associated with an arbitrary spare element by mapping information. As a result, the number of fuse sets can be made equal to or less than the number of spare elements, and the defects can be flexibly remedied even when the defects are uniformly distributed or when the defects are unevenly distributed. In general, the relationship between the number of fuse sets Nfs and spare elements in the present invention is expressed by the following equation.
[0012]
Nfs <M × N
Each fuse set 50-515 has eight output lines 80-87. Any one of these output lines 80 to 87 is activated when a defective column selection line is replaced. Eight replacement control signal lines 40 to 47 are connected to the output lines 80 to 87 of the fuse sets 50 to 515 to form a wired OR circuit. One of these eight replacement control signal lines 40 to 47 is set to a high level in accordance with a high level signal output from any one of the fuse sets 50 to 515 when a defective cell is replaced. . When one of the replacement control signal lines 40 to 47 becomes high level, one spare column selection line SCSL is selected by the spare column decoder (SCD) to which this high level signal is supplied. At the same time, the column decoder (CD) to which the high level signal is supplied via the inverter circuit 22 deselects the column selection line CSL in the sub cell array 11. Accordingly, the eight replacement control signal lines 40 to 47 control the eight column decoder circuits 20 to 27 and the spare column decoders 90 to 97 adjacent thereto, respectively.
The operation of the replacement control signal line 4 will be described more specifically. The first replacement control signal line 40 selectively activates the column decoder circuit 20 and the spare column decoder 90 adjacent thereto. Accordingly, the input terminal of each column decoder (CD) constituting the column decoder circuit 20 is connected to the replacement control signal line 40 via the inverter 22, and the input terminal of the spare column decoder (SCD) 90 is connected to the replacement control signal line 40. Connected directly. As a result, when the replacement control signal line 40 is at a high level, the spare column decoder 90 is activated and the column decoder circuit 20 is deactivated. As a result, the spare column selection line SCSL0 is selected in place of the column selection line CSL selected by the column decoder circuit 20 and the data of the spare element 12 is read out.
[0013]
Similarly, the second and subsequent replacement control signal lines 41, 42,... Control the activation of the column decoder circuits 21, 22,... And the spare column decoders 91, 92,. According to this configuration, when the spare column selection line SCSL is selected in an arbitrary sub-cell array, the column selection line CSL is deactivated and a defective cell is replaced with a spare cell.
FIG. 4 shows a specific configuration of the fuse sets 50 to 515 shown in FIG. Since these fuse sets 50 to 515 have the same configuration, only one will be described. The fuse set 5 includes an addressing fuse circuit 501 that stores a defective address of the memory cell array 1 and an enable fuse circuit 502 that stores whether or not the fuse set 5 is used. Further, the fuse set 5 includes a mapping fuse circuit 503. The mapping fuse circuit 503 stores in advance one address of the eight spare column selection lines SCSL to which the fuse set 5 corresponds.
The addressing fuse circuit 501 has a total of 11 fuses FS. Among these, for example, seven fuses FS (1) to (7) are used for designating the minimum unit of the column address. The remaining four fuses FS (8) to (11) are used to select the 16 spare elements 12 read by one spare column selection line SCSL. That is, the addressing fuse circuit 501 includes address information for designating a defective memory cell in the sub-cell array 11 and address information for selecting 16 banks Bn (n = 0 to 15). . The mapping fuse circuit 503 has three fuses FS (13) to (15) necessary for selecting eight spare column selection lines SCSLm. That is, the mapping fuse circuit 503 stores address information for selecting one of the eight sub-cell array columns Cm (m = 0 to 7) arranged in the row direction.
[0014]
The fuses FS of the fuse circuits 501 to 503 are all connected in series between the power supply Vcc and the ground Vss together with the precharging PMOS transistor Qp and the selection NMOS transistor Qn. A connection node N between the PMOS transistor Qp and the NMOS transistor Qn is an output node. The fuse data is read by turning on the PMOS transistor Qp and precharging the output node N to the power supply voltage Vcc, and then turning off the PMOS transistor Qp and turning on the NMOS transistor Qn. That is, fuse FS Cut off When disconnected, the high level (= Vcc) is output from the output node N, and when the fuse FS is not disconnected, the low level (= Vss) is output from the output node N.
The output signal of the fuse circuit 501 is supplied to an address match detection circuit 504 configured by a plurality of comparators CMP together with column addresses a0 to a6 and addresses b0 to b3. The addresses b0 to b3 are addresses necessary for selecting the 16 spare elements 12 selected by one spare column selection line SCSL. The address match detection circuit 504 detects whether or not the output signal of the fuse circuit 501 matches the column addresses a0 to a6 and the addresses b0 to b3. The plurality of output signals from the address match detection circuit 504 and the output signal from the enable fuse circuit 502 are supplied to an AND gate 505. From the output terminal of the AND gate 505, a Match signal 507 (that is, an enable signal for replacing a defective cell) indicating that the address supplied from the outside matches the fuse information is output.
[0015]
The Match signal 507 is supplied to the decoder 506. Three output signal lines 5081, 5082, and 5083 of the mapping fuse circuit 503 are connected to the decoder 506. The decoder 506 decodes the output signal of the mapping fuse circuit 503 when the Match signal 507 is activated. As a result, any one of the eight output lines 8 of the decoder 506 is activated, and this becomes a replacement control signal for activating one of the replacement control signal lines 4.
In this example, the addressing fuse circuit 501 has eleven fuses, the enabling fuse circuit 502 has one fuse, and the mapping fuse circuit 503 has three fuses. However, this is only an example. The number of fuses in the addressing fuse circuit 501 increases / decreases according to the capacity of the sub-cell array 11 and the capacity of the bank, and the number of fuses in the mapping fuse circuit 503 also increases / decreases according to the number of sub-cell array columns. A plurality of fuses of the enabling fuse circuit 502 may be provided.
FIG. 5 shows an example of the decoder 506. The decoder 506 includes three AND signals G1 to G8 supplied with three signals output from the fuse circuit 503, their inverted signals, and a Match signal 507. A replacement control signal is output from the output terminals of the AND gates G1 to G8.
[0016]
According to the above embodiment, spare elements 12 are arranged in 128 sub-cell arrays 11, and the number of fuse sets is 16 which is smaller than the number of spare elements 12, so that defects of 16 sub-cell arrays 11 can be relieved. . In addition, each fuse set 5 has mapping information indicating which of the 16 sub-cell array columns Cm corresponds to the 16 fuse sets 5 together with the defective address, and 8 replacements are performed based on this mapping information. Any one of the control signal lines 4 is selected so that the fuse set 5 can correspond to an arbitrary sub-cell array column Cm. Therefore, even when defective portions are dispersed inside the memory cell array or when the defective portions are unevenly distributed in a part of the memory cell array, the 16 fuse sets 5 can be flexibly dealt with.
Specifically, for example, in the memory cell array 1 shown in FIG. 1, consider a case where there are 16 defective cells along one column selection line CSL in the sub-cell array column C0. In this case, mapping information for activating the replacement control signal line 40 is stored in all 16 fuse sets 50 to 515, and 16 fuse sets 50 to 515 store 16 pieces of information along one column selection line. Defective cells are relieved.
[0017]
Specifically, the effect of the redundancy method of this embodiment is illustrated using the conventional method. 14 This will be described in comparison with FIG. 14 and 15, the same parts as those in FIG. First, in the conventional system shown in FIG. 14, the spare element 12 (m, n) is arranged for every 128 sub-cell arrays 11 (m, n) of the memory cell array 1. This configuration is the same as in the present embodiment. However, a fuse set group 601 (6010 to 6017) is provided for each spare column selection line SCSL. Each fuse set group 601 has 16 fuse sets 602 (602 0 to 602 15) to correspond to the 16 spare elements 12 divided along the spare column selection line SCSL. For example, each spare element 12 and each fuse set 5 are in one-to-one correspondence such that the fuse set 6020 corresponds to the spare element 12 (1, 0) and the fuse set 60215 corresponds to the spare element 12 (1, 15). Is supported. In this example, assuming that the number of addresses is the same as in the above embodiment, the number of fuses is {7 (number of addresses) +1 (enable)} × 16 × 8 = 1024. This is 4.3 times the number of fuses in the above embodiment.
[0018]
Further, in the case of the conventional system shown in FIG. 14, 128 spare elements 12 can be replaced with defective cells, so that the degree of freedom of relief is large as in the above embodiment. However, when the number of defects generated in one chip is about 10 on average, the number of fuse sets actually used for defect repair is about 10. Therefore, there are many fuse sets that are not used for defect relief. For this reason, the redundancy efficiency of a defective cell is low although the redundant circuit occupies a large area of the chip.
Next, in the conventional method shown in FIG. 15, the spare elements 12 are arranged in common for the plurality of sub-cell arrays 11 arranged in the column direction. The fuse sets 7010 to 7017 are arranged in the sub-cell array columns C0 to C7. In this example, the number of fuses is as small as {7 (number of addresses) +1 (enable)} × 8 = 64. However, assuming that the average number of defects generated in one chip is 10 as described above, since there are only 8 spare elements 12, the repair rate is low and the yield of the chip is greatly reduced.
On the other hand, in the case of the above embodiment, the memory cell array 1 has 128 spare elements 12. However, the number of fuses is {7 (number of addresses) +4 (spare element selection) +1 (enable) +3 (mapping)} × 16 = 240. That is, the number of fuses can be greatly reduced as compared with the method shown in FIG. In addition, defective cells can be rewritten by arbitrarily selecting one of the 128 spare elements. Therefore, the relief efficiency is good.
[0019]
FIG. 6 shows a modification of the fuse set. In the above embodiment, when there are a plurality of defective cells along a certain column selection line, the address information corresponding to each defective cell is programmed in the mapping fuse circuit 503 to correspond to the plurality of fuse sets. . On the other hand, if all the memory cells along one column selection line are defective, in order to be able to relieve them with one fuse set, the structure of the fuse set shown in FIG. What is necessary is just to deform | transform like 6. That is, a fuse circuit 511, an AND gate 513, and an OR gate 514 are added to the fuse set of FIG. The fuse circuit 511 is an enable fuse circuit having one fuse and indicating whether or not this fuse set is used. Of the output signals from the coincidence detection circuit 504, an output signal corresponding to the bank address designating circuit unit 501b is supplied to the AND gate 513. The output signal of the AND gate 513 and the output signal of the fuse circuit 511 are supplied to an OR gate 514, and the OR gate 514 is supplied to the AND gate 505.
In the above configuration, when all the memory cells are defective along a certain column selection line, the fuse of the fuse circuit 511 of the corresponding fuse set is cut. At this time, it is not necessary to program the bank address designating circuit unit 501b of the address designating fuse circuit 501.
[0020]
In this way, when a defective column address is input, the Match signal 507 is set to the high level by the output signal of the fuse circuit 511 regardless of the bank address. In other words, when all the cells along one column selection line are defective, it is possible to perform defect repair with one fuse set for these defective cells. Therefore, defective cells can be flexibly remedied according to the number and location of defective cells.
In the above embodiment, the spare element 12 is arranged for each sub-cell array 11, but the present invention is not limited to this. The arrangement and number of spare elements can be variously modified as shown in FIGS.
FIG. 7 shows an example in which one spare element 12 is arranged for a plurality of sub-cell arrays 11 arranged in the row direction. At this time, one spare element 12 is used for defect repair of a plurality of sub-cell arrays 11 arranged in the row direction. The number of spare elements 12 is 1 / integer of the number M × N of the sub-cell arrays 11.
The configuration shown in FIG. 7 is effective when the density of defective cells is small because the number of spare elements is small. According to this configuration, the area can be reduced without reducing the relief efficiency.
[0021]
FIG. 8 shows an example in which one spare element 12 is arranged in common for a plurality of sub-cell arrays 11 arranged in the column direction. According to this configuration, defective cells generated in the plurality of sub-cell arrays 11 along the column selection line CSL can be collectively replaced with the spare element 12. In addition, with this configuration, the number of fuses, the number of comparison circuits, and the number of AND gates in one fuse set can be reduced, and the chip area can be reduced and high-speed operation is possible.
FIG. 9 shows an example in which spare elements 12 are arranged between the sub-cell array 11 and the row decoder 3. According to this configuration, when an input / output circuit is arranged near the row decoder, when a spare element is selected, data can be transferred between the selected spare element and the input / output circuit at high speed.
FIG. 10 shows an example in which the row decoder 3 is arranged between the sub cell array 11 and the spare element 12. Also with this configuration, the same effect as in FIG. 9 can be obtained.
FIG. 11 shows an example in which the spare element 12 is arranged in the middle part of the sub-cell arrays 11 arranged in the row direction. Also with this configuration, the same effect as in FIG. 9 can be obtained.
[0022]
9 to 11, the spare elements 12 can be arranged in common in the column direction as in the example shown in FIG.
FIG. 12 shows an example in which the number of spare elements is varied depending on the location of the memory cell array. Specifically, it is shown that there are a portion where two spare elements 12 are provided and a portion where one spare element 12 is provided for one sub-cell array 11. In general, a defect is likely to occur in a portion where the continuity of the pattern is interrupted, such as a chip end portion or a memory cell array end portion, depending on manufacturing process conditions. Therefore, as shown in FIG. 12, by arranging a plurality of spare elements in a sub-cell array located in a portion where the continuity of the pattern is interrupted, such as an end of a chip or an end of a memory cell array, a plurality of spare elements are arranged. Defects can be remedied.
FIG. 13 shows an example in which the number of spare elements is varied according to the capacity of the sub-cell array. For example, there are memory devices in which the memory cell array is not divided into sub-cell arrays having equal capacity, such as memory cells having parity bits and Rambus compliant DRAMs. A memory cell array having such a sub-cell array has a different defect occurrence density depending on the capacity of the sub-cell array. In the memory cell array 11 shown in FIG. 13, the sub-cell array 11a has a capacity of 160K bits, for example, and the sub-cell array 11b has a capacity of 128K, for example. In this case, the defect occurrence density of the sub cell array 11a is higher than that of the sub cell array 11b. Therefore, two spare elements 12 are arranged corresponding to each sub-cell array 11a, and one spare element 12 is arranged corresponding to each sub-cell array 11b.
[0023]
According to the above configuration, since a large number of spare elements are arranged only for the sub-cell array having a high defect occurrence density, the number of spare elements can be minimized and the repair efficiency of defective cells can be improved.
In addition, the present invention can be variously modified. For example, the above embodiment has described the case where a defective column selection line, that is, a defective bit line is replaced by a spare element. However, the present invention is not limited to this, and the present invention can be similarly applied to a case where a defective word line is replaced with a spare element.
Further, in the above embodiment, the fuse is used as the nonvolatile memory element constituting the defective address memory circuit, but various other nonvolatile semiconductor memory elements such as ROM, EPROM, and EEPROM can be used.
Furthermore, the semiconductor memory device to which the present invention is applied is not limited to a single unit, but includes a case of a memory device margined by a logic circuit or the like.
[0024]
【The invention's effect】
According to the present invention, by storing the mapping information with the redundant cell array in the memory circuit that stores the defective address, the defective cell can be reliably remedied even when the defective cell is unevenly distributed in a part of the memory cell array. In addition, it is possible to improve the area efficiency of the redundancy circuit by eliminating the number of redundant cell arrays necessary for repairing defective cells.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main part of a DRAM according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a specific configuration of the subarray shown in FIG.
3 is a circuit diagram specifically showing the sub-cell array shown in FIG. 1 and its peripheral circuits. FIG.
4 is a circuit diagram showing the fuse set shown in FIG. 1. FIG.
FIG. 5 is a circuit diagram showing a configuration of a decoder shown in FIG. 4;
FIG. 6 is a block diagram showing a modification of the fuse set.
FIG. 7 is a block diagram showing a modified example of the arrangement of sub-cell arrays and spare elements.
FIG. 8 is a block diagram showing a modified example of the arrangement of sub-cell arrays and spare elements.
FIG. 9 is a block diagram showing a modified example of the arrangement of sub-cell arrays and spare elements.
FIG. 10 is a block diagram showing a modified example of the arrangement of sub-cell arrays and spare elements.
FIG. 11 is a block diagram showing a modified example of the arrangement of sub-cell arrays and spare elements.
FIG. 12 is a block diagram showing a modified example of the arrangement of sub-cell arrays and spare elements.
FIG. 13 is a block diagram showing a modified example of the arrangement of sub-cell arrays and spare elements.
FIG. 14 is a block diagram showing an example of a conventional redundancy system.
FIG. 15 is a block diagram showing another example of a conventional redundancy system.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Column decoder circuit, 3 ... Row decoder circuit, 4 ... Replacement control signal line, 5 ... Fuse set, 6 ... Sense amplifier row, 7 ... Column selection switch circuit, 8 ... Output terminal, 9... Spare column decoder, 11... Sub cell array, 12... Spare element (redundant cell array), 501... Addressing fuse circuit, 502. Fuse circuit, 504... Address match detection circuit, 505... AND circuit, 506.

Claims (9)

A memory cell array in which memory cells divided into a plurality of sub-cell arrays are arranged in rows and columns;
A redundant cell array disposed corresponding to each of the sub-cell arrays;
A row decoder for selecting a row of the memory cell array according to an input address;
A column decoder for selecting a column of the memory cell array according to an input address;
When mapping information indicating a correspondence relationship between an address of a defective memory cell included in the memory cell array and the redundant cell array is stored, if the address of the defective memory cell and the input address match, the match result and the A plurality of memory circuits for outputting a replacement control signal for a defective memory cell based on the mapping information;
A spare decoder that is activated in response to a replacement control signal supplied from the memory circuit and selects the redundant cell array;
The number of the memory circuits is equal to or less than the number of the redundant cell arrays. A memory cell array in which memory cells divided into a plurality of sub-cell arrays are arranged in rows and columns;
A redundant cell array disposed corresponding to each of the sub-cell arrays;
A row decoder for selecting a row of the memory cell array according to an input address;
A column decoder for selecting a column of the memory cell array according to an input address;
A plurality of first storage elements for storing addresses of defective memory cells included in the memory cell array; a plurality of second storage elements for storing mapping information indicating a correspondence relationship between the redundant cell array and each fuse set; The address of the defective memory cell stored in the first storage element is compared with the input address, and when the stored address of the defective memory cell matches the input address A plurality of comparators that output output signals; and a decoder that decodes mapping information stored in the second storage element and outputs a replacement control signal when the coincidence output signal is output from each of the comparators; A plurality of memory circuits comprising:
A spare decoder activated in response to an output signal of the decoder and selecting the redundant cell array;
The number of the memory circuits is equal to or less than the number of the redundant cell arrays. The memory circuit is
An addressing fuse circuit for storing the address of the defective memory cell;
A mapping fuse circuit for storing mapping information indicating a correspondence relationship with the redundant cell array;
An address coincidence detection circuit for performing coincidence detection between the address stored in the addressing fuse circuit and the input address;
A decoder that decodes an output signal of the mapping fuse circuit in accordance with a match output signal of the address match detection circuit and generates the replacement control signal;
The semiconductor memory device according to claim 1, comprising: The plurality of subarrays constitute a bank;
An addressing fuse circuit for storing the address of the defective memory cell;
A mapping fuse circuit for storing mapping information indicating a correspondence relationship with the redundant cell array;
A bank addressing fuse circuit for storing an address of the bank;
An enable fuse circuit indicating whether or not to use the memory circuit;
A first address coincidence detection circuit for performing coincidence detection between the address stored in the addressing fuse circuit and the input address;
A second address match detection circuit for performing match detection between the address stored in the bank address designating fuse circuit and the input address;
A first AND circuit to which a match output signal of the second address match detection circuit is supplied;
An OR circuit to which an output signal of the first AND circuit and an output signal of the enable fuse circuit are supplied;
A second AND circuit to which the coincidence output signal of the second address coincidence detection circuit and the output signal of the OR circuit are supplied;
A decoder for decoding the output signal of the mapping fuse circuit in accordance with the output signal of the second AND circuit and generating the replacement control signal;
The semiconductor memory device according to claim 1, further comprising:   Each storage circuit has a plurality of output terminals for outputting the replacement control signal, and the output terminals of the storage circuits are connected to each other by a plurality of replacement control signal lines to form a wired OR circuit. The semiconductor memory device according to claim 1, wherein:   The spare decoder is connected to one of the replacement control signal lines, and a column decoder arranged corresponding to each spare decoder is connected to the same replacement control signal line as the corresponding spare decoder via an inverter circuit. 6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is connected. An addressing fuse circuit for storing the address of the defective memory cell;
A mapping fuse circuit for storing mapping information indicating a correspondence relationship with the redundant cell array;
An address coincidence detection circuit for performing coincidence detection between the address stored in the addressing fuse circuit and the input address;
A decoder that decodes an output signal of the mapping fuse circuit in accordance with a match output signal of the address match detection circuit and generates the replacement control signal;
The semiconductor memory device according to claim 1, further comprising: A first memory cell array in which a plurality of memory cells are arranged in rows and columns;
A second memory cell array in which a plurality of memory cells are arranged in rows and columns;
A plurality of first redundancy units for replacing a first defective memory cell in the first memory cell array;
A plurality of second redundant units for replacing a second defective memory cell in the second memory cell array;
The mapping information indicating the address of the defective memory cell and the correspondence relationship with the first and second redundant units is stored, and when the address of the defective memory cell matches the input address, based on the mapping information A plurality of memory circuits that output replacement control signals for defective memory cells,
The number of the memory circuits is less than or equal to the number of the first and second redundant units,
The first memory cell array includes a first bank, the second memory cell array includes a second bank, and each of the plurality of storage circuits includes a defective memory cell and the first memory cell in the first memory cell array. A semiconductor memory device that replaces any one of the defective memory cells of the two memory cell arrays. A memory cell array in which memory cells divided into a plurality of banks are arranged in rows and columns;
A redundant cell array for replacing defective memory cells in the memory cell array;
Storing mapping information indicating a correspondence relationship between an address of a defective memory cell included in the memory cell array and the redundant cell array, address information for selecting the bank, and an address of the defective memory cell and an input address; A plurality of memory circuits that output a replacement control signal of a defective memory cell based on the mapping information and the address information ,
The number of the memory circuit, a semiconductor memory device according to claim number less der Rukoto of the redundant cell array.

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