JPH10163490A - Method for manufacturing transistor - Google Patents
Method for manufacturing transistorInfo
- Publication number
- JPH10163490A JPH10163490A JP9217581A JP21758197A JPH10163490A JP H10163490 A JPH10163490 A JP H10163490A JP 9217581 A JP9217581 A JP 9217581A JP 21758197 A JP21758197 A JP 21758197A JP H10163490 A JPH10163490 A JP H10163490A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- forming
- region
- ion implantation
- punch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
- H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】
【課題】ソース及びドレイン間のパンチスルーを阻止す
る。
【解決手段】パッド酸化膜１０２の形成された半導体基
板上に、パッド酸化膜１０２の所定領域を露出させるホ
ールを備えた絶縁膜パターンを形成し、この絶縁膜パタ
ーンをイオン注入マスクとして半導体基板内に半導体基
板と同一の導電型の不純物イオンを注入して、露出した
パッド酸化膜１０２の下にパンチスルー阻止領域１１０
を形成し、露出したパッド酸化膜１０２を取り除く。次
いで、ゲート絶縁膜を形成し、更にホール内のゲート絶
縁膜上にゲート電極を形成し、ゲート電極周辺のゲート
絶縁膜及びその下の絶縁膜パターンを順次に取り除く。
(57) [Problem] To prevent punch-through between a source and a drain. An insulating film pattern having a hole exposing a predetermined region of the pad oxide film is formed on a semiconductor substrate on which a pad oxide film is formed, and the insulating film pattern is used as an ion implantation mask in the semiconductor substrate. Is implanted with impurity ions of the same conductivity type as that of the semiconductor substrate, and under the exposed pad oxide film 102, a punch-through preventing region 110 is formed.
Is formed, and the exposed pad oxide film 102 is removed. Next, a gate insulating film is formed, a gate electrode is formed on the gate insulating film in the hole, and the gate insulating film around the gate electrode and the insulating film pattern thereunder are sequentially removed.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体素子の製造方
法に係り、特にパンチスルー阻止領域を有するＭＯＳト
ランジスタの製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS transistor having a punch-through blocking region.
【０００２】[0002]
【従来の技術】半導体素子の高集積化に伴ってゲートの
長さも縮まっている。従って、0.1〜0.35μm又はそれ以
下のゲート長を有するトランジスタの製造において解決
すべき問題の１つは、トランジスタのソース及びドレイ
ン間のパンチスルー現象を阻止することである。パンチ
スルー現象が発生すると、ソース及びドレイン間に不要
な漏れ電流が流れるようになる。2. Description of the Related Art As semiconductor devices become more highly integrated, the length of the gate is reduced. Therefore, one of the problems to be solved in the fabrication of transistors having gate lengths of 0.1-0.35 μm or less is to prevent punch-through between the source and drain of the transistor. When the punch-through phenomenon occurs, unnecessary leakage current flows between the source and the drain.
【０００３】パンチスルー現象を阻止するための従来の
方法として、ゲート電極を形成する前に、フォトマスク
を用いて局部的なイオン注入を行うものがある。この方
法では、ゲート電極を形成する前に、半導体基板中のゲ
ート電極の形成される部分以外の部分をマスクで覆った
状態で、半導体基板、即ちウェル領域に当該ウェル領域
と同一の導電型の不純物をイオン注入することによって
半導体基板内にパンチスルー阻止領域を形成する。この
ような従来の技術による局部的なイオン注入方法は、簡
単な工程で実現することが可能であるが、ゲート電極を
形成する前に局部的イオン注入を行うために、ゲート電
極を形成する際に、ゲート電極とチャンネル領域がミス
アラインされる虞がある。As a conventional method for preventing the punch-through phenomenon, there is a method in which local ion implantation is performed using a photomask before forming a gate electrode. In this method, before forming a gate electrode, a semiconductor substrate, that is, a well region, having the same conductivity type as that of the well region is formed on a semiconductor substrate in a state where a portion of the semiconductor substrate other than the portion where the gate electrode is formed is covered with a mask. A punch-through blocking region is formed in the semiconductor substrate by ion-implanting impurities. Such a local ion implantation method according to the related art can be realized by a simple process. However, in order to perform the local ion implantation before forming the gate electrode, a method for forming the gate electrode is required. In addition, the gate electrode and the channel region may be misaligned.
【０００４】ソース及びドレイン間のパンチスルーを阻
止するための従来の他の方法として、半導体基板の全面
にグローバルイオン注入を行う方法がある。この方法に
よれば、半導体基板の全面に不純物イオンを所定のドー
ズ量及びイオン注入エネルギで注入する、深いイオン注
入工程(deep implantation process) を施すことによっ
てパンチスルー阻止領域を形成する。次に、トランジス
タのスレショルド電圧を調節するために、前記深いイオ
ン注入工程時のエネルギより低いエネルギで浅いイオン
注入工程(shallow implantation process)を施すことに
よってスレショルド電圧調節領域を形成する。しかしな
がら、この方法によれば、後続工程で形成されるソース
／ドレイン領域の底面が前記パンチスルー阻止領域と重
なる。この結果、ソース／ドレインの接合静電容量が増
加し、よってトランジスタのスイッチング速度が遅くな
ってしまう。As another conventional method for preventing punch-through between a source and a drain, there is a method of performing global ion implantation on the entire surface of a semiconductor substrate. According to this method, a punch-through prevention region is formed by performing a deep implantation process in which impurity ions are implanted over the entire surface of a semiconductor substrate at a predetermined dose and ion implantation energy. Next, in order to adjust a threshold voltage of the transistor, a threshold voltage adjusting region is formed by performing a shallow ion implantation process with lower energy than the energy of the deep ion implantation process. However, according to this method, the bottom surface of the source / drain region formed in the subsequent step overlaps with the punch-through prevention region. As a result, the source / drain junction capacitance increases, and the switching speed of the transistor decreases.
【０００５】[0005]
【発明が解決しようとする課題】本発明は、上記の従来
の技術による問題点に鑑みてなされたものであって、ソ
ース／ドレイン領域の接合静電容量が増大する現象を阻
止すると共に、ゲート電極とのミスアラインメントを阻
止し得るパンチスルー阻止領域を有するトランジスタの
製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and it is an object of the present invention to prevent a phenomenon that a junction capacitance of a source / drain region is increased and to prevent a gate from being increased. It is an object of the present invention to provide a method of manufacturing a transistor having a punch-through prevention region capable of preventing misalignment with an electrode.
【０００６】[0006]
【課題を解決するための手段】前記の目的を達成するた
めに、本発明によるトランジスタの製造方法は、まずパ
ッド酸化膜の形成された半導体基板上に前記パッド酸化
膜の所定領域を露出させるホールを備えた絶縁膜パター
ンを形成する。次いで、前記絶縁膜パターンをイオン注
入マスクとして前記半導体基板内に前記半導体基板と同
一の導電型の不純物イオンを注入することによって前記
露出したパッド酸化膜の下にパンチスルー阻止領域を形
成する。次いで、前記露出したパッド酸化膜を取り除
き、結果物上にゲート絶縁膜を形成し、前記絶縁膜パタ
ーンのホール内のゲート絶縁膜上にゲート電極を形成す
る。次いで、前記ゲート電極周辺のゲート絶縁膜及びそ
の下の絶縁膜パターンを順次に取り除く。In order to achieve the above object, a method of manufacturing a transistor according to the present invention comprises: a first step of exposing a predetermined region of a pad oxide film on a semiconductor substrate having a pad oxide film formed thereon; Is formed with an insulating film pattern. Next, a punch-through blocking region is formed under the exposed pad oxide film by implanting impurity ions of the same conductivity type as the semiconductor substrate into the semiconductor substrate using the insulating film pattern as an ion implantation mask. Next, the exposed pad oxide film is removed, a gate insulating film is formed on the resultant structure, and a gate electrode is formed on the gate insulating film in the hole of the insulating film pattern. Next, the gate insulating film around the gate electrode and the insulating film pattern thereunder are sequentially removed.
【０００７】ここで、前記パンチスルー阻止領域を形成
する段階前又は後に、トランジスタのスレショルド電圧
調節領域を形成するための不純物イオン注入段階をさら
に含むことが好ましい。この際、前記パンチスルー阻止
領域を形成するための不純物イオン注入時のイオン注入
エネルギは、前記スレショルド電圧調節領域を形成する
ための不純物イオン注入時のイオン注入エネルギより高
く形成する。Here, before or after the step of forming the punch-through blocking region, the method may further include a step of implanting impurity ions for forming a threshold voltage adjusting region of the transistor. At this time, ion implantation energy at the time of implanting impurity ions for forming the punch-through blocking region is formed higher than ion implantation energy at the time of impurity ion implantation for forming the threshold voltage adjusting region.
【０００８】[0008]
【発明の実施の形態】以下、添付図面に基づき本発明の
好適な実施の形態を詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
【０００９】先ず、図１に示すように、半導体基板１０
０上にパッド酸化膜１０２を形成し、その上に絶縁膜１
０４、例えば窒化膜を所定の厚さに形成する。この絶縁
膜１０４は後続工程で形成されるゲート電極の厚さと同
一の厚さに形成することが好ましい。ここで、半導体基
板１００はトランジスタのチャンネルタイプによってＰ
ウェル又はＮウェルとなる。First, as shown in FIG.
0, a pad oxide film 102 is formed thereon, and an insulating film 1
04, for example, a nitride film is formed to a predetermined thickness. This insulating film 104 is preferably formed to have the same thickness as a gate electrode formed in a subsequent step. Here, the semiconductor substrate 100 is made of P depending on the channel type of the transistor.
Well or N-well.
【００１０】次いで、図２に示すように、絶縁膜１０４
をパタニングしてパッド酸化膜１０２の所定領域を露出
させるホールｈを有する絶縁膜パターン１０４Ａを形成
する。Next, as shown in FIG.
To form an insulating film pattern 104A having a hole h exposing a predetermined region of the pad oxide film 102.
【００１１】次いで、図３に示すように、絶縁膜パター
ン１０４Ａをイオン注入マスクとして、半導体基板１０
０内に所定の不純物イオン１０６、例えば半導体基板１
００と同一の導電型の不純物を注入することによって、
露出したパッド酸化膜１０２の下にパンチスルー阻止領
域１１０を形成する。Next, as shown in FIG. 3, the semiconductor substrate 10 is formed by using the insulating film pattern 104A as an ion implantation mask.
0, predetermined impurity ions 106, for example, the semiconductor substrate 1
By implanting impurities of the same conductivity type as 00,
A punch-through prevention region 110 is formed under the exposed pad oxide film 102.
【００１２】ここで、通常は、ＰＭＯＳトランジスタ領
域においてパンチスルー現象が発生し易いため、ＰＭＯ
Ｓトランジスタ領域に限って局部的なイオン注入を行っ
ても良い。また、パンチスルー阻止領域１１０の形成前
又は後にスレショルド電圧を調節するためのイオン注入
段階をさらに備えても良い。Here, since a punch-through phenomenon usually occurs easily in the PMOS transistor region, the PMO
Local ion implantation may be performed only in the S transistor region. The method may further include an ion implantation step for adjusting a threshold voltage before or after the formation of the punch-through blocking region 110.
【００１３】この実施の形態では、パンチスルー阻止領
域１１０を形成するための不純物イオン１０６をスレシ
ョルド電圧を調節するための不純物イオンより高いイオ
ン注入エネルギで注入することによって、パンチスルー
阻止領域１１０をスレショルド電圧調節領域（図示せ
ず）より深く形成する。例えば、スレショルド電圧を調
節するために不純物イオンを約４０ｋｅＶのエネルギと
約3.5×1012原子／cm2のドーズ量で注入する場合、パン
チスルー阻止領域１１０を形成するためには不純物イオ
ン１０６を約１００ｋｅＶのエネルギと約2.0×1012原
子／cm2のドーズ量で注入する。これは、パンチスルー
阻止領域１１０を形成するための深いイオン注入工程が
トランジスタのスレショルド電圧に及ぼす影響を最小化
するためである。In this embodiment, the impurity ions 106 for forming the punch-through blocking region 110 are implanted at a higher ion implantation energy than the impurity ions for adjusting the threshold voltage, so that the punch-through blocking region 110 is formed with a threshold. It is formed deeper than a voltage adjustment region (not shown). For example, when impurity ions are implanted with an energy of about 40 keV and a dose of about 3.5 × 10 12 atoms / cm 2 to adjust the threshold voltage, the impurity ions 106 are formed to form the punch-through blocking region 110. The implantation is performed at an energy of 100 keV and a dose of about 2.0 × 10 12 atoms / cm 2 . This is to minimize the effect of the deep ion implantation process for forming the punch-through blocking region 110 on the threshold voltage of the transistor.
【００１４】次いで、図４に示すように、パッド酸化膜
１０２のうちホールｈにより露出した部分は、パンチス
ルー阻止領域１１０を形成するためのイオン注入時に損
傷されるため、当該露出したパッド酸化膜１０２を取り
除く。Next, as shown in FIG. 4, the portion of the pad oxide film 102 exposed by the hole h is damaged at the time of ion implantation for forming the punch-through blocking region 110. Remove 102.
【００１５】次いで、図５に示すように、結果物の全面
にゲート絶縁膜１１２、例えば熱酸化膜を薄く形成す
る。この際、絶縁膜パターン１０４Ａを窒化膜で形成し
た場合は、ゲート絶縁膜１１２は、ホールｈによって露
出された半導体基板１００の表面、即ちパンチスルー阻
止領域１１０の表面にのみ選択的に形成される。Next, as shown in FIG. 5, a thin gate insulating film 112, for example, a thermal oxide film is formed on the entire surface of the resultant structure. At this time, when the insulating film pattern 104A is formed of a nitride film, the gate insulating film 112 is selectively formed only on the surface of the semiconductor substrate 100 exposed by the hole h, that is, only on the surface of the punch-through prevention region 110. .
【００１６】次いで、図６に示すように、結果物の全面
にゲート電極形成用の導電物質を蒸着した後に、ホール
ｈ内にのみ導電物質が残るよう該導電物質をエッチバッ
クして、ホールｈ内にゲート電極１２０を形成する。こ
の際、導電物質として、イオン注入マスクとして用いら
れた絶縁膜パターン１０４Ａに対して選択的な食刻が可
能な物質を用いることが好ましい。例えば、絶縁膜パタ
ーン１０４Ａを窒化膜で形成した場合は、前記導電物質
として導電性ポリサイド又はドーピングされたポリシリ
コンを用いることが好ましい。ゲート電極１２０の形成
の後、絶縁膜パターン１０４Ａ上のゲート絶縁膜１１２
が露出する。Next, as shown in FIG. 6, after a conductive material for forming a gate electrode is deposited on the entire surface of the resultant structure, the conductive material is etched back so that the conductive material remains only in the hole h. A gate electrode 120 is formed therein. At this time, it is preferable to use, as the conductive material, a material that can be selectively etched with respect to the insulating film pattern 104A used as the ion implantation mask. For example, when the insulating film pattern 104A is formed of a nitride film, it is preferable to use conductive polycide or doped polysilicon as the conductive material. After the formation of the gate electrode 120, the gate insulating film 112 on the insulating film pattern 104A is formed.
Is exposed.
【００１７】次いで、図７に示すように、露出したゲー
ト絶縁膜１１２及びその下の絶縁膜パターン１０４Ａを
順次に取り除く。Next, as shown in FIG. 7, the exposed gate insulating film 112 and the underlying insulating film pattern 104A are sequentially removed.
【００１８】その後、通常の工程によってソース／ドレ
イン領域（図示せず）を形成することによってトランジ
スタを完成する。Thereafter, source / drain regions (not shown) are formed by a usual process to complete the transistor.
【００１９】以上のように、本発明の好適な実施の形態
に係るトランジスタの製造方法によれば、ソース／ドレ
イン間のパンチスルーを阻止するための領域とゲート電
極がセルフアラインされるため、この間にミスアライン
メントが発生する現象を防止することができる。さら
に、パンチスルー阻止領域とソース／ドレイン領域が互
いに重なる部分が存在しないため、ソース／ドレインの
接合静電容量の増大を防止することができる。As described above, according to the method of manufacturing a transistor according to the preferred embodiment of the present invention, the region for preventing punch-through between the source / drain and the gate electrode are self-aligned. A phenomenon in which misalignment occurs can be prevented. Furthermore, since there is no portion where the punch-through blocking region and the source / drain region overlap each other, it is possible to prevent an increase in the source / drain junction capacitance.
【００２０】以上、本発明を好適な実施の形態を挙げて
説明したが、本発明は、この実施の形態に限定されず、
本発明の技術的思想の範囲内で当業者によって様々な変
形が可能である。Although the present invention has been described with reference to the preferred embodiment, the present invention is not limited to this embodiment.
Various modifications can be made by those skilled in the art within the scope of the technical concept of the present invention.
【００２１】[0021]
【発明の効果】本発明に拠れば、ソース／ドレイン領域
の接合静電容量の増大を抑えると共に、ゲート電極とパ
ンチスルー阻止領域とのミスアラインメントを防止する
ことができる。According to the present invention, an increase in the junction capacitance of the source / drain regions can be suppressed, and misalignment between the gate electrode and the punch-through preventing region can be prevented.
【００２２】[0022]
【図１】本発明の好適な実施の形態に係るトランジスタ
の製造方法を説明するための断面図である。FIG. 1 is a cross-sectional view for explaining a method for manufacturing a transistor according to a preferred embodiment of the present invention.
【図２】本発明の好適な実施の形態に係るトランジスタ
の製造方法を説明するための断面図である。FIG. 2 is a cross-sectional view for explaining a method for manufacturing a transistor according to a preferred embodiment of the present invention.
【図３】本発明の好ましい実施例によるトランジスタの
製造方法を説明するための断面図である。FIG. 3 is a cross-sectional view illustrating a method of manufacturing a transistor according to a preferred embodiment of the present invention.
【図４】本発明の好ましい実施例によるトランジスタの
製造方法を説明するための断面図である。FIG. 4 is a cross-sectional view illustrating a method of manufacturing a transistor according to a preferred embodiment of the present invention.
【図５】本発明の好ましい実施例によるトランジスタの
製造方法を説明するための断面図である。FIG. 5 is a cross-sectional view illustrating a method of manufacturing a transistor according to a preferred embodiment of the present invention.
【図６】本発明の好ましい実施例によるトランジスタの
製造方法を説明するための断面図である。FIG. 6 is a cross-sectional view illustrating a method of manufacturing a transistor according to a preferred embodiment of the present invention.
【図７】本発明の好ましい実施例によるトランジスタの
製造方法を説明するための断面図である。FIG. 7 is a cross-sectional view illustrating a method of manufacturing a transistor according to a preferred embodiment of the present invention.
Claims (12)
板上に前記パッド酸化膜の所定領域を露出させるホール
を備えた絶縁膜パターンを形成する段階と、 ｂ）前記絶縁膜パターンをイオン注入マスクとして前記
半導体基板内に前記半導体基板と同一の導電型の不純物
イオンを注入して、前記露出したパッド酸化膜の下にパ
ンチスルー阻止領域を形成する段階と、 ｃ）前記露出したパッド酸化膜を取り除く段階と、 ｄ）結果物上にゲート絶縁膜を形成する段階と、 ｅ）前記絶縁膜パターンのホール内のゲート絶縁膜上に
ゲート電極を形成する段階と、 ｆ）前記ゲート電極周辺のゲート絶縁膜及びその下の絶
縁膜パターンを順次に取り除く段階と、 を含むことを特徴とするトランジスタの製造方法。A) forming an insulating film pattern having holes exposing a predetermined region of the pad oxide film on a semiconductor substrate having the pad oxide film formed thereon; b) ion-implanting the insulating film pattern. Implanting impurity ions of the same conductivity type as the semiconductor substrate into the semiconductor substrate as a mask to form a punch-through blocking region below the exposed pad oxide film; and c) exposing the exposed pad oxide film. D) forming a gate insulating film on the resulting product; e) forming a gate electrode on the gate insulating film in a hole of the insulating film pattern; Removing the gate insulating film and the underlying insulating film pattern in sequence.
れることを特徴とする請求項１に記載のトランジスタの
製造方法。2. The method according to claim 1, wherein the insulating film pattern is formed of a nitride film.
又はドーピングされたポリシリコンで形成されることを
特徴とする請求項２に記載のトランジスタの製造方法。3. The method according to claim 2, wherein the gate electrode is formed of conductive polycide or doped polysilicon.
記半導体基板のＰＭＯＳ領域に限って行われることを特
徴とする請求項１に記載のトランジスタの製造方法。4. The method according to claim 1, wherein the step of implanting the impurity ions is performed only in a PMOS region of the semiconductor substrate.
れることを特徴とする請求項１に記載のトランジスタの
製造方法。5. The method according to claim 1, wherein the gate insulating film is formed of a thermal oxide film.
階の前に、トランジスタのスレショルド電圧調節領域を
形成するための不純物イオン注入段階をさらに含むこと
を特徴とする請求項１に記載のトランジスタの製造方
法。6. The method of claim 1, further comprising, before forming the punch-through blocking region, implanting an impurity ion to form a threshold voltage adjusting region of the transistor. Method.
めの不純物イオン注入時のイオン注入エネルギは、前記
スレショルド電圧調節領域を形成するための不純物イオ
ン注入時のイオン注入エネルギより高いことを特徴とす
る請求項６に記載のトランジスタの製造方法。7. An ion implantation energy at the time of impurity ion implantation for forming the punch-through blocking region is higher than an ion implantation energy at the time of impurity ion implantation for forming the threshold voltage adjusting region. A method for manufacturing a transistor according to claim 6.
酸化法によって行われることを特徴とする請求項６に記
載のトランジスタの製造方法。8. The method according to claim 6, wherein the step of forming the gate insulating film is performed by a thermal oxidation method.
後に、トランジスタのスレショルド電圧調節領域を形成
するための不純物イオン注入段階をさらに含むことを特
徴とする請求項１に記載のトランジスタの製造方法。9. The method of claim 1, further comprising, after forming the punch-through region, implanting impurity ions for forming a threshold voltage adjusting region of the transistor.
ための不純物イオン注入時のイオン注入エネルギは、前
記スレショルド電圧調節領域を形成するための不純物イ
オン注入時のイオン注入エネルギより高いことを特徴と
する請求項９に記載のトランジスタの製造方法。10. An ion implantation energy at the time of impurity ion implantation for forming the punch-through blocking region is higher than an ion implantation energy at the time of impurity ion implantation for forming the threshold voltage adjusting region. A method for manufacturing a transistor according to claim 9.
熱酸化法によって行われることを特徴とする請求項９に
記載のトランジスタの製造方法。11. The step of forming the gate insulating film,
The method according to claim 9, wherein the method is performed by a thermal oxidation method.
を蒸着する段階と、 前記絶縁膜パターンのホール内にのみ導電物質が残るよ
う前記導電物質をエッチバックする段階と、 を含むことを特徴とする請求項１に記載のトランジスタ
の製造方法。12. The step of forming the gate electrode comprises: depositing a conductive material on the entire surface of the resultant structure on which the gate insulating film is formed; and forming the conductive material only in holes of the insulating film pattern. The method of claim 1, further comprising: etching back a conductive material.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960058494A KR19980039470A (en) | 1996-11-27 | 1996-11-27 | Manufacturing method of semiconductor device |
| KR96-58494 | 1996-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10163490A true JPH10163490A (en) | 1998-06-19 |
Family
ID=19484018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9217581A Withdrawn JPH10163490A (en) | 1996-11-27 | 1997-08-12 | Method for manufacturing transistor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH10163490A (en) |
| KR (1) | KR19980039470A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417634A (en) * | 2017-02-02 | 2018-08-17 | 恩智浦有限公司 | Method for manufacturing semiconductor switching device |
| CN114999907A (en) * | 2022-08-08 | 2022-09-02 | 合肥新晶集成电路有限公司 | Manufacturing method of gate oxide layer and manufacturing method of field effect transistor |
-
1996
- 1996-11-27 KR KR1019960058494A patent/KR19980039470A/en not_active Withdrawn
-
1997
- 1997-08-12 JP JP9217581A patent/JPH10163490A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417634A (en) * | 2017-02-02 | 2018-08-17 | 恩智浦有限公司 | Method for manufacturing semiconductor switching device |
| CN108417634B (en) * | 2017-02-02 | 2023-09-15 | 恩智浦有限公司 | Method for manufacturing semiconductor switching device |
| CN114999907A (en) * | 2022-08-08 | 2022-09-02 | 合肥新晶集成电路有限公司 | Manufacturing method of gate oxide layer and manufacturing method of field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980039470A (en) | 1998-08-17 |
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