JPH10111671A - Liquid crystal display - Google Patents

Abstract

(57) Abstract: A liquid crystal display device capable of performing fine and high-precision drive control independent of an external clock signal by generating an internal clock signal unique to the device, and improving display quality. I will provide a. A clock generation circuit generates an internal clock signal independent of an external clock signal. The correction pulse generation circuit 114 generates a correction pulse based on the internal clock signal. The control circuit 107 superimposes the correction pulse on the driving signal for the signal line driving circuit, and outputs the corrected driving signal for the signal line driving circuit to the signal line driving circuit 105. The signal line driving circuit 105 sequentially shifts the corrected driving signal for the signal line driving circuit, and finally applies the corrected driving signal to the signal line 104 as a signal line driving signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that performs internal drive control based on a clock signal.

[0002]

2. Description of the Related Art A conventional liquid crystal display device will be described below with reference to the drawings. FIG. 7 is a block diagram showing a configuration of a conventional liquid crystal display device.

Referring to FIG. 7, the liquid crystal display device includes a liquid crystal panel 4, a signal line driving circuit 5, a scanning line driving circuit 6, and a control circuit 7. The plurality of signal lines 1 and the plurality of scanning lines 2
Pixels 3 are arranged in a matrix at the intersection of the signal line 1 and the scanning line 2. The liquid crystal panel 4 is driven by a signal line driving circuit 5 and a scanning line driving circuit 6. The signal line driving circuit 5 and the scanning line driving circuit 6 are controlled by a control circuit 7. The control circuit 7 adjusts the drive timing of the liquid crystal panel 4 using a frame signal 8, a horizontal synchronization signal 9, and a shift clock signal 10 supplied from outside the device as clock signals. That is, the control circuit 7 of the conventional liquid crystal display device performs drive control using only a clock signal supplied from the outside.

[0004]

However, in the above configuration, the generation of all the timings in the control circuit must be performed only by the external clock signal, that is, by the frame signal, the horizontal synchronizing signal, and the shift clock signal. Must. On the other hand, when the voltage waveform of the drive signal of the signal line is corrected to reduce display unevenness of the liquid crystal display device, or when the correction pulse is superimposed on the drive signal of the signal line, the position of the correction pulse and the pulse You need to decide the width.

In this case, in the conventional liquid crystal display device, a horizontal synchronizing signal input from the outside and a timer circuit using a time constant circuit including a resistor and a capacitor are used.
The position of the correction pulse and its pulse width are set.
As a result, if the start position and the pulse width of the correction pulse are to be set finely and with high precision, the configuration of the timer circuit becomes complicated, and there is a problem that the position and the pulse width of the correction pulse cannot be set with high precision. Was.

Further, since the shift clock signal is the clock signal having the highest frequency input to the device, there is another problem that the drive voltage of the signal line cannot be controlled at a timing finer than the shift clock signal.

In view of the above, the present invention provides a device-specific internal clock signal to perform fine and accurate drive control independent of an external clock signal.
It is an object to provide a liquid crystal display device capable of improving display quality.

[0008]

To achieve the above object, a liquid crystal display device according to the present invention comprises a liquid crystal layer inserted between pixel electrodes in which a plurality of signal lines and a plurality of scanning lines are arranged in a matrix. A liquid crystal panel, a signal line driving circuit for applying a signal line driving signal to a signal line, a scanning line driving circuit for applying a scanning line driving signal to a scanning line, and at least one of a signal line driving circuit and a scanning line driving circuit. Control circuit for outputting a drive signal to control at least one of a signal line drive circuit and a scan line drive circuit, and an internal clock signal generating means for generating an internal clock signal independent of an external clock signal supplied from outside the device The control circuit controls at least one of the signal line driving circuit and the scanning line driving circuit using the internal clock signal.

With the above structure, an internal clock signal independent of the external clock signal can be generated by the internal clock signal generating means provided inside the device, and the signal line drive can be performed precisely and precisely without depending on the external clock signal. The circuit and the scan line driver circuit can be driven and controlled. As a result, fine and high-precision drive control can be performed independently of the external clock signal, and display quality can be improved.In addition, the control circuit can use the internal clock signal based on device-specific information. It is preferable to control at least one of the signal line driving circuit and the scanning line driving circuit. In this case, it is possible to drive and control the signal line driving circuit and the scanning line driving circuit more finely and with high precision for each device according to the information unique to the device.

In addition, the apparatus further includes a correction pulse generating means for generating a correction pulse for correcting a drive signal using the internal clock signal, and the control circuit uses the correction pulse to generate a correction pulse independent of the external clock signal. It is preferable to correct the voltage waveform of the drive signal at the timing described below. In this case, since the voltage waveform of the drive signal can be corrected at a timing unique to the device, the voltage waveform of the signal line drive signal or the scan line drive signal can be corrected according to the correction conditions unique to the device.

It is preferable that at least one of the start position and the pulse width of the correction pulse is changed in accordance with the correction amount of the voltage waveform of the drive signal, and the correction pulse is superimposed on the drive signal. In this case, the voltage waveform of the signal line driving signal or the scanning line driving signal can be corrected more finely and with high accuracy for each device by the correction condition unique to the device.

Further, the apparatus further includes a mask signal generating means for generating a mask signal for masking the scanning line drive signal using the internal clock signal, wherein the control circuit uses the mask signal to generate a mask signal independent of the external clock signal. It is preferable to mask the drive signal at the timing unique to the device. In this case, since the drive signal can be masked at the timing unique to the device, the signal line drive signal or the scan line drive signal can be masked according to the mask condition specific to the device.

It is preferable that the drive signal is masked by changing the mask width of the mask signal in accordance with the mask amount of the drive signal. In this case, the voltage waveform of the signal line driving signal or the scanning line driving signal can be corrected more finely and with high accuracy for each device according to the mask condition specific to the device.

In addition, the control circuit further includes a timer for counting a predetermined time by using the internal clock signal. When the control circuit detects that the external clock signal is stopped for a certain period based on a signal from the timer, It is preferable to control the signal line driver circuit and the scan line driver circuit so as to stop driving the signal line and the scan line. In this case, since the time can be measured without depending on the external clock signal, abnormal operation of the device due to no signal state can be prevented, and power consumption can be reduced by preventing wasteful power consumption. Can be.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. (Embodiment 1) First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of the liquid crystal display device according to the first embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device includes a liquid crystal panel 104, a signal line driving circuit 105, and a scanning line driving circuit 1.
06, a control circuit 107, a clock generation circuit 112, and a correction pulse generation circuit 114.

The liquid crystal panel 104 includes a plurality of signal lines 101.
A liquid crystal layer is inserted between pixel electrodes in which a plurality of scanning lines 102 are arranged in a matrix. Here, the pixel 103 is a capacitive load, and is an intersection of the signal line 101 and the scanning line 102. The frame signal 108, the horizontal synchronization signal 109, the shift clock signal 110, and the data signal 111 are input to the control circuit 107. Clock generation circuit 112 generates an internal clock signal input to control circuit 107. Also, the clock generation circuit 1
The internal clock signal generated by the control circuit 12
07, it is input to the correction pulse generation circuit 114 as the internal clock signal 113.

The control circuit 107 outputs a drive signal for the signal line drive circuit to the signal line drive circuit 105, and controls the signal line drive circuit 105. The signal line driving circuit 105 sequentially shifts the driving signal for the signal line driving circuit, outputs the signal to the signal line 101 as a signal line driving signal, and drives the signal line 101. Further, the control circuit 107 outputs a driving signal for the scanning line driving circuit to the scanning line driving circuit 106 and controls the scanning line driving circuit 106. The scanning line driving circuit 106 sequentially shifts the driving signal for the scanning line driving circuit, outputs the signal to the scanning line 102 as a scanning line driving signal, and drives the scanning line 102.

Next, the characteristic operation of the liquid crystal display device according to the first embodiment configured as described above will be described. The waveform of the signal line drive signal applied by the signal line drive circuit 105 is distorted at the time of switching from the L level to the H level. As a result, the effective value of the drive voltage is reduced as compared with a state without switching from the L level to the H level. Therefore, display unevenness called vertical crosstalk occurs in the display. In the present embodiment, in order to correct this, a correction pulse for compensating for the decrease in the effective value is superimposed on the drive signal for the signal line drive circuit, and finally, the voltage waveform of the signal line drive signal Has been corrected. Specifically, when the drive signal for the signal line drive circuit is at the H level and the correction pulse is at the H level, the H level of the drive signal for the signal line drive circuit is emphasized, and the drive signal for the signal line drive circuit becomes When the correction pulse is at the H level at the L level, the L level of the drive signal for the signal line driving circuit is emphasized.

For this reason, a counter or the like composed of a digital circuit is used as the correction pulse generating circuit 114. The correction pulse generation circuit 114 outputs the horizontal synchronization signal 109
, And is counted each time the internal clock signal 113 is sent.
For example, the voltage is switched to H level or L level by the number of pulses set based on the duty ratio of the drive signal and the like.
Here, the clock generation circuit 112 built in the device
Is an independent clock signal from the frame signal 108, the horizontal synchronization signal 109, and the shift clock signal 110, which are external clock signals, and thus does not depend on the frequency of the external clock signal.
In addition, it is not affected by the frequency fluctuation of the external clock signal. As a result, the correction pulse generation circuit 114 can generate a correction pulse having a desired pulse waveform.

The control circuit 107 includes a frame signal 108, which is an external clock signal, a horizontal synchronizing signal 109, a shift clock signal 110, and a data signal 111.
Based on the correction pulse, drive signals for a signal line drive circuit and a scan line drive circuit having a predetermined voltage waveform are generated. Signal line driving circuit 105 and scanning line driving circuit 10
6 drives the signal lines 101 and the scanning lines 102 of the liquid crystal panel 104 based on these drive signals.

Next, the operation of correcting a drive signal using the correction pulse generating circuit configured as described above will be described. FIG. 2 is a waveform diagram for explaining a correction operation of the signal line drive signal using the correction pulse generation circuit 114 shown in FIG. In FIG. 2, reference numeral 115 denotes a frame signal;
Is a horizontal synchronizing signal, 117 is an internal clock signal, 118 is an original drive signal for the signal line drive circuit, 119 is a correction pulse, and 120 is a drive signal after correction for the signal line drive circuit.

The correction pulse 119 generated by the correction pulse generation circuit 114 based on the internal clock signal 117 is
The control circuit 107 superimposes the signal on the original drive signal 118 for the signal line drive circuit. As a result, the original drive signal 118 for the signal line drive circuit becomes the corrected drive signal 120 for the signal line drive circuit, and is finally applied to the signal line 104 by the signal line drive circuit 105 as a signal line drive signal. Is done.

As described above, according to the present embodiment, by providing the clock generation circuit inside the device, the voltage waveform of the drive signal can be corrected at a timing independent of the external clock and with high accuracy. . Further, stable correction can be performed for each device by using correction conditions unique to the device. When the liquid crystal display device according to the present embodiment was actually manufactured, display unevenness was improved as compared with the conventional liquid crystal display device.

In this embodiment, if the control is performed so as to adjust the start position of the correction pulse and the width of the correction pulse every time the correction pulse is superimposed, high-precision display correction more suitable for a display image can be performed. Is also clear.

In this embodiment, the correction pulse is superimposed on the drive signal for the signal line drive circuit. However, the same effect can be obtained by superimposing the correction pulse on the drive signal for the scan line drive circuit. be able to. (Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a block diagram illustrating a configuration of a liquid crystal display device according to the second embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display device includes a liquid crystal panel 124, a signal line driving circuit 125, and a scanning line driving circuit 1.
26, a control circuit 127, a clock generation circuit 132, and a mask signal generation circuit 134.

The liquid crystal panel 124 includes a plurality of signal lines 121.
And a plurality of scanning lines 122 arranged in a matrix, and a liquid crystal layer is inserted between pixel electrodes. Here, the pixel 123 is a capacitive load, and is an intersection of the signal line 121 and the scanning line 122. The frame signal 128, the horizontal synchronization signal 129, the shift clock signal 130, and the data signal 131 are input to the control circuit 127. Clock generation circuit 132 generates an internal clock signal input to control circuit 127. Also, the clock generation circuit 1
The internal clock signal generated by the control circuit 1
27, is input to the mask signal generation circuit 134 as an internal clock signal 133.

The control circuit 127 outputs a drive signal for the signal line drive circuit to the signal line drive circuit 125, and controls the signal line drive circuit 125. The signal line drive circuit 125 sequentially shifts the drive signal for the signal line drive circuit, outputs the signal as a signal line drive signal to the signal line 121, and drives the signal line 121. Further, the control circuit 127 outputs a driving signal for the scanning line driving circuit to the scanning line driving circuit 126 and controls the scanning line driving circuit 126. The scanning line driving circuit 126 sequentially shifts the driving signal for the scanning line driving circuit and outputs it as a scanning line driving signal to the scanning line 122 to drive the scanning line 122.

Next, the characteristic operation of the liquid crystal display device according to the second embodiment configured as described above will be described. The waveform of the scan line drive signal applied by the scan line drive circuit 126 is distorted when switching from the L level to the H level. Also, due to the dielectric anisotropy of the liquid crystal, the capacitance is small during off display,
When the display is on, the capacity is large. As a result, the rounding of the waveform varies depending on the brightness of the display image, and display unevenness occurs. Therefore, display unevenness called horizontal crosstalk occurs in the display. In this embodiment, in order to correct this, the scanning line drive signal is masked with a mask width that compensates for the difference in the effective value due to the difference in roundness.

Therefore, a counter or the like composed of a digital circuit is used as the mask signal generation circuit 114.
The mask signal generation circuit 114 is reset by the horizontal synchronization signal 129 and counts each time the internal clock signal 133 is sent. Here, the internal clock signal generated by the clock generation circuit 132 built in the device includes a frame signal 128 which is an external clock signal,
Horizontal synchronization signal 129 and shift clock signal 130
Is independent of the frequency of the external clock signal, and is not affected by the frequency fluctuation of the external clock signal. Therefore, the mask signal generation circuit 114 can switch the voltage to the H level with the number of pulses set in advance based on the information of the apparatus, and generate a desired mask signal.

The control circuit 127 includes a frame signal 128 as an external clock signal, a horizontal synchronizing signal 129, a shift clock signal 130, and a data signal 131.
Based on the mask signal, drive signals for a signal line drive circuit and a scan line drive circuit having a predetermined voltage waveform are generated. Signal line driving circuit 125 and scanning line driving circuit 1
26 drives the signal lines 121 and the scanning lines 122 of the liquid crystal panel 124 based on these drive waveforms.

Next, the masking operation of the driving signal using the mask signal generating circuit configured as described above will be described. FIG. 4 is a waveform diagram for explaining a mask operation of a signal line drive signal using mask signal generation circuit 134 shown in FIG. In FIG. 4, reference numeral 135 denotes a frame signal;
6 is a horizontal synchronization signal, 137 is an internal clock signal, 138
Is an original driving signal for the scanning line driving circuit, 139 is a mask signal, and 140 is a driving signal after masking for the scanning line driving circuit.

The mask signal 139 generated by the mask signal generating circuit 134 based on the internal clock signal 138 is
The control circuit 127 performs an AND operation with the original driving signal 138 for the scanning line driving circuit. As a result, the original drive signal 138 for the scan line drive circuit becomes the masked drive signal 140 for the scan line drive circuit, and finally the scan line drive circuit 126 applies the scan line drive signal 126 to the scan line 122 as a scan line drive signal. Applied.

As described above, according to the present embodiment, by providing the clock generation circuit inside the device, the drive signal can be masked with high timing with a timing unique to the device independent of the external clock signal. Can be. Furthermore, it is possible to perform a stable mask operation for each device by using a mask condition specific to the device. Actually, when the liquid crystal display device of the present embodiment was manufactured, display unevenness was improved as compared with the conventional liquid crystal display device.

Also, in this embodiment, it is apparent that if the control is performed so that the width of the mask is adjusted each time the mask is applied, it is possible to perform high-accuracy display correction more suitable for the displayed image. It is also apparent that the same effect as in the present embodiment can be obtained by masking the rear side of the drive signal for the scan line drive circuit.

Although the driving signal for the scanning line driving circuit is masked in the present embodiment, the same effect can be obtained by masking the driving signal for the signal line driving circuit. (Embodiment 3) Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a block diagram illustrating a configuration of a liquid crystal display device according to the third embodiment of the present invention.

Referring to FIG. 5, the liquid crystal display device includes a liquid crystal panel 144, a signal line driving circuit 145, and a scanning line driving circuit 1.
46, a control circuit 147, a clock generation circuit 152, and a counting circuit 154.

The liquid crystal panel 144 includes a plurality of signal lines 141.
And a plurality of scanning lines 142 are formed by inserting a liquid crystal layer between pixel electrodes arranged in a matrix. Here, the pixel 143 is a capacitive load and is an intersection of the signal line 141 and the scanning line 142. The frame signal 148, the horizontal synchronization signal 149, the shift clock signal 150, and the data signal 151 are input to the control circuit 147. Clock generation circuit 152 generates an internal clock signal input to control circuit 147. Also, the clock generation circuit 1
The internal clock signal generated by the control circuit 1
47, is input to the counting circuit 154 as an internal clock signal 153.

The control circuit 147 generates a drive signal for a signal line drive circuit having a predetermined voltage waveform based on the frame signal 148, the horizontal synchronization signal 149, the shift clock 150, and the data signal 151, which are external clock signals. The signal is output to the line driving circuit 145 and the signal line driving circuit 145 is controlled. The signal line driver circuit 145 sequentially shifts the drive signal for the signal line driver circuit, outputs the signal as a signal line drive signal to the signal line 141, and drives the signal line 141. Similarly, the control circuit 147 outputs a driving signal for the scanning line driving circuit having a predetermined voltage waveform to the scanning line driving circuit 146, and controls the scanning line driving circuit 146. Scan line drive circuit 146
Is to sequentially shift the driving signal for the scanning line driving circuit and output it to the scanning line 142 as a scanning line driving signal,
2 is driven. The counting circuit 154 outputs a display drive on / off signal 155 to the control circuit 147. The display drive on / off signal 155 indicates a display drive state at H level and a display drive stop state at L level.

Next, the characteristic operation of the liquid crystal display device according to the third embodiment configured as described above will be described. As the counting circuit 154, a counter made of a digital circuit or the like is used. The counting circuit 154 is reset by the horizontal synchronizing signal 149,
Count every time 3 is sent. Here, the internal clock signal generated by the clock generation circuit 152 incorporated in the device is a clock signal independent of the frame signal 148, the horizontal synchronization signal 149, and the shift clock signal 150, which are external clock signals. ,
It does not depend on the frequency of the external clock and is not affected by frequency fluctuations of the external clock. The counting circuit 154 sends an L level display drive on / off signal 155 to the control circuit 147 when the pulse of the horizontal synchronization signal 149 does not appear in the preset number of pulses. The control circuit 147 which has received the display drive on / off signal 155 at the L level stops the drive control to the signal line drive circuit 147 and the scan line drive circuit 146.

Next, a driving stop operation using the counting circuit configured as described above will be described. FIG. 6 is a waveform diagram for explaining a driving stop operation using the counting circuit 154 shown in FIG. 6, reference numeral 156 denotes a frame signal, 157 denotes a horizontal synchronizing signal, 158 denotes an internal clock signal, 159 denotes a display drive on / off signal, and 160 denotes a horizontal synchronizing pulse which should appear originally.

The counting circuit 154 is reset by the horizontal synchronizing signal 157 and counts each time the internal clock signal 158 is sent. At this time, when the horizontal synchronization pulse 160 which should appear originally does not occur and the horizontal synchronization pulse does not occur even after a certain period of time, the display drive on / off signal 159 switches from the H level to the L level, It is sent to the control circuit 147.

As described above, according to the present embodiment, by providing the clock generation circuit inside the device, it is possible to have a timekeeping function independent of the external clock signal, and to input the horizontal synchronizing signal for a certain time or more. It is possible to perform control such that driving is stopped in the case where the non-operation state continues. Therefore, a no-signal state can be avoided, and abnormal operation of the apparatus due to the no-signal state can be prevented. In addition, the time counting function measures the elapsed time after the power of the apparatus is turned on, and stops the driving when a predetermined time has elapsed, thereby saving power.

As described above, each embodiment of the present invention has been described. However, it is also possible to arbitrarily combine the embodiments, and in this case, the effect of each embodiment can be obtained.

[0046]

As described above, according to the present invention,
By providing a clock generation circuit inside, a fine and highly accurate correction operation can be performed for each device using a clock signal independent of an external clock signal. As a result, display unevenness such as vertical crosstalk and horizontal crosstalk can be reduced, and higher quality display can be obtained. In addition, it is possible to measure the time independently of the external clock, thereby preventing abnormal operation of the apparatus due to no signal state and saving power.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a waveform chart for explaining a drive signal correction operation using the correction pulse generation circuit shown in FIG. 1;

FIG. 3 is a block diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a waveform chart for explaining a mask operation of a drive signal using the mask signal generation circuit shown in FIG. 3;

FIG. 5 is a block diagram illustrating a configuration of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 6 is a waveform chart for explaining a drive stop operation using the counting circuit shown in FIG. 5;

FIG. 7 is a block diagram showing a configuration of a conventional liquid crystal display device.

[Explanation of symbols]

 101 signal line 102 scanning line 103 pixel 104 liquid crystal panel 105 signal line driving circuit 106 scanning line driving circuit 107 control circuit 108 frame signal 109 horizontal synchronization signal 110 shift clock signal 111 data signal 112 clock generation circuit 113 internal clock 114 correction pulse generation circuit

Claims (8)

[Claims] 1. A liquid crystal panel having a liquid crystal layer inserted between pixel electrodes in which a plurality of signal lines and a plurality of scanning lines are arranged in a matrix, and a signal line drive for applying a signal line drive signal to the signal lines. A scanning line driving circuit for applying a scanning line driving signal to the scanning line; a driving signal output to at least one of the signal line driving circuit and the scanning line driving circuit; A control circuit for controlling at least one of the line drive circuits; and an internal clock signal generating means for generating an internal clock signal independent of an external clock signal supplied from outside the device, wherein the control circuit includes the internal clock signal. Wherein at least one of the signal line driving circuit and the scanning line driving circuit is controlled by using the liquid crystal display device. 2. The liquid crystal display according to claim 1, wherein the control circuit controls at least one of the signal line driving circuit and the scanning line driving circuit based on information unique to the device using the internal clock signal. apparatus 3. The control circuit according to claim 2, further comprising: a correction pulse generating unit configured to generate a correction pulse for correcting the drive signal using the internal clock signal, wherein the control circuit uses the correction pulse to generate the external clock signal. 3. The liquid crystal display device according to claim 1, wherein the voltage waveform of the drive signal is corrected at a timing unique to the device independent of the device. 4. The liquid crystal according to claim 3, wherein at least one of a start position and a pulse width of the correction pulse is changed according to a correction amount of a voltage waveform of the drive signal, and the correction pulse is superimposed on the drive signal. Display device. 5. The apparatus according to claim 1, further comprising: a mask signal generating unit configured to generate a mask signal for masking the drive signal using the internal clock signal. The control circuit uses the mask signal to generate the external clock signal. 5. The liquid crystal display device according to claim 1, wherein the drive signal is masked at a timing unique to the device independent of the signal. 6. The liquid crystal display device according to claim 5, wherein the drive signal is masked by changing a mask width of the mask signal according to a mask amount of the drive signal. 7. The liquid crystal display device according to claim 1, further comprising a timer for measuring a predetermined time by using the internal clock signal. 8. The control circuit, when detecting that the external clock signal has been stopped for a certain period based on a signal from the timing unit, stops driving the signal line and the scanning line. The liquid crystal display device according to claim 7, wherein the liquid crystal display device controls the signal line driving circuit and the scanning line driving circuit.