JP2003177725A - Active matrix type planar display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type planar display device of a Cs-ON gate type, in which flicking is decreased without changing the conditions of a manufacturing process. <P>SOLUTION: In this planar display device, a DC counter voltage is applied to a counter electrode and a scanning line driving circuit makes an OFF time when a gate signal changes from a first potential being a potential in which TFTs (thin film transistors) are in OFF states to a third potential in which the TFTs compensate the reduction of potentials of pixel electrodes to be earlier than a compensation rising time when a gate signal to be supplied to a scanning line existing at the preceding stage of the scanning line changes from the third potential to a second potential as to the gate signal which is supplied to the scanning lines. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix flat panel display device, and more particularly to a Cs on-gate flat panel display device.

[0002]

2. _Description of the _Related Art In a liquid crystal display device, in order to prevent the charge held in the liquid crystal capacitance C _lc from leaking through a switching element and deteriorating the display quality, the liquid crystal capacitance C _lc is arranged in parallel with the liquid crystal capacitance C _{lc of} each pixel. A storage capacitor Cs is added.

There are two types of configurations of the array substrate to which the auxiliary capacitance Cs is added.

The first type is to provide an auxiliary capacitance line in parallel with a scanning line via a pixel electrode and an insulating film,
It is a Cs independent line type configured to obtain a capacitance between the pixel electrode and the auxiliary capacitance line.

The second type is a Cs on-gate type which is constructed so as to obtain a capacitance between the pixel electrodes which are partially overlapped with the scanning line in the preceding stage in the scanning direction via the insulating film. This Cs on-gate type has an advantage that a high aperture ratio can be achieved because unnecessary wiring such as an auxiliary capacitance line can be reduced.

[0006]

In the liquid crystal display device as described above, a thin film transistor (hereinafter referred to as a TFT) is turned off from an ON state by a gate signal.
Since the polarity of the voltage applied to the parasitic capacitance of the TFT is reversed when switching to the F state, the charge is redistributed with respect to the charges accumulated in the pixel electrode and the electrode having the same potential as the pixel electrode. It is known that the potential of the pixel electrode drops. This amount of potential decrease depends not only on the magnitude of the capacitance electrically connected to the pixel electrode, but also on the potential of the pixel electrode before the potential decrease and the potential waveform of the gate signal due to the time constant of the scanning line as shown in FIG. Also varies depending on the degree of distortion (in FIG. 5, the dotted line is a distorted waveform).

Therefore, particularly in a large-sized, high-definition liquid crystal display device, the time constant of the scanning line is large, and the amount of potential drop of the pixel electrode cannot be made uniform on the display screen. That is, the left and right sides of the screen have different potential drop amounts. As a result, the voltage applied to the capacitor composed of the pixel electrode and the counter electrode becomes non-uniform within the display screen, causing flicker and degrading the display screen quality.

In the Cs on-gate type liquid crystal display device described above, the following method has been proposed as a method for reducing the decrease in the potential of the pixel electrode.

According to the method, the waveform of the gate signal is different.
This method has two potentials (Japanese Patent Laid-Open No. 2000-3556).
0 etc.).

That is, as shown in FIG.
From the first potential to the second potential, a first potential for setting the N state, a second potential for setting the OFF state, and a third potential for compensating for a potential drop of the pixel electrode are provided. After the displacement, the potential becomes the third potential, then returns to the second potential, and then is held at the second potential until the next scanning period.

As a result, the potential of the gate signal when the TFT of the pixel is switched from the ON state to the OFF state is displaced from the first potential to the second potential. After that, the potential shifts from the second potential to the third potential, and in synchronization with this, the potential of the gate signal in the previous stage shifts from the third potential to the second potential.

Since the pixel electrode and the scanning line in the preceding stage are capacitively coupled via the insulating film, the decrease in the potential of the pixel electrode due to the decrease in the potential of the gate signal is caused by the increase in the potential of the preceding gate signal. The increase in the potential of the pixel electrode will offset each other. Therefore, the amount of decrease in the potential of the pixel electrode can be reduced.

However, in the conventional Cs on-gate type liquid crystal display device, there is a time lag from the displacement of the potential of the gate signal from the first potential to the second potential to the displacement of the third potential. , Equal to the phase difference between the waveform of the gate signal and the image signal of the signal line. This phase difference depends on the time constant of the scanning line, and the time for the potential of the gate signal to reach the potential for turning on the TFT is different in the screen. Therefore, the phase of the potential of the image signal should be delayed by the time constant at the end of the scanning line. The purpose is to make the time of the ON state of the TFT uniform in the display screen.

The time lag is inevitable because the relationship with the display quality is not clear and there is only one time count pulse for setting the phase difference. is there.

On the power supply side of the potential of the gate signal, the distortion of the potential of the gate signal due to the time constant is small, and the potential drops instantly from the first potential to the second potential. For this reason, the potential of the pixel electrode also instantaneously drops, and when the potential of the gate signal in the preceding stage changes from the second potential to the third potential, the potential of the pixel electrode has already dropped.

However, in the center of the display screen, the potential of the pixel electrode is distorted, and therefore the potential of the pixel electrode also needs to be lowered.
When the potential of the gate signal changes from the second potential to the third potential, the reduction of the potential of the pixel electrode may not be completed yet.

At this time, the potential of the gate signal in the preceding stage is displaced from the third potential to the second potential, but the difference between the first potential and the second potential causes the second potential and the third potential to change. Since the difference between the two is smaller, the potential change is affected by the same time constant, but the change from the third potential to the second potential is relatively quick, and the potential of the pixel electrode accompanying this potential change is relatively rapid. Also rises quickly.

As a result, the potential of the pixel electrode begins to rise before the reduction of the potential of the pixel electrode is completed, so that the potential of the gate signal reaches a potential different from that of the pixel electrode on the power supply side.

Similarly, the potential of the pixel electrode on the terminal side of the scanning line reaches a potential different from that on the power supply side of the gate signal and the center of the display screen.

In this state, the optimum potential of the counter electrode with respect to the potential of the pixel electrode greatly varies depending on the position in the display screen, so that flicker occurs.

In order to reduce flicker, a method of changing to a low resistance wiring material or a method of forming a thick film may be mentioned with the aim of reducing the time constant of the scanning line. However, such a change in the manufacturing process condition is not preferable because it may lead to a decrease in the uniformity of the pattern accuracy or the like and may cause a new defect, or may increase the manufacturing cost.

Therefore, in view of the above problems, the present invention provides Cs
In an on-gate type active matrix flat panel display device, without changing the manufacturing process conditions,
We propose a method that reduces flicker.

[0023]

According to a first aspect of the present invention, a plurality of signal lines and scanning lines which are arranged orthogonally to each other and a switching element are arranged near an intersection of the signal lines and the scanning lines. An array substrate provided with a pixel electrode that is formed into a counter electrode, a counter substrate that forms a counter electrode with respect to the array substrate, a light modulation layer disposed between the array substrate and the counter substrate, and an image signal A signal line drive circuit for supplying a signal line, and a scanning line drive circuit for supplying a gate signal for writing the image signal to the pixel electrode to the scanning line with the switching element in an ON state. The pixel electrode at least protrudes so as to intersect with the preceding scanning line with respect to the scanning direction sequentially supplied, and the gate signal causes a first potential for turning on the switching element; Different from the second electric potential for turning off the switching element and the first electric potential and the second electric potential, compensating for the decrease of the pixel electric potential of the pixel electrode written at the first electric potential. In the active matrix flat panel display device, which is composed of at least a third potential and holds the pixel potential of the pixel electrode at the second potential, the scanning line driving circuit is supplied to the scanning line. The OFF time, which is the time at which the gate signal is displaced from the second potential to the third potential, is the second potential from the third potential of the gate signal supplied to the scanning line preceding the scanning line. The active matrix flat panel display device is characterized in that it is earlier or later than the compensation rising time, which is the time at which it is displaced.

The invention according to claim 2 is characterized in that a DC counter potential is applied to the counter electrode, and the third potential is lower than the second potential. It is a flat display device.

According to a third aspect of the present invention, the scanning line driving circuit generates a time for holding the first potential of the gate signal by a first timing signal and sets a time for holding the third potential. A second timing signal different from the first timing signal
The active matrix flat panel display device according to claim 1, wherein the active matrix flat panel display device is generated by the timing signal.

According to a fourth aspect of the present invention, an alternating counter potential is applied to the counter electrode, the second potential changes in two steps in accordance with the reversal of the counter potential, and the third potential is the 2. The active matrix type flat panel display device according to claim 1, wherein the value takes a value between two levels of the second potential.

According to a fifth aspect of the present invention, there is provided the active matrix type flat display device according to the first to fourth aspects, wherein the light modulation layer is a liquid crystal layer.

According to a sixth aspect of the present invention, the switching element is a thin film transistor.
5 is an active matrix type flat panel display device.

The operation of the active matrix flat panel display device of the present invention will be described.

The compensation rising time, which is the time when the second potential of the gate signal supplied to the scanning line is changed to the third potential, is set to the third of the gate signal supplied to the scanning line preceding the scanning line. By making it earlier than the OFF time, which is the time at which the potential of (1) shifts to the second potential, the potential of the pixel electrodes on the entire display screen is made uniform.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) An active matrix type liquid crystal display device 1 according to a first embodiment of the present invention will be described below.
0 will be described with reference to FIGS. 1 to 3.

(1) Structure of Liquid Crystal Display Device 10 This liquid crystal display device 10 is provided with a liquid crystal panel 12 having an effective display area, for example, a color display pixel of UXGA specification having a diagonal size of 15 inches.

As shown in FIG. 1, the liquid crystal panel 12 includes (1600 × 3 (R, G, B)) signal lines 16 and 1200 scanning lines arranged orthogonal to the signal lines 16. 18 and a pixel electrode 2 arranged via a TFT 20 arranged in the vicinity of the intersection of each signal line 16 and scanning line 18.
2 is provided with the array substrate 14.

Further, it is arranged between the array substrate 14 and the counter electrode substrate, and a counter electrode substrate (not shown) provided with a color filter arranged above the facing surface of the array substrate 14 with a predetermined gap. And a liquid crystal (not shown) as a light modulation layer.

Each of the scanning lines 18 is a gate of the TFT 20, each of the signal lines 16 is a drain of the TFT 20, and each of the pixel electrodes 22 is a source of the TFT 20.
They are electrically connected to each other, so that the scan line 1
The image signal Vsig from the signal line 16 corresponding to the gate signal Vg supplied to 8 is written in the pixel electrode 22, and is displayed based on the potential difference between the pixel electrode 22 and the DC counter electrode Vcom.

As shown in FIG. 2, the pixel electrode 22 is superposed on the scanning line 18 at the preceding stage via an insulating film. This forms the auxiliary capacitance Cs. This auxiliary capacitance C
s has a capacity that is at least ½ of the liquid crystal capacity C _lc or more. Then, it is shown that this configuration is the above-mentioned Cs on-gate type.

The signal line 16 is connected to a source driver 24, and the source driver 24 D / A converts the digital image data signal DATA to generate an analog image signal Vs.
ig is supplied to the signal line 16.

The scanning line 18 is connected to the gate driver 28 and supplied with the gate signal Vg.

Source driver 24 and gate driver 28
Is provided with a liquid crystal controller 30.

From the liquid crystal controller 30, to the source driver 24, the horizontal clock signal XCLK, the horizontal start signal STH, and the above-mentioned image data signal DAT are sent.
A, the polarity inversion signal POL is supplied. Further, for the gate driver 28, the first vertical clock signal YCLK
1, the vertical start signal STV, the output inhibit signal OE, and the second vertical clock signal YCLK2 are supplied.

(2) Structure of Source Driver 24 The source driver 24 is composed of a circuit including a shift register, a latch circuit and a D / A converter. Then, based on the horizontal clock signal XCLK and the horizontal start signal STH input from the liquid crystal controller 30, each signal line 16 is output from the digital image data DATA.
The analog image signal Vsig is output to.

(3) Structure of Gate Driver 28 The gate driver 28 includes a shift register in which a plurality of flip-flops are cascaded, and a pixel electrode 22 in which an analog image signal Vsig is written for each output of the shift register for a predetermined period. A first logic part for setting a third potential for compensating for the potential fluctuation of the second logic part, a second period for setting a predetermined period of rising of each output of the first logic part, and a second period for holding the third potential It is composed of a circuit including a logic section and an output buffer. Then, the gate driver 28 sequentially outputs a gate signal Vg described later according to the vertical start signal STV, the first vertical clock signal YCLK1, the output inhibition signal OE, and the second vertical clock signal YCLK2.

(4) State of Writing in Pixel Electrode 22 FIG. 3 shows the image signal Vs of the pixel electrode 22 in this embodiment.
It is a waveform diagram showing a state of writing ig.

The written state will be described below with reference to the waveform diagram of FIG.

From the gate driver 28, the first potential of +20 V for turning on the TFT 20, the second potential of -6 V for turning off the TFT 20, and the pixel electrode 22.
Of the third potential of −11 V for compensating for the potential fluctuation of the output signal of the gate signal is output. In this case, the period H1 for holding the first potential (for example, 12.7 μsec) is
Generated in synchronization with the vertical clock signal YCLK1, the third potential holding period H2 (for example, 5 μsec) is
It is generated in synchronization with the second vertical clock signal YCLK2 and sequentially output from the scanning line 18 of the first stage to the scanning line 16 of the 1200th stage. Note that H3 (for example, 16.7 μsec), which is the inversion time of the image signal, is synchronized with the horizontal clock signal XCLK.

The flip-flop of the first logic section of the gate driver 28 sets the output from the flip-flop of the shift register to the third potential based on the output from the flip-flop of the next stage. For example, in the case where the TFT operates as an N channel, when the potential of the gate signal drops from the ON level to the second potential which is the OFF level, the charges written in the pixel electrode 22 are transferred to various capacitors. It is redistributed and the potential of the pixel electrode 22 decreases. Therefore, the third potential is set to, for example, −11 V so as to compensate for the decrease in the potential of the pixel electrode 22.

When the TFT 20 operates as a P channel, the voltage of the gate signal changes from ON level to O level.
When rising to the FF level, the electric charges written in the pixel electrode 22 are redistributed among various capacitors, and the potential of the pixel electrode 22 rises. In this case, the third potential is set to a voltage above the OFF level.

Then, in this case, the period H2 for holding the third potential is generated by the synchronization of the second vertical clock signal YCLK2 as described above.

Further, in FIG. 3, when the second potential of the gate signal Vg is changed to the first potential, the front portion of the gate signal V is precut, so that the gate signal Vg rises slowly by 4 μsec. . This is realized by the output inhibit signal OE, and is the pixel potential V that is the write voltage.
This is for surely starting p.

The holding period H1 of the first potential, which is the write voltage, is performed in synchronization with the first vertical clock signal YCLK1 as described above.

Here, the time at which the gate signal of the nth stage in FIG. 3 changes from the first potential to the second potential (hereinafter referred to as O
Pay attention to t1 (referred to as FF time).

Conventionally, the same time as the OFF time of the gate signal of the nth stage and the time when the third potential in the gate signal Vg of the (n-1) th stage changes to the second potential (hereinafter referred to as compensation rising time) t2. Met.

However, in this embodiment, the compensation rising time t2 of the gate signal Vg of the (n-1) th stage is delayed with respect to the OFF time t1 of the gate signal Vg of the nth stage.

As a result, O of the gate signal Vg of the nth stage
At FF time t1, the gate signal Vg of the (n-1) th stage
Since the potential of is still holding the third potential,
The displacement state in which the gate signal Vg of the nth stage falls from the first potential to the second potential is not dragged by the change of the potential of the gate signal Vg of the n−1th stage, It is possible to fall surely to the potential of. for that reason,
Even if the scanning line 18 has a time constant, the fall of the gate signal Vg from the first displacement to the second displacement on the power supply side, the center, and the end portion of the scanning line 18 in the display screen is almost the same, There is no flicker as in the past.

In this case, since there are two vertical clock signals, the first potential holding period H1 and the second potential holding period H2 can be generated at different timings, and the nth stage It is possible to delay the compensation rising time of the gate signal Vg of the (n-1) th stage with respect to the OFF time t1 of the gate signal Vg of.

Further, since the first potential holding period H1 which is the writing time is the same as the conventional first potential holding period, the writing time is not shortened and a display defect does not occur.

The reason why the flicker phenomenon does not occur in this embodiment will be described in detail with reference to FIG.

Depending on the time constant of the scanning line 18, the gate signal V
The falling state of g is different. At this time, the left side of the scanning line 18 is the power supply side and the right side is the termination side.

Therefore, as shown by the solid line in FIG. 5, the change of the gate signal V on the left side has a low time constant, so that the change is rapid.

However, as shown by the dotted line in FIG. 5, the gate signal Vg at the right end becomes rounded because the time constant of the scanning line 18 becomes large.

Therefore, the writing voltage on the scanning line 18 at the left end can be surely written in accordance with the rapidly changing gate signal Vg, but at the right end, the gate signal V
It will be affected by the rounding of g.

In the prior art, at the OFF time t1,
The change from the third potential of the scanning line 18 in the preceding stage to the change of the second potential is caused. In this case, the left scan line 1
8 and the right scanning line 18 are different from each other. Therefore, the write voltage V
The potential of p changes on both sides to cause a flicker phenomenon.

However, in the present embodiment, since the change in the potential of the gate signal Vg in the preceding stage changing from the third potential to the second potential is not dragged, the first potential of the gate signal Vg changes from the first potential. The change to the second potential will be completed completely until the end. The state that changes to the end does not change from the conventional state due to the influence of the time constant of the scanning line 18. However, in the present embodiment, since it is not dragged by the change of the gate signal Vg in the preceding stage, it is possible to surely lower the potential to the second potential. Therefore, the writing states of the pixel potential on the scanning line 18 on the left side and the pixel potential on the right side become equal, and the flicker phenomenon does not occur.

(Second Embodiment) In the first embodiment, the counter voltage applied to the counter electrode is DC, but the present invention can be realized also in the common inversion drive method in which an AC counter voltage is applied to the counter electrode. You can

Hereinafter, description will be given based on the waveform chart of FIG.

FIG. 4 is a waveform diagram showing the counter voltage Vcom in the common inversion driving method, which is divided into a positive polarity writing time and a negative polarity writing time.

In the case of positive polarity writing, the gate signal Vg changes from the first potential Vgh to the second potential Vg.
4 and then changes to Vg1 and Vg2 in accordance with the inversion period of the common voltage Vcom.

Conventionally, this inversion period was inverted in synchronization with the opposing voltage (state of the dotted line in FIG. 4), but in the second embodiment, the holding period of Vg4 is lengthened.

As a result, the OFF time when the scanning line 18 in the nth stage falls from Vgh to Vg4 and the compensation rising time t when the scanning line 18 in the n-1th stage rises from Vg3 to Vg2.
Since the same time as 2 does not occur, the flicker phenomenon can be prevented as in the first embodiment.

Similarly, in writing with negative polarity, Vg3
The holding time is longer than that of the conventional one, and the compensation rising time t2 that rises from Vg3 in the n−1th stage to Vg2 and the fall time from Vgh to Vg3 in the scanning line 18 in the nth stage.
The flicker phenomenon can be prevented by shifting the FF time t1.

(Modification 1) In the first embodiment, the third potential holding period H2 is set to a preset time. However, the present invention is not limited to this, and the second vertical clock signal YCLK2 is used.
Is manually adjusted to set the holding period H2 corresponding to each liquid crystal display device 10, and each liquid crystal display device 10 is held.
It may be possible to make adjustment so that flicker does not occur.

Also in the second embodiment, Vg is manually set in the same manner.
The period of 3 and Vg4 may be adjusted so that the flicker phenomenon can be prevented by adjusting according to each liquid crystal display device 10.

(Modification 2) In each of the above embodiments, the compensation rising time t2 of the scanning line 18 in the next stage is delayed with respect to the OFF time t1 of the gate signal.
Even if the compensation rise time t2 is earlier than the F time t1,
It is also possible to suppress the flicker phenomenon.

[0074]

As described above, according to the present invention, the potential holding period for compensating for the decrease in the pixel potential of the pixel electrode, which is the characteristic of the Cs on-gate type, is set from the ON state of the switching element in the scanning line of the next stage. It is possible to prevent the occurrence of a flicker phenomenon in the display screen by changing the potential to be turned off and shifting the time.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a liquid crystal display device showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a liquid crystal display device 10 in the present embodiment.

FIG. 3 is a waveform diagram when writing is performed on a pixel electrode.

FIG. 4 is a waveform diagram when writing is performed on a pixel electrode in the second embodiment.

FIG. 5 is a waveform diagram of a gate signal, where a solid line is a waveform diagram at the left end and a dotted line is a waveform diagram in a blunted state at the right end.

FIG. 6 is a waveform diagram when writing is performed on a conventional pixel electrode.

[Explanation of symbols]

10 Liquid crystal display device 12 LCD panel 14 Array substrate 16 signal lines 18 scan lines 20 TFT 22 Pixel electrode 24 Source Driver 28 Gate driver 30 LCD controller

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 622D F term (reference) 2H093 NC03 NC09 NC34 NC35 ND10 ND33 ND36 5C006 AA01 AA16 AA22 AC22 AC25 AF46 AF50 AF52 AF71 BB16 BC03 BC06 BC12 BF03 BF04 BF06 BF15 FA14 FA16 FA18 FA22 FA23 FA26 FA37 5C080 AA10 BB05 CC03 DD05 DD06 DD07 EE19 EE29 EE30 FF11 GG12 JJ02 JJ04 JJ06 KK01 KK43

Claims (6)

[Claims] 1. An array substrate comprising a plurality of signal lines and scanning lines arranged orthogonally to each other, and a pixel electrode arranged via a switching element in the vicinity of an intersection of the signal lines and the scanning lines. A counter substrate that constitutes a counter electrode with respect to the array substrate; a light modulation layer disposed between the array substrate and the counter substrate; and a signal line drive circuit that supplies an image signal to the signal line, A scanning line driving circuit that supplies a gate signal for writing the image signal to the pixel electrode to the scanning line by turning on the switching element, The pixel electrode at least so as to intersect with the scanning line, the gate signal causes a first potential for turning on the switching element, and the switching element turns off. And a second potential different from the first potential and the second potential for compensating for a decrease in the pixel potential of the pixel electrode written at the first potential. In the active-matrix-type flat panel display device, which is at least configured and has the pixel potential of the pixel electrode during the period of holding the pixel potential, the scan line driving circuit is configured to output the gate signal of the gate signal supplied to the scan line. The OFF time, which is the time when the potential changes from the second potential to the third potential,
An active matrix type characterized in that it is earlier or later than the compensation rising time which is the time when the third potential of the gate signal supplied to the scanning line in the preceding stage of the scanning line is changed to the second potential. Flat display device. 2. The active matrix flat panel display device according to claim 1, wherein a direct current counter potential is applied to the counter electrode, and the third potential is lower than the second potential. 3. The scanning line driving circuit sets a time period for holding the first potential of the gate signal to a first level.
2. The active matrix type flat panel display device according to claim 1, wherein the second potential signal is generated by the second timing signal different from the first timing signal, and the time for holding the third potential is generated by the second timing signal. 4. An alternating counter potential is applied to the counter electrode, the second potential is changed in two steps in accordance with the reversal of the counter potential, and the third potential is the second step of the two steps. 2. The active matrix type flat panel display device according to claim 1, wherein the value takes a value between the potentials. 5. The active matrix flat display device according to claim 1, wherein the light modulation layer is a liquid crystal layer. 6. The active matrix flat panel display device according to claim 1, wherein the switching element is a thin film transistor.