JPH0982851A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0982851A JPH0982851A JP7235609A JP23560995A JPH0982851A JP H0982851 A JPH0982851 A JP H0982851A JP 7235609 A JP7235609 A JP 7235609A JP 23560995 A JP23560995 A JP 23560995A JP H0982851 A JPH0982851 A JP H0982851A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- chip
- film
- semiconductor device
- polyimide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/01079—Gold [Au]
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特に、チップ表面のボンディングパッドへのワイヤーボ
ンディング作業時に、チップ表面に設けられているチッ
プ表面への外部からの機械的衝撃を緩衝するための硬化
樹脂膜にクラック及び破壊が生じることがないチップ表
面構造を備えた半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, during wire bonding work on the bonding pad on the chip surface, the chip surface is provided on the chip surface so that the cured resin film for cushioning external mechanical shocks to the chip surface does not crack or break. The present invention relates to a semiconductor device having a structure.
【０００２】[0002]
【従来の技術】近年、半導体部品は高集積化，高密度化
の傾向にあり、それに伴い半導体装置に搭載する半導体
チップは、微細化，大型化している。一方、半導体チッ
プのケースであるパッケージは安価な樹脂封止型のもの
が多く使用されている。しかしながら、半導体チップの
微細化，大型化にともなって、半導体チップは封止樹脂
からの応力を強く受けるようになり、例えば封止樹脂中
のシリカ充填剤によって半導体チップの表面保護膜（例
えばＳｉＯ2 膜，Ｓｉ3Ｎ4膜）にクラックが発生した
り、さらには配線の断線，特性変動を引き起こし、半導
体チップが不良になるという事故がしばしば報告される
ようになってきている。そこで多くの半導体メーカーで
はチップ表面に外部からの衝撃を緩衝する緩衝剤として
ポリイミド膜等の硬化樹脂膜を形成して，前記問題点を
解消する試みがなされている。ポリイミド膜を緩衝剤と
して用いてなる半導体チップが搭載された半導体装置の
一具体例を図７に示す。図７は半導体装置の要部断面を
拡大して示した図であり、図において、１３は半導体チ
ップ、１４，１５はボンディングパッド、１７はポリイ
ミド膜、１６，２３はポリイミド膜１７に形成された近
接してとなり合う開口、１８は金線、１９は金線の先端
に形成されたボンディングボール、２０はインナーリー
ド、２１はアウターリード、２２は封止樹脂、２４はポ
リイミド膜１７のクラック部分、２５はポリイミド膜１
７の界面剥離部分、２６はポリイミド膜１７の開口１
６，２３の間に位置する部分である。この半導体装置で
は、インナーリード２０に直接導通しているアウターリ
ード２１が半導体装置の外部にあることにより、半導体
チップ１３の内部からの電気信号及び外部基板（図示せ
ず）からの電気信号が入出力されるようになっている。2. Description of the Related Art In recent years, semiconductor parts have tended to be highly integrated and highly densified, and accordingly, semiconductor chips mounted on semiconductor devices have become finer and larger. On the other hand, as a package of a semiconductor chip, an inexpensive resin-sealed package is often used. However, with the miniaturization and size increase of the semiconductor chip, the semiconductor chip is strongly subjected to the stress from the sealing resin, and for example, the silica filler in the sealing resin causes a surface protective film (for example, SiO 2 ) of the semiconductor chip. It has been frequently reported that semiconductor chips become defective due to cracks in the film, Si 3 N 4 film), wire breakage, and characteristic fluctuations. Therefore, many semiconductor manufacturers have attempted to solve the above problems by forming a cured resin film such as a polyimide film on the surface of the chip as a buffering agent for buffering external shocks. FIG. 7 shows a specific example of a semiconductor device mounted with a semiconductor chip using a polyimide film as a buffer. FIG. 7 is an enlarged view showing a cross section of a main part of the semiconductor device. In the figure, 13 is a semiconductor chip, 14 and 15 are bonding pads, 17 is a polyimide film, and 16 and 23 are formed on a polyimide film 17. Adjacent openings are adjacent to each other, 18 is a gold wire, 19 is a bonding ball formed at the tip of the gold wire, 20 is an inner lead, 21 is an outer lead, 22 is a sealing resin, 24 is a crack portion of the polyimide film 17, 25 is a polyimide film 1
7 is the interface peeling portion, and 26 is the opening 1 of the polyimide film 17.
It is a part located between 6 and 23. In this semiconductor device, since the outer lead 21 that is directly connected to the inner lead 20 is outside the semiconductor device, an electric signal from the inside of the semiconductor chip 13 and an electric signal from an external substrate (not shown) are input. It is supposed to be output.
【０００３】かかる半導体装置の製造工程を簡単に説明
すると、所定の工程を終了した半導体チップ１３の表面
にポリイミド膜１７を形成し、このポリイミド膜１７
に、ボンディングパッド１４とボンディングボール１９
を接続するために開口２３を形成する。ワイヤーボンダ
ーによって金線１８の先端を電気スパーク等によって溶
融させて形成したボンディングボール１９を、ボンディ
ングパッド１４に熱、超音波、荷重等を用いて接着す
る。そして、ボンディングパッド１４と金線１８の一端
を接続し、金線１８の他端をインナーリード２０に接続
し、しかる後、このようにしてワイヤーボンディングが
なされた半導体チップ１３を封止樹脂２２にて封止する
と、半導体装置が完成する。The process of manufacturing such a semiconductor device will be briefly described. A polyimide film 17 is formed on the surface of the semiconductor chip 13 which has undergone a predetermined process, and the polyimide film 17 is formed.
In addition, the bonding pad 14 and the bonding ball 19
An opening 23 is formed to connect the two. A bonding ball 19 formed by melting the tip of the gold wire 18 by an electric spark or the like with a wire bonder is bonded to the bonding pad 14 by using heat, ultrasonic waves, a load, or the like. Then, the bonding pad 14 and one end of the gold wire 18 are connected, the other end of the gold wire 18 is connected to the inner lead 20, and then the semiconductor chip 13 thus wire-bonded is applied to the sealing resin 22. Then, the semiconductor device is completed.
【０００４】[0004]
【発明が解決しようとする課題】前記半導体装置の製造
工程におけるワイヤーボンディング工程時、ワイヤーボ
ンディング設備の精度が十分でない場合や、設備異常，
オペレーターの操作及び設定ミス等によってボンディン
グボール１９の接着位置がボンディングパッド１４の中
心から著しくずれる場合がある。この場合、ポリイミド
膜１７の開口２３の端部とボンディングボール１９が接
触して、かかる端部にクラック２４が発生し、半導体チ
ップ１３とポリイミド膜１７の間に界面剥離（２５）が
発生する。この界面剥離（２５）が発生すると、当該剥
離部分２５に水分が侵入し、半導体チップ１３が耐湿性
不良を起こし、半導体装置の信頼性が著しく低下してし
まう。During the wire bonding process in the manufacturing process of the semiconductor device, if the accuracy of the wire bonding equipment is not sufficient, or the equipment malfunctions,
The bonding position of the bonding ball 19 may be significantly deviated from the center of the bonding pad 14 due to an operator's operation, setting error, or the like. In this case, the edge of the opening 23 of the polyimide film 17 comes into contact with the bonding ball 19, a crack 24 is generated at the edge, and an interface peeling (25) occurs between the semiconductor chip 13 and the polyimide film 17. When the interface peeling (25) occurs, moisture enters the peeled portion 25, the moisture resistance of the semiconductor chip 13 is deteriorated, and the reliability of the semiconductor device is significantly lowered.
【０００５】また、半導体チップ１３に前記ボンディン
グパッド１４とは異なるボンディングパッド１５が前記
ボンディングパッド１４に近接して設けられている場
合、近接する二つのボンディングパッド１４，１５を隔
てるポリイミド膜１７は、その膜厚に対する膜幅が狭い
ために非常に強度が弱くなる。このため、かかるポリイ
ミド膜１７は、前記したようなワイヤーボンディング工
程時のボンディングボール１９との接触によって破壊し
たり、また、半導体装置の製造工程および半導体装置の
信頼性試験時において破壊することがあり、これによ
り、半導体チップ１３が前記の耐湿性不良を起こした
り、また、ボンディングパッド１４とボンディングパッ
ド１５間の電気的絶縁が保たれなくなってしまうといっ
た不具合を生じる。また、このような半導体チップ１３
に２つのボンディングパッド１４，１５が近接して設け
られている場合、かかるボンディングパッド１４，１５
を表出させるための開口１６，２３をポリイミド膜１７
に形成する工程において、開口１６，２３間に残される
ポリイミド膜２６の膜厚に対する膜幅が著しく小さくな
るため、ポリイミド膜１７のエッチング作業が困難にな
る。When a bonding pad 15 different from the bonding pad 14 is provided on the semiconductor chip 13 in the vicinity of the bonding pad 14, the polyimide film 17 separating the two adjacent bonding pads 14, 15 from each other is Since the film width with respect to the film thickness is narrow, the strength becomes extremely weak. Therefore, the polyimide film 17 may be broken due to contact with the bonding ball 19 in the wire bonding process as described above, or may be broken in the manufacturing process of the semiconductor device and the reliability test of the semiconductor device. As a result, the semiconductor chip 13 may have the above-mentioned poor moisture resistance, and the electrical insulation between the bonding pads 14 and 15 may not be maintained. In addition, such a semiconductor chip 13
When the two bonding pads 14 and 15 are provided close to each other, the bonding pads 14 and 15 are
Openings 16 and 23 for exposing the polyimide film 17
In the step of forming, the film width with respect to the film thickness of the polyimide film 26 left between the openings 16 and 23 becomes extremely small, so that the etching operation of the polyimide film 17 becomes difficult.
【０００６】本発明は上記のような課題に鑑みてなされ
たものであり、ワイヤーボンディング時にチップ表面に
設けられている外部からの機械的衝撃を緩衝するための
硬化樹脂膜にクラック及び破壊が生じることがない半導
体チップを提供することを目的とする。The present invention has been made in view of the above problems, and cracks and breaks occur in a cured resin film provided on the surface of a chip during wire bonding for buffering a mechanical shock from the outside. It is an object of the present invention to provide a semiconductor chip that does not exist.
【０００７】[0007]
【課題を解決するための手段】本発明にかかる半導体装
置は、チップ表面が外部からの機械的衝撃を緩衝するた
めの硬化樹脂膜で被覆され、当該硬化樹脂膜に前記チッ
プ表面に形成されているワイヤーボンディング用のボン
ディングパッドを表出させるための開口が形成されてな
る半導体装置において、前記硬化樹脂膜の前記開口の周
辺に位置する領域がその他の領域よりも小さい厚みに形
成され、当該厚みが前記ボンディングパッドにボンディ
ングされるべきワイヤーボンディングボールの厚みの半
分以下になっていることを特徴とするものである。In a semiconductor device according to the present invention, a chip surface is coated with a cured resin film for buffering a mechanical shock from the outside, and the cured resin film is formed on the chip surface. In a semiconductor device in which an opening for exposing a bonding pad for wire bonding is formed, a region of the cured resin film located around the opening is formed to have a smaller thickness than other regions, Is less than half the thickness of the wire bonding ball to be bonded to the bonding pad.
【０００８】前記構成においては、前記チップ表面を被
覆する硬化樹脂膜に、前記チップ表面に形成されている
２個以上の前記ボンディングパッドをそれぞれ表出させ
るための２個以上の開口が形成されており、前記硬化樹
脂膜の前記２個以上の開口のうちの互いに隣接する２つ
の開口間に位置している部分が、前記小さい厚みに形成
されているのが好ましい。In the above structure, the cured resin film covering the surface of the chip is formed with two or more openings for exposing the two or more bonding pads formed on the surface of the chip. It is preferable that a portion of the cured resin film, which is located between two adjacent openings of the two or more openings, is formed to have the small thickness.
【０００９】また前記構成においては、前記チップ表面
を被覆する硬化樹脂膜に、前記チップ表面に形成されて
いる複数の前記ボンディングパッドをそれぞれ表出させ
るための複数の開口が形成されており、前記硬化樹脂膜
の前記複数の開口のそれぞれの周辺領域を含む一繋がり
の領域が、前記小さい厚みに形成されているのが好まし
い。Further, in the above structure, the cured resin film covering the surface of the chip is formed with a plurality of openings for exposing the plurality of bonding pads formed on the surface of the chip, respectively. It is preferable that a continuous region including a peripheral region of each of the plurality of openings of the cured resin film is formed to have the small thickness.
【００１０】また前記構成においては、前記硬化樹脂膜
がポリイミド膜であるのが好ましい。In the above structure, it is preferable that the cured resin film is a polyimide film.
【００１１】[0011]
【発明の実施の形態】本発明の半導体装置においては、
チップ表面が外部からの機械的衝撃を緩衝するための硬
化樹脂膜で被覆され、当該硬化樹脂膜に前記チップ表面
に形成されているワイヤーボンディング用のボンディン
グパッドを表出させるための開口が形成されてなる半導
体装置において、前記硬化樹脂膜の前記開口の周辺に位
置する領域がその他の領域よりも小さい厚みに形成さ
れ、当該厚みが前記ボンディングパッドにボンディング
されるべきワイヤーボンディングボールの厚みの半分以
下になっていることにより、ワイヤーボンディング時に
ワイヤーボンディングボールのボンディング位置がずれ
ても、前記硬化樹脂膜の前記ボンディングパッドを表出
させるための開口の周辺領域が前記ワイヤーボンディン
グボールの厚みの半分以下の厚みになっているので、当
該周辺領域にワイヤーボンディングボールが接触するこ
とを防止することができ、硬化樹脂膜にクラックや破壊
が生じるのを防止することができる。また、かかる硬化
樹脂膜にクラックや破壊が生じるのを防止することがで
きるので、ワイヤーボンディング作業におけるワイヤー
ボンディング位置のマージンを拡大でき、ワイヤーボン
ディング作業の高速化を図ることができる。BEST MODE FOR CARRYING OUT THE INVENTION In the semiconductor device of the present invention,
The chip surface is covered with a cured resin film for buffering mechanical shocks from the outside, and an opening for exposing a bonding pad for wire bonding formed on the chip surface is formed in the cured resin film. In the semiconductor device, the region of the cured resin film located around the opening is formed to have a smaller thickness than other regions, and the thickness is less than half the thickness of the wire bonding ball to be bonded to the bonding pad. By this, even if the bonding position of the wire bonding ball is displaced during wire bonding, the peripheral area of the opening for exposing the bonding pad of the cured resin film is less than half the thickness of the wire bonding ball. Since it is thick, the wire can be It is possible to prevent the bonding ball is in contact, it is possible to prevent cracks and breakage may occur in the cured resin film. Further, since it is possible to prevent the cured resin film from being cracked or broken, it is possible to increase the margin of the wire bonding position in the wire bonding work, and to speed up the wire bonding work.
【００１２】また本発明においては、前記構成の好まし
い例として、前記チップ表面を被覆する硬化樹脂膜に、
前記チップ表面に形成されている２個以上の前記ボンデ
ィングパッドをそれぞれ表出させるための２個以上の開
口が形成されており、前記硬化樹脂膜の前記２個以上の
開口のうちの互いに隣接する２つの開口間に位置してい
る部分が、前記小さい厚みに形成されていると、硬化樹
脂膜の隣接する２つの開口の間の領域は通常その幅が極
めて小さいものとなるが、前記薄い厚みに形成している
ことにより、かかる領域の膜厚に対する膜幅の比（膜幅
／膜厚）を大きくでき、かかる領域の機械的強度が向上
する。従って、硬化樹脂膜の隣接する２つの開口の間の
領域がワイヤーボンディング工程時のボンディングボー
ルとの接触によって破壊したり、また、半導体装置の製
造工程および半導体装置の信頼性試験時において破壊し
たりすることを防止できる。Further, in the present invention, as a preferred example of the above-mentioned constitution, a cured resin film for coating the surface of the chip,
Two or more openings are formed to expose the two or more bonding pads formed on the chip surface, and the two or more openings of the cured resin film are adjacent to each other. When the portion located between the two openings is formed to have the small thickness, the area between the two adjacent openings of the cured resin film usually has a very small width, but the thin thickness is small. By forming the film in such a manner, the ratio of the film width to the film thickness in such a region (film width / film thickness) can be increased, and the mechanical strength of such region is improved. Therefore, a region between two adjacent openings of the cured resin film may be destroyed by contact with a bonding ball during a wire bonding process, or may be destroyed during a semiconductor device manufacturing process and a semiconductor device reliability test. Can be prevented.
【００１３】また本発明においては、前記構成の好まし
い例として、前記チップ表面を被覆する硬化樹脂膜に、
前記チップ表面に形成されている複数の前記ボンディン
グパッドをそれぞれ表出させるための複数の開口が形成
されており、前記硬化樹脂膜の前記複数の開口のそれぞ
れの周辺領域を含む一繋がりの領域が、前記小さい厚み
に形成されていると、前記複数の開口のうち互いに隣接
する２つの開口の間にある硬化樹脂膜の膜厚に対する膜
幅の比（膜幅／膜厚）を大きくでき、これの機械的強度
を向上させることができるとともに、チップ表面の微細
な面積の領域において硬化樹脂膜をこれに段差（膜厚
差）が生じるよう加工する必要がなくなるので、加工精
度が向上し、装置の信頼性を高めることができる。In the present invention, as a preferred example of the above structure, a cured resin film coating the surface of the chip is
A plurality of openings for respectively exposing the plurality of bonding pads formed on the chip surface are formed, and a continuous area including each peripheral area of the plurality of openings of the cured resin film is formed. When the thickness is small, the ratio of the film width to the film thickness of the cured resin film (film width / film thickness) between two adjacent openings of the plurality of openings can be increased. It is possible to improve the mechanical strength of the device, and it is not necessary to process the cured resin film in a region of a small area on the chip surface so that a step (film thickness difference) is generated in the region. The reliability of can be increased.
【００１４】また本発明においては、前記構成の好まし
い例として、前記硬化樹脂膜がポリイミド膜であると、
前記硬化樹脂膜が熱的安定性及び耐機械的強度の点で優
れたものとなり、装置の信頼性がより高いものとなる。Further, in the present invention, as a preferred example of the above constitution, when the cured resin film is a polyimide film,
The cured resin film becomes excellent in terms of thermal stability and mechanical strength, and the reliability of the device becomes higher.
【００１５】[0015]
（実施例１）図１は本発明の実施例１による半導体装置
の要部構成を拡大して示した断面図であり、図におい
て、１は半導体チップ、２はポリイミド膜、２ａはポリ
イミド膜２より厚みが小さいポリイミド膜、３，１１は
ボンディングパッド、４はボンディングボール、５，１
２はポリイミド膜２（２ａ）に形成された，近接して隣
り合う開口、７は金線、８はインナーリード、９は封止
樹脂、１０はアウターリードである。(Embodiment 1) FIG. 1 is an enlarged cross-sectional view of a main part structure of a semiconductor device according to Embodiment 1 of the present invention. In the drawing, 1 is a semiconductor chip, 2 is a polyimide film, 2a is a polyimide film 2 A thinner polyimide film, 3, 11 are bonding pads, 4 are bonding balls, 5, 1
Reference numeral 2 is an opening formed in the polyimide film 2 (2a) and adjacent to each other, 7 is a gold wire, 8 is an inner lead, 9 is a sealing resin, and 10 is an outer lead.
【００１６】以下、各構成を更に詳しく構成を説明す
る。所要の製造プロセスを終了し、その表面の所定領域
にボンディングパッド３，１１が形成された半導体チッ
プ１の当該表面にポリイミド膜２が形成されている。こ
のポリイミド膜２の前記ボンディングパッド３，１１を
覆う領域に、ボンディングパッド３，１１を表出させる
ための開口５，１２がフォトリソグラフィー技術，及び
ケミカルエッチング技術を用いて形成され、さらに、開
口５の周辺領域に厚みの小さいポリイミド膜（部分）２
ａがフォトリソグラフィー技術，及びケミカルエッチン
グ技術を用いて形成されている。これら開口５，１２の
形成及び厚みの小さいポリイミド膜（部分）２ａの形成
の順序を逆にしてもよい。ワイヤーボンダーによって金
線７の一端を電気スパーク等によって溶融させて形成し
たボンディングボール４がボンディングパッド３に熱、
超音波、荷重等を用いて接着されている。金線７の他端
はインナーリード８へ接続されている。そして、封止工
程でこれら各構成要素が封止樹脂９にて一体的に封止さ
れている。インナーリード８と直接導通しているアウタ
ーリード１０は半導体装置の外部にあり、金線７，イン
ナーリード８，アウターリード１０によって半導体チッ
プ１の内部からの電気信号、図示しない外部基板からの
電気信号が入出力される。The respective configurations will be described in more detail below. After the required manufacturing process is completed, the polyimide film 2 is formed on the surface of the semiconductor chip 1 on which the bonding pads 3 and 11 are formed in the predetermined regions on the surface. Openings 5 and 12 for exposing the bonding pads 3 and 11 are formed in a region of the polyimide film 2 that covers the bonding pads 3 and 11 by using a photolithography technique and a chemical etching technique. Polyimide film (part) with a small thickness in the peripheral area 2
a is formed by using the photolithography technique and the chemical etching technique. The order of forming the openings 5 and 12 and forming the thin polyimide film (portion) 2a may be reversed. The bonding ball 4 formed by melting one end of the gold wire 7 by an electric spark or the like by the wire bonder heats the bonding pad 3,
Bonded using ultrasonic waves, load, etc. The other end of the gold wire 7 is connected to the inner lead 8. Then, in the sealing step, these respective constituent elements are integrally sealed with the sealing resin 9. The outer lead 10 directly connected to the inner lead 8 is outside the semiconductor device, and the gold wire 7, the inner lead 8 and the outer lead 10 cause an electric signal from the inside of the semiconductor chip 1 and an electric signal from an external substrate (not shown). Is input and output.
【００１７】前記構成において、ポリイミド膜２は封止
樹脂９中に含まれるシリカ等の充填材（フィラー）の形
状，粒径等に応じて、この充填材からの機械的衝撃を緩
衝して，半導体チップ１の特性劣化を防止するに必要な
厚みに形成される。厚みの小さいポリイミド膜（部分）
２ａの膜厚は、ボンディングボール４の厚さの半分以下
で極力薄い厚みに形成する。上限値をボンディングボー
ル４の厚さの半分とするのは、ボンディングボールをボ
ンディングした場合、前記図７から分かるように、ボン
ディングボール（１９）は通常その厚さの約半分の部分
（下側部分）がポリイミド膜（１７）の開口端部に接近
するためである。従って、たとえば、ボンディングボー
ル４の厚みが２０μｍであれば、厚みの小さいポリイミ
ド膜（部分）２ａの膜厚は１０μｍ以下にする。また、
下限値は現状のフォトリソグラフィー技術，及びケミカ
ルエッチング技術を駆使して形成することのできる最小
膜厚である。厚みの小さいポリイミド膜（部分）２ａの
膜厚を極力薄くすることにより、ポリイミド膜２ａ
（２）へのボンディングボール４の接触が防止され、ポ
リイミド膜２ａ（２）にクラックや破壊が生じるのを防
止できる。特に、厚みの小さいポリイミド膜（部分）２
ａの膜厚が薄ければ薄い程、ワイヤーボンディング工程
においてボンディングボール４のボンディング位置が理
想的なボンディング位置から大きくずれても、ボンディ
ングボール４とポリイミド膜２ａとの接触を回避するこ
とができ、ワイヤーボンディング工程におけるボンディ
ング位置の作業マージンを拡大することができる。ま
た、図１に示すように、近接して隣り合う開口５，１２
間のポリイミド膜を厚みの小さいポリイミド膜（部分）
２ａにすることにより、膜の機械的強度を向上させるこ
とができる。すなわち、近接して隣り合う開口５，１２
間のポリイミド膜は自ずと微細な幅を有するものになっ
てしまうが、これを厚みの小さいポリイミド膜（部分）
２ａにしてその厚みを極力小さくすることにより、膜厚
に対する膜幅の比（膜幅／膜厚）を大きくでき、膜の機
械強度を向上させることができる。In the above structure, the polyimide film 2 buffers the mechanical impact from the filler according to the shape and particle size of the filler (filler) such as silica contained in the sealing resin 9, The semiconductor chip 1 is formed to have a thickness necessary to prevent characteristic deterioration of the semiconductor chip 1. Thin polyimide film (part)
The film thickness of 2a is less than half the thickness of the bonding ball 4 and is formed as thin as possible. The upper limit is set to half the thickness of the bonding ball 4, when the bonding ball is bonded, as can be seen from FIG. 7, the bonding ball (19) is usually about half the thickness (lower part). ) Approaches the open end of the polyimide film (17). Therefore, for example, when the thickness of the bonding ball 4 is 20 μm, the thickness of the thin polyimide film (portion) 2a is set to 10 μm or less. Also,
The lower limit is the minimum film thickness that can be formed by making full use of the current photolithography technology and chemical etching technology. By reducing the film thickness of the thin polyimide film (portion) 2a as much as possible, the polyimide film 2a
It is possible to prevent the bonding ball 4 from coming into contact with (2) and prevent the polyimide film 2a (2) from cracking or breaking. In particular, a thin polyimide film (part) 2
As the film thickness of a is thinner, even if the bonding position of the bonding ball 4 is largely deviated from the ideal bonding position in the wire bonding process, it is possible to avoid contact between the bonding ball 4 and the polyimide film 2a. The work margin at the bonding position in the wire bonding process can be expanded. In addition, as shown in FIG.
Polyimide film between thin polyimide film (part)
By setting it to 2a, the mechanical strength of the film can be improved. That is, the openings 5 and 12 that are adjacent and adjacent to each other
The polyimide film between them will naturally have a fine width, but this is due to the small thickness of the polyimide film (part).
By making the thickness 2a to be as small as possible, the ratio of the film width to the film thickness (film width / film thickness) can be increased, and the mechanical strength of the film can be improved.
【００１８】（実施例２）図２は本発明の実施例２によ
る半導体装置における半導体チップの主要部の構成を示
した平面図であり、図において、図１と同一符号は同一
または相当する部分を示している。本実施例の半導体装
置の全体構成は前記実施例１の半導体装置のそれと基本
的に同じである。前記実施例１の半導体装置では、ボン
ディングパッド３，１１と開口５，１２が互いの端部が
同一位置となるよう形成されているが、本実施例では、
この図２に示すように、ポリイミド膜２より厚みが小さ
いポリイミド膜（部分）２ａがボンディングパッド３の
周縁部を覆うように開口５が形成されている。かかる構
成にしても、前記実施例１と同様の効果を得ることがで
きる。(Embodiment 2) FIG. 2 is a plan view showing a structure of a main part of a semiconductor chip in a semiconductor device according to a second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 are the same or corresponding portions. Is shown. The overall structure of the semiconductor device of this embodiment is basically the same as that of the semiconductor device of the first embodiment. In the semiconductor device of the first embodiment, the bonding pads 3 and 11 and the openings 5 and 12 are formed so that their ends are at the same position, but in the present embodiment,
As shown in FIG. 2, the opening 5 is formed so that the polyimide film (portion) 2 a having a smaller thickness than the polyimide film 2 covers the peripheral portion of the bonding pad 3. Even with this configuration, the same effect as that of the first embodiment can be obtained.
【００１９】（実施例３）図３は本発明の実施例３によ
る半導体装置における半導体チップの主要部の構成を示
した断面図であり、図において、図１と同一符号は同一
または相当する部分を示し、２ｂはテーパー形状の断面
形状を有するポリイミド膜２より厚みが小さいポリイミ
ド膜である。本実施例の半導体装置の全体構成は前記実
施例１の半導体装置のそれと基本的に同じである。前記
実施例１では開口（ボンディングパッド３）の周辺領域
のポリイミド膜を一様にその厚みが小さいポリイミド膜
２ａにしたが、本実施例では開口（ボンディングパッド
３）の周辺領域のポリイミド膜をボンディングパッド３
の端部に向かってその厚みが徐々の減少するテーパー形
状の断面形状を有するポリイミド膜２ｂにしたものであ
る。かかる本実施例の構成にしても、前記実施例１と同
様の効果を得ることができる。(Embodiment 3) FIG. 3 is a sectional view showing a structure of a main portion of a semiconductor chip in a semiconductor device according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in FIG. 1 are the same or corresponding portions. 2b is a polyimide film having a smaller thickness than the polyimide film 2 having a tapered cross-sectional shape. The overall structure of the semiconductor device of this embodiment is basically the same as that of the semiconductor device of the first embodiment. In the first embodiment, the polyimide film in the peripheral region of the opening (bonding pad 3) is uniformly formed as the polyimide film 2a having a small thickness, but in the present embodiment, the polyimide film in the peripheral region of the opening (bonding pad 3) is bonded. Pad 3
The polyimide film 2b has a tapered cross-sectional shape whose thickness gradually decreases toward the end. Even with the configuration of this embodiment, the same effect as that of the first embodiment can be obtained.
【００２０】（実施例４）図４は本発明の実施例４によ
る半導体装置における半導体チップの主要部の構成を示
した平面図であり、図において、図１と同一符号は同一
または相当する部分を示し、２ｃはポリイミド膜２より
厚みが小さいポリイミド膜である。本実施例の半導体装
置の全体構成は前記実施例１の半導体装置のそれと基本
的に同じである。前記実施例１，２の半導体チップで
は、厚みの小さいポリイミド膜２ａをその外周の形状が
四角形となるように形成したが、本実施例では、この図
４に示すように、厚みの小さいポリイミド膜２ｃをその
外周の形状が楕円になるように形成している。かかる本
実施例の構成にしても、前記実施例１と同様の効果を得
ることができる。即ち、本発明において厚みの小さいポ
リイミド膜の外周形状は任意に形状でよい。尚、厚みの
小さいポリイミド膜２ａのチップ表面における形成範囲
は、ワイヤボンディング作業時にボンディングボール４
がボンディングパッド３の中心からずれる可能性がある
範囲に形成する。このボンディングボール４のずれる可
能性がある範囲は、ボンディングボール４の直径の大き
さ程度で十分である。なぜなら、かかる範囲以上にボン
ディングボール４のボンディング位置がずれると、ボン
ディングパッド３とボンディングボール４の接着面が極
端に減少し、本来のワイヤーボンディングの目的を果た
せなくなるからである。(Embodiment 4) FIG. 4 is a plan view showing the structure of the main part of a semiconductor chip in a semiconductor device according to Embodiment 4 of the present invention. In the figure, the same reference numerals as those in FIG. 2c is a polyimide film having a smaller thickness than the polyimide film 2. The overall structure of the semiconductor device of this embodiment is basically the same as that of the semiconductor device of the first embodiment. In the semiconductor chips of Examples 1 and 2, the polyimide film 2a having a small thickness was formed so that the outer peripheral shape was a quadrangle, but in the present example, as shown in FIG. 4, the polyimide film having a small thickness was formed. 2c is formed so that the outer peripheral shape thereof is elliptical. Even with the configuration of this embodiment, the same effect as that of the first embodiment can be obtained. That is, in the present invention, the outer peripheral shape of the thin polyimide film may be any shape. The area where the thin polyimide film 2a is formed on the chip surface is limited to the bonding ball 4 during the wire bonding operation.
Are formed in a range in which there is a possibility that they will deviate from the center of the bonding pad 3. The range in which the bonding balls 4 may be displaced is sufficient if the bonding balls 4 are about the diameter of the bonding balls 4. This is because if the bonding position of the bonding ball 4 deviates beyond this range, the bonding surface between the bonding pad 3 and the bonding ball 4 extremely decreases, and the original purpose of wire bonding cannot be achieved.
【００２１】（実施例５）図５は本発明の実施例５によ
る半導体装置における半導体チップの主要部の構成を示
した平面図であり、図において、図１と同一符号は同一
または相当する部分を示し、２ｄはポリイミド膜２より
厚みが小さいポリイミド膜である。本実施例の半導体装
置の全体構成は前記実施例１の半導体装置のそれと基本
的に同じである。本実施例の半導体チップはチップ表面
の中央に複数のボンディングパッド３が互いに近接して
線状に並ぶよう形成され、これら複数のボンディングパ
ッド３の各々の表面に開口５を配して，チップ表面の前
記複数のボンディングパッド３の各々の周辺領域を含む
一繋りの領域に厚みが小さいポリイミド膜２ｄを形成し
たものである。(Embodiment 5) FIG. 5 is a plan view showing a structure of a main portion of a semiconductor chip in a semiconductor device according to a fifth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 are the same or corresponding portions. 2d is a polyimide film having a smaller thickness than the polyimide film 2. The overall structure of the semiconductor device of this embodiment is basically the same as that of the semiconductor device of the first embodiment. In the semiconductor chip of the present embodiment, a plurality of bonding pads 3 are formed in the center of the chip surface so as to be arranged in a line in close proximity to each other, and an opening 5 is provided on each surface of the plurality of bonding pads 3 to form a chip surface. The polyimide film 2d having a small thickness is formed in a continuous region including the peripheral region of each of the plurality of bonding pads 3.
【００２２】（実施例６）図６は本発明の実施例６によ
る半導体装置における半導体チップの主要部の構成を示
した平面図であり、図において、図１と同一符号は同一
または相当する部分を示し、２ｅはポリイミド膜２より
厚みが小さいポリイミド膜である。本実施例の半導体装
置の全体構成は前記実施例１の半導体装置のそれと基本
的に同じである。本実施例の半導体チップはチップ表面
の周囲及び中央に複数のボンディングパッド３が所定間
隔を空けて線状に並ぶよう形成され、これら複数のボン
ディングパッド３の各々の表面に開口５を配して，チッ
プ表面の前記複数のボンディングパッド３の各々の周辺
領域を含む一繋りの領域に厚みが小さいポリイミド膜２
ｅを形成したものである。(Embodiment 6) FIG. 6 is a plan view showing the structure of a main portion of a semiconductor chip in a semiconductor device according to Embodiment 6 of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding portions. 2e is a polyimide film having a smaller thickness than the polyimide film 2. The overall structure of the semiconductor device of this embodiment is basically the same as that of the semiconductor device of the first embodiment. In the semiconductor chip of the present embodiment, a plurality of bonding pads 3 are formed around the center and the center of the surface of the chip so as to be linearly arranged at predetermined intervals, and an opening 5 is formed on each surface of the plurality of bonding pads 3. , A polyimide film 2 having a small thickness in a continuous region including the peripheral region of each of the plurality of bonding pads 3 on the chip surface
e.
【００２３】かかる実施例５，６の半導体装置において
も、前記実施例１と同様の効果を得ることができる。特
に、実施例６の半導体装置では、チップ表面における所
定間隔を空けて線状に並ぶよう形成された複数のボンデ
ィングパッド３の周辺領域を含む一繋りの領域に、厚み
が小さいポリイミド膜２ｅを形成しているので、チップ
表面の微細（面積の）領域においてポリイミド膜をこれ
に段差（膜厚差）が生じるよう加工する必要がなくな
る。従って、高い加工精度でポリイミド膜のエッチング
加工を行うことができ、装置の信頼性を高めることがで
きる。Also in the semiconductor devices of the fifth and sixth embodiments, the same effect as that of the first embodiment can be obtained. In particular, in the semiconductor device of Example 6, the polyimide film 2e having a small thickness is formed in the continuous region including the peripheral regions of the plurality of bonding pads 3 formed so as to be linearly arranged at a predetermined distance on the chip surface. Since it is formed, it is not necessary to process the polyimide film in the fine (area) area of the chip surface so that a step (thickness difference) is generated therein. Therefore, the polyimide film can be etched with high processing accuracy, and the reliability of the device can be improved.
【００２４】尚、前記実施例では、チップ表面のポリイ
ミド膜２を形成した後にフォトリソグラフィー技術とケ
ミカルエッチング技術を用いて、厚みの小さいポリイミ
ド膜２ａ〜２ｅを形成するようにしたが、本発明におい
ては、先に厚みの小さいポリイミド膜を形成した後に、
厚みの大きいポリイミド膜を形成して段差を設けるよう
にしてもよい。In the embodiment, the polyimide film 2 on the surface of the chip is formed, and then the thin polyimide films 2a to 2e are formed by using the photolithography technique and the chemical etching technique. After forming a thin polyimide film first,
A step may be provided by forming a thick polyimide film.
【００２５】また、前記実施例では、半導体チップのチ
ップ表面への外部からの機械的衝撃を緩衝するための表
面保護膜としてポリイミド膜を用いたものについて説明
したが、かかる表面保護膜として、ポリイミドとポリイ
ミドとは異なる他の樹脂成分からなるポリイミド系樹
脂、エポキシ系樹脂、フェノール系樹脂等のそれ自体公
知の熱硬化性樹脂や，紫外線等の光によって硬化するそ
れ自体公知の光硬化性樹脂を用いた場合にも本発明を適
用できることは言うまでもない。Further, in the above-mentioned embodiment, the case where the polyimide film is used as the surface protective film for buffering the external mechanical shock to the chip surface of the semiconductor chip has been described. A thermosetting resin known per se such as a polyimide resin, an epoxy resin, a phenolic resin or the like composed of another resin component different from polyimide and a photocurable resin known per se which is cured by light such as ultraviolet rays. It goes without saying that the present invention can be applied even when used.
【００２６】[0026]
【発明の効果】以上のように、本発明にかかる半導体装
置によれば、チップ表面が外部からの機械的衝撃を緩衝
するための硬化樹脂膜で被覆され、当該硬化樹脂膜に前
記チップ表面に形成されているワイヤーボンディング用
のボンディングパッドを表出させるための開口が形成さ
れてなる半導体装置において、前記硬化樹脂膜の前記開
口の周辺に位置する領域がその他の領域よりも小さい厚
みに形成され、当該厚みが前記ボンディングパッドにボ
ンディングされるべきワイヤーボンディングボールの厚
みの半分以下になっているものとしたので、ワイヤーボ
ンディング時にワイヤーボンディングボールのボンディ
ング位置がずれても、前記硬化樹脂膜の前記ボンディン
グパッドを表出させるための開口の周辺領域にワイヤー
ボンディングボールが接触することを防止することがで
きる。従って、ワイヤーボンディング時に硬化樹脂膜に
クラックや破壊が生じるのを防止することができ、しか
も、ワイヤーボンディング位置のマージンを拡大するこ
とができるので、高信頼性の半導体装置を製造歩留りを
製造することができる。As described above, according to the semiconductor device of the present invention, the chip surface is covered with the cured resin film for buffering the mechanical shock from the outside, and the cured resin film is applied to the chip surface. In a semiconductor device in which an opening for exposing a formed bonding pad for wire bonding is formed, a region of the cured resin film located around the opening is formed to have a smaller thickness than other regions. Since the thickness is less than half the thickness of the wire bonding ball to be bonded to the bonding pad, even if the bonding position of the wire bonding ball is displaced during wire bonding, the bonding of the cured resin film is performed. A wire bonding bow is provided in the area around the opening for exposing the pad. There can be prevented from contacting. Therefore, it is possible to prevent the cured resin film from being cracked or broken during wire bonding, and it is possible to expand the margin of the wire bonding position. Therefore, it is possible to manufacture a highly reliable semiconductor device at a high yield. You can
【図１】本発明の実施例１による半導体装置の要部構成
を拡大して示した断面図である。FIG. 1 is an enlarged sectional view showing a configuration of a main part of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の実施例２による半導体装置における半
導体チップの主要部の構成を示した平面図である。FIG. 2 is a plan view showing a configuration of a main part of a semiconductor chip in a semiconductor device according to a second embodiment of the present invention.
【図３】本発明の実施例３による半導体装置における半
導体チップの主要部の構成を示した断面図である。FIG. 3 is a sectional view showing a configuration of a main part of a semiconductor chip in a semiconductor device according to a third embodiment of the present invention.
【図４】本発明の実施例４による半導体装置における半
導体チップの主要部の構成を示した平面図である。FIG. 4 is a plan view showing a configuration of a main part of a semiconductor chip in a semiconductor device according to a fourth embodiment of the present invention.
【図５】本発明の実施例５による半導体装置における半
導体チップの主要部の構成を示した平面図である。FIG. 5 is a plan view showing a configuration of a main part of a semiconductor chip in a semiconductor device according to a fifth embodiment of the present invention.
【図６】本発明の実施例６による半導体装置における半
導体チップの主要部の構成を示した平面図である。FIG. 6 is a plan view showing a configuration of a main part of a semiconductor chip in a semiconductor device according to a sixth embodiment of the present invention.
【図７】従来の半導体装置の要部構成を拡大して示した
断面図である。FIG. 7 is a cross-sectional view showing an enlarged main part configuration of a conventional semiconductor device.
１ 半導体チップ ２ ポリイミド膜 ２ａ，２ｃ，２ｄ，２ｅ 厚みが小さいポリイミド膜 ３，１１ ボンディングパッド ４ ボンディングボール ５，１２ 開口 ７ 金線 ８ インナーリード ９ 封止樹脂 １０ アウターリード １３ 半導体チップ １４，１５ ボンディングパッド １６，２３ 開口 １８ 金線 １９ ボンディングボール ２０ インナーリード ２１ アウターリード ２２ 封止樹脂 ２４ ポリイミド膜のクラック部分 ２５ ポリイミド膜の界面剥離部分 ２６ ポリイミド膜の開口間に位置する部分 1 Semiconductor Chip 2 Polyimide Film 2a, 2c, 2d, 2e Thin Polyimide Film 3,11 Bonding Pad 4 Bonding Ball 5,12 Opening 7 Gold Wire 8 Inner Lead 9 Encapsulating Resin 10 Outer Lead 13 Semiconductor Chip 14, 15 Bonding Pads 16 and 23 Openings 18 Gold wires 19 Bonding balls 20 Inner leads 21 Outer leads 22 Sealing resin 24 Polyimide film cracked portions 25 Polyimide film interface peeled portions 26 Polyimide film located between openings
Claims (4)
衝するための硬化樹脂膜で被覆され、当該硬化樹脂膜に
前記チップ表面に形成されているワイヤーボンディング
用のボンディングパッドを表出させるための開口が形成
されてなる半導体装置において、 前記硬化樹脂膜の前記開口の周辺に位置する領域がその
他の領域よりも小さい厚みに形成され、当該厚みが前記
ボンディングパッドにボンディングされるべきワイヤー
ボンディングボールの厚みの半分以下になっていること
を特徴とする半導体装置。1. A chip surface is coated with a cured resin film for buffering a mechanical shock from the outside, and the cured resin film exposes a bonding pad for wire bonding formed on the chip surface. In the semiconductor device in which the opening is formed, a region of the cured resin film located around the opening is formed to have a smaller thickness than other regions, and the thickness is a wire bonding ball to be bonded to the bonding pad. Is less than half the thickness of the semiconductor device.
は、前記チップ表面に形成されている２個以上の前記ボ
ンディングパッドをそれぞれ表出させるための２個以上
の開口が形成されており、前記硬化樹脂膜の前記２個以
上の開口のうちの互いに隣接する２つの開口間に位置し
ている部分が、前記小さい厚みに形成されている請求項
１に記載の半導体装置。2. The cured resin film covering the surface of the chip is formed with two or more openings for exposing the two or more bonding pads formed on the surface of the chip, respectively. The semiconductor device according to claim 1, wherein a portion of the two or more openings of the cured resin film located between two adjacent openings is formed to have the small thickness.
は、前記チップ表面に形成されている複数の前記ボンデ
ィングパッドをそれぞれ表出させるための複数の開口が
形成されており、前記硬化樹脂膜の前記複数の開口のそ
れぞれの周辺領域を含む一繋がりの領域が、前記小さい
厚みに形成されている請求項１に記載の半導体装置。3. The cured resin film covering the surface of the chip is formed with a plurality of openings for exposing the plurality of bonding pads formed on the surface of the chip, respectively. The semiconductor device according to claim 1, wherein a continuous region including peripheral regions of each of the plurality of openings is formed to have the small thickness.
求項１〜３のいずれかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein the cured resin film is a polyimide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7235609A JPH0982851A (en) | 1995-09-13 | 1995-09-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7235609A JPH0982851A (en) | 1995-09-13 | 1995-09-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0982851A true JPH0982851A (en) | 1997-03-28 |
Family
ID=16988551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7235609A Pending JPH0982851A (en) | 1995-09-13 | 1995-09-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0982851A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017212248A (en) * | 2016-05-23 | 2017-11-30 | サンケン電気株式会社 | Semiconductor device |
| JP7176662B1 (en) * | 2021-11-04 | 2022-11-22 | 三菱電機株式会社 | Semiconductor equipment and power conversion equipment |
-
1995
- 1995-09-13 JP JP7235609A patent/JPH0982851A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017212248A (en) * | 2016-05-23 | 2017-11-30 | サンケン電気株式会社 | Semiconductor device |
| JP7176662B1 (en) * | 2021-11-04 | 2022-11-22 | 三菱電機株式会社 | Semiconductor equipment and power conversion equipment |
| WO2023079640A1 (en) * | 2021-11-04 | 2023-05-11 | 三菱電機株式会社 | Semiconductor device and power conversion apparatus |
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