JPH0982096A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high speed, low power consumption nonvolatile semiconductor memory having a small chip area by selecting a bit line without setting the bit lines collectively at a predetermined voltage after application of a voltage for rewriting data thereby inspecting the rewritten state. SOLUTION: A bit line control circuit 2 performs writing, reading, rewriting and verifying of data for a memory cell array 1. The circuit 2 is connected with a data I/O buffer 6 and receives the output from a column decoder 3 receiving an address signal from an address butter 4. The circuit 2 comprises a CMOS flip-flop and performs latching operation for writing/rewriting data or sense operation for bit line potential and verify read-out. After a data writing operation for applying a writing voltage to a selected memory cell, a verify read-out for inspecting the writing state of memory cell applied with a voltage is performed without setting the bit lines collectively at 0V or Vcc .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a NAND cell, NOR cell, AND cell,
The present invention relates to a nonvolatile semiconductor memory device such as a DINOR cell type EEPROM.

[0002]

2. Description of the Related Art Conventionally, as one of semiconductor memory devices, an electrically rewritable EEPROM has been known. Above all, NAN by connecting a plurality of memory cells in series
NAND cell type EEPROM forming a D cell block
M has attracted attention as a material that can be highly integrated.

One memory cell of a NAND cell type EEPROM is a FET-MO in which a floating gate (charge storage layer) and a control gate are laminated on a semiconductor substrate with an insulating film interposed therebetween.
It has an S structure. Then, a plurality of memory cells are connected in series so that adjacent memory cells share a source / drain to form a NAND cell, which is connected to a bit line as a unit. Such NAND cells are arranged in a matrix to form a memory cell array. The memory cell array is integrally formed in a p-type substrate or a p-type well.

NANDs arranged in the column direction of a memory cell array
The drain at one end of the cell is commonly connected to a bit line via a select gate transistor, and the source at the other end is also connected to a common source line via a select gate transistor. The control gate of the memory transistor and the gate electrode of the selection gate transistor have control gate lines (word lines) in the row direction of the memory cell array,
Commonly connected as a select gate line.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory cell located farthest from the bit line contact. A high voltage V is applied to the control gate of the selected memory cell.
pp (= about 20V) is applied, the intermediate potential VMWL (= about 10V) is applied to the control gate and the select gate of the memory cell on the bit line contact side, and 0V or 0V depending on the data is applied to the bit line. Intermediate potential VMBL (= 8V)
give. When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. This shifts the threshold value of the selected memory cell in the positive direction.
This state is, for example, "1". When an intermediate potential is applied to the bit line, electron injection does not occur, so the threshold value does not change and remains negative. This state is "0".

Data erasing is simultaneously performed on all the memory cells in the selected NAND cell block.
That is, all the control gates in the selected NAND cell block are set to 0V, and the bit line, the source line, the p-type well (or p-type substrate), the control gate in the non-selected NAND cell block, and all the selection gates are set high. A voltage of about 20V is applied. As a result, in all the memory cells in the selected NAND cell block, electrons in the floating gate are emitted to the p-type well (or p-type substrate), and the threshold voltage shifts in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to 0V, the control gates and the selection gates of the other memory cells are set to the power supply voltage Vcc or the voltage VH higher than the power supply voltage, and the current in the selected memory cell is changed. It is carried out by detecting whether or not it flows.

As is clear from the above description of the operation, the NA
In the ND cell type EEPROM, the non-selected memory cells act as transfer gates during write and read operations. From this viewpoint, the threshold voltage of the written memory cell is limited. For example, the preferable range of the threshold value of the memory cell in which “1” is written is Vcc =
In the case of 3V, it becomes about 0.5 to 2.0V. Considering the change with time after data writing, the variation in manufacturing parameters of memory cells, and the variation in power supply potential, the threshold distribution after data writing is required to be in a smaller range.

However, it is difficult to keep the threshold value range after "1" writing within the permissible range in the conventional method of writing data in all memory cells under the same condition with fixed write potential and write time. . For example, the characteristics of memory cells vary due to variations in the manufacturing process. Therefore, looking at the write characteristics, there are memory cells that are easily written and memory cells that are hard to be written. On the other hand, a method has been proposed in which writing is performed while verifying by adjusting the writing time so that the threshold value of each memory cell is written within a desired range (JP-A-5-144277). Gazette).

FIG. 5 shows a configuration example of the bit line control circuit,
FIG. 24 shows a conventional example of the operation during write pulse application / write verify. After the write data is latched by the CMOS flip-flop FF from the input / output lines IO and / IO, the precharge signal φP becomes “H”,
The bit line BLi is precharged to (Vcc-Vthn). The voltage VMB is from Vcc to the intermediate potential VMBL (up to 8).
V). After that, the signal φF becomes VMWL (-10V), and the bit line BLi becomes 0V depending on the latched data.
Or VMBL (~ 8V). 0 when writing "1"
V, it is 8 V in the case of writing "0". At this time, when the selection gate SG1 is 10V, the SG2 is 0V, and the control gate is CG2, CG1 is 10V, CG2
Is high voltage Vpp (~ 20V), CG3 ~ CG8 is 10V
It is.

Select gates SG1 and SG2, control gate C
When G1 to CG8 are reset to 0V, the signal .phi.F becomes "L" and the reset signal .phi.R becomes "H", and the bit line BLi is reset to 0V. Then, the verify read operation is performed.

In the verify read operation, as in the normal read operation, first, the precharge signal φP becomes "H" and the bit line BLi is precharged to (Vcc-Vthn). Thereafter, the selection gate and the control gate are driven by the row decoder 5. After the select gates SG1 and SG2 and the control gates CG1 to CG8 are reset, the verify signal .phi.V becomes "H" and (Vcc-Vthn) is output only to the bit line BLi in which "0" is written.

Thereafter, φSP and φRP are “H”, φSN and φRN.
Becomes "L" and φF becomes "H". After the signal .phi.SP is "L" and .phi.SN is "H" to sense the bit line potential, the signal .phi.RP is "L" and .phi.RN is "H" and the rewrite data is latched. At this time, the relation between write data, memory cell data, and rewrite data is
It is as shown in (Table 1) below.

[0014]

[Table 1]

The characteristic of this conventional system is that it includes an operation (corresponding to FIG. 24A) of setting all the bit lines to 0 V at the end of the write pulse applying operation. During the write verify read operation, it is necessary to set the bit line to the “H” level in advance before reading the data in the memory cell to the bit line. Therefore, the bit line potential is set at the beginning of the write verify read operation for all bit lines. Must be charged to the (Vcc-Vthn) potential.
When the operation system of FIG. 24 is used, all the "0" write bit lines must be reciprocated between 8V and 0V in the write pulse application operation / write verify read operation cycle.

Therefore, 8 V is applied during the write pulse application operation.
After discharging all the bit lines charged up to 0V once,
During the next write pulse applying operation, all the "0" write bit lines must be charged up to 8V. That is, since the number of bit lines that perform charging / discharging between 0V and 8V during the write pulse application operation / write verify read operation increases, the power consumption becomes very large and the bit line charging / discharging operation 0V → (Vcc -Vthn),
The time required for each operation of (Vcc-Vthn) → 8V, 8V → 0V becomes long. Therefore, there has conventionally been a problem that the time required for the write pulse application operation and the write sequence becomes long.

As described above, when the conventional write pulse application operation / write verify read operation method is used, the number of bit lines for charging / discharging between 0V and 8V during operation increases, and therefore power consumption increases. However, there is a problem that the time required for the charging / discharging operation of the bit line becomes long and the time required for the write pulse applying operation and the write sequence becomes long.

On the other hand, the EEP which enables electrical rewriting
Another example of the ROM is a NOR cell type EEPROM.

One memory cell of the NOR cell type EEPROM is, like the NAND cell type, a FET-MOS structure in which a floating gate (charge storage layer) and a control gate are laminated on a semiconductor substrate via an insulating film. Has this NOR
The cells are arranged in a matrix to form a memory cell array. The memory cell array is integrally formed in a p-type substrate or a p-type well. An equivalent circuit of the memory cell array of the NOR cell type EEPROM is shown in FIG.

The operation of this NOR cell type EEPROM is as follows.
It is as follows. During the data write operation, a high voltage 12V is applied to the gate (word line) of the selected memory cell, and 6V or 0V is applied to the bit line depending on the data. When 6 V is applied to the bit line, the electrons flowing near the drain of the memory cell are accelerated, and high energy electrons are injected into the floating gate in order to obtain high energy. As a result, the threshold value of the selected memory cell shifts to a region higher than the power supply voltage Vcc. This state is, for example, "1". When 0V is applied to the bit line, electron injection does not occur, so the threshold voltage does not change,
Stops between 0V and Vcc. This state is "0".

During the data erasing operation, -12V is applied to the selected word line and Vcc or 0V is applied to the bit line according to the data. When Vcc is applied to the bit line, electrons in the floating gate are emitted to the bit line, and the threshold voltage is lowered to a value between 0V and Vcc ("0" erase). When 0V is applied to the bit line, electron emission does not occur, so the threshold voltage does not change and is higher than Vcc ("1" erase).

The data read operation is performed by setting the selected word line to Vcc and detecting whether or not a current flows in the selected memory cell.

As is clear from the above description of the operation, NO
In the R cell type EEPROM, the threshold voltage of the erased memory cell is limited. For example, a preferable range of the threshold value of a memory cell erased from "0" is Vcc =
In the case of 3V, it becomes about 0.5 to 2.0V. Considering changes over time after data erasure, variations in manufacturing parameters of memory cells, and variations in power supply potential, the threshold distribution after data erasure is required to be in a smaller range.

However, it is difficult to keep the threshold value range after "0" erase within an allowable range in the conventional method of erasing data in all memory cells under the same condition with fixed erase potential and erase time. . For example, the characteristics of memory cells vary due to variations in the manufacturing process. Therefore, looking at the write characteristics, there are memory cells that are easily erased and memory cells that are not easily erased. On the other hand, there has been proposed a method of erasing while verifying by adjusting the erasing time so that the threshold of each memory cell is erased so as to be within a desired range.

Next, FIG. 25 shows a circuit configuration of a bit line control circuit according to a conventional example in the NOR cell type EEPROM.
FIG. 26 shows operation timings of erase pulse application / erase verify read when the conventional method is used (for details, see Japanese Patent Laid-Open No. 5-144277). The circuit configuration of FIG. 25 differs from the circuit configuration of FIG. 18 in that the transistors Qn21 and Qn22 are present. In the conventional method, when the erase verify read operation is started following the erase pulse application operation, the bit line collective charging operation of charging all the bit lines to the Vcc potential is performed, and then the memory cell data is verified. In this scheme,
Every time the erase verify read operation is performed, all "1" data erase bit lines are charged from 0V to Vcc potential and then discharged to 0V again.

Therefore, when the conventional method is used, the number of bit lines for charging / discharging between 0V and Vcc increases during the erase pulse applying operation / erase verify read operation, resulting in very large power consumption and bit line. 0V → Vcc → 0
The time required for each operation of V becomes long. Therefore, there is a problem that the time required for the erase sequence becomes long.

Furthermore, in the conventional circuit configuration,
In order to discharge the bit line of "1" data erase in the bit line control circuit during the erase verify read operation, an element for this discharge (corresponding to the transistors Qn21, Qn22 in FIG. 25) is required. The number of elements in the line control circuit increases. In addition, there is a problem that the time required for the operation becomes long because the batch charge operation to the Vcc potential of the bit line is required at the beginning of the discharge operation or the erase verify operation.

As described above, when the conventional erase pulse applying operation / erase verify read operation method is used,
Since the number of bit lines that perform charging / discharging between 0 V and Vcc during operation increases, the power consumption becomes very large and the time required for charging / discharging the bit lines becomes long, and therefore erase pulse application operation and erase operation are performed. Sequence takes a long time,
There was a problem. Further, since the conventional bit line control circuit has a large number of elements, there is a problem that the chip size becomes large.

[0029]

As described above, when the conventional write pulse applying operation / write verify read operation method or the conventional erase pulse applying operation / erase verify read operation method is used, power consumption increases. In addition, there are problems that the required operation time is long and the chip area is large.

The present invention has been made in consideration of the above circumstances, and an object thereof is to achieve low power consumption, high speed data rewriting operations such as writing and erasing, and a small chip area. It is to provide a semiconductor memory device.

[0031]

[Means for Solving the Problems]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, according to the present invention, a memory cell array in which memory cells or memory cell units having a plurality of connected memory cells are arranged in an array, column selecting means for selecting a bit line of the memory cell array, and the memory cell array of the memory cell array. A data latch / sense amplifier provided at one end in the bit line direction for performing a sensing operation and a latch operation for rewriting data; a first operation for applying a voltage for rewriting data to a selected memory cell; A second operation of inspecting a data rewriting state of a memory cell to which a voltage is applied, and an operation sequence of rewriting the data of the memory cell by alternately repeating the first operation and the second operation,
In a non-volatile semiconductor memory device having means for automatically setting rewriting data for each bit in the following first operation according to the result of the inspection, the data latch / sense amplifier is a CMOS flip-flop. Then, one of the nodes is connected to the bit line via the transfer gate, and the bit line is set to 0 V after the first operation.
Alternatively, the second operation is performed by selecting a bit line without collectively setting Vcc.

(Operation) In the present invention, in the write pulse application operation / write verify read operation, the collective setting operation of the potentials of all bit lines to 0V or Vcc potential is not performed. At this time, in the bit line having a positive threshold voltage of the corresponding memory cell among the “0” write bit lines, the write pulse is applied once after being charged to the “H” level potential during the write pulse application operation. motion/
There is no decrease from the "H" level potential during any of the write verify read operations. For this reason,
Until the data writing to all the selected memory cells is completed, it remains fixed at the "H" level potential.

Therefore, the bit lines that need to be charged to the "H" level potential during the write pulse application operation are:
Of all the "0" write bit lines, only the bit line at a potential lower than the "H" level is required, and the number of bit lines that charge and discharge between 0V and the "H" level potential is higher than in the conventional example. Can be significantly reduced. For this reason, the power consumption can be significantly reduced and the time required for the charge / discharge operation of the bit line can be significantly reduced.

Further, in the present invention, in the erase pulse applying operation / erase verify read operation, the collective setting operation of the potentials of all bit lines to 0V or Vcc potential is not performed. At this time, in the "1" data erase bit line, once the potential becomes "L" level during the erase pulse applying operation or the erase verify read operation, the erase pulse applying operation and the erase verify read operation are performed. It does not rise from the "L" level potential. Therefore, it remains fixed at the "L" potential until the data erase of all the selected memory cells is completed.

Therefore, the bit lines that need to be discharged to the "L" level potential during the erase pulse application operation are
Since it does not exist except during the first erase pulse application operation, the number of bit lines to be charged / discharged can be significantly reduced as compared with the conventional example. Therefore, the power consumption can be significantly reduced, and the time required for the charging / discharging operation of the bit line can be greatly shortened, so that the operation can be speeded up.

Since the number of elements in the bit line control circuit can be reduced as compared with the conventional case, the chip area can be made smaller than the conventional case. As described above, according to the present invention, it is possible to provide a chip that consumes less power than the conventional one, has a high speed data rewriting operation, and is inexpensive.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a NAND cell type EEPROM according to the first embodiment of the present invention. Data writing / reading to / from the memory cell array 1
A bit line control circuit 2 is provided to perform rewriting and verify reading. The bit line control circuit 2 is connected to the data input / output buffer 6 and receives the address signal from the address buffer 4 and the column decoder 3
Receives as output. In addition, the memory cell array 1
A row decoder 5 for controlling a control gate and a select gate, and a substrate potential control circuit 7 for controlling the potential of the p substrate (or p type well) in which the memory cell array 1 is formed. ing.

The bit line control circuit 2 is mainly composed of a CMOS flip-flop, and latches data for writing, a sensing operation for reading the potential of the bit line, a sensing operation for verify reading after writing, and rewriting. Latch data.

2 (a) and 2 (b) are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array, and FIGS. 3 (a) and 3 (b) are respectively AA 'in FIG. 2 (a). And B
It is a -B 'sectional view. P surrounded by the element isolation oxide film 12
Type silicon substrate (or p-type well) 11 has a plurality of NANs
A memory cell array including D cells is formed. In the description of this embodiment, focusing on one NAND cell, eight memory cells M1 to M8 are connected in series to form one NAND cell. Each memory cell has a floating gate 1 on a substrate 11 with a gate insulating film 13 interposed therebetween.
4 (14 ₁ , 14 ₂ , ..., 14 ₈ ) are formed, and the control gate 16 (16 ₁ , 1
6 ₂ , ..., 16 ₈ ) are formed and configured. The n-type diffusion layers 19 serving as the source and drain of these memory cells are adjacent to each other, and the memory cells are connected in series.

Select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 1 formed at the same time as the floating gate and the control gate of the memory cell on the drain side and the source side of the NAND cell, respectively.
6 ₁₀ are provided. CVD is performed on the substrate on which elements are formed.
The oxide film 17 covers the bit line 18, and the bit line 18 is disposed on the oxide film 17. The bit line 18 is in contact with the drain side diffusion layer 19 at one end of the NAND cell. The control gates 14 of the NAND cells arranged in the row direction are commonly arranged as control gate lines CG1, CG2, ..., CG8. These control gate lines become word lines. The select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also arranged continuously in the row direction as select gate lines SG1 and SG2.

FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

FIG. 5 shows a specific structure of the bit line control circuit 2 in FIG. A CMOS flip-flop F that constitutes the sense amplifier and data latch circuit in this embodiment
F is an E type, p channel MOS transistor Qp1,
Qp2 and E type, n-channel MOS transistor Qn3,
A signal-synchronous CMOS inverter composed of Qn4 and an E-type p-channel MOS transistor Qp3, Q
p4 and E type, n-channel MOS transistor Qn5, Q
a signal synchronous CMOS inverter composed of n6,
It consists of.

Between the output node N1 of the CMOS flip-flop FF and the bit line BLi, an E type, n channel MOS transistor Q controlled by the signal φF is provided.
connected through n7.

Between the bit line BLi and the power supply Vcc, E controlled by the output node N1 of the flip-flop FF.
Type, n-channel MOS transistor Qn8 and signal φ
An E type n-channel MOS transistor Qn9 controlled by V is connected in series. By these transistors, the bit line BLi is charged to (Vcc-Vth) according to the data of the CMOS flip-flop FF at the time of write-verify reading. However, (Vcc
Only the bit line at a potential lower than the −Vth) potential has Qn8,
Charged via Qn9.

The E type n-channel MOS transistor Qn11 is a circuit for precharging the bit line BLi to (Vcc-Vth). The E type n-channel MOS transistor Qn10 is a reset transistor for resetting the bit line BLi to 0V.

The two nodes of the CMOS flip-flop FF are input / output lines IO and / via the E type and n channel MOS transistors Qn1 and Qn2 which are transfer gates controlled by the column selection signal CSLi.
It is connected to IO.

The operation of the bit line control circuit of this embodiment will be described below.

FIG. 6 shows the operation timing at the time of reading. The signal φF becomes "L" and the bit lines BLi and C
The MOS flip-flop FF is separated. When the precharge signal φP becomes "H", the bit line BLi is precharged to (Vcc-Vthn). However, Vthn
Is the threshold voltage of the transistor Qn11. After this,
Select gates SG1 and SG2, control gates CG1 to CG8
Then, the row decoder 5 outputs a voltage. For example, CG
If 2 is selected, SG1, SG2, CG1, CG3
~ CG8 becomes Vcc and CG2 becomes 0V. When the data in the memory cell is "0", the bit line BLi is at "L" level, and when the data is "1", it remains at "H" level.

After the selection gate and the control gate are reset to 0V, the signals φSP and φRP are set to “H”, φSN and φRN are set to “L”, and the CMOS flip-flop FF is deactivated. φF becomes "H", and the potential of the bit line BLi is transmitted to the output line of the CMOS flip-flop FF. Then, .phi.SP becomes "L", .phi.SN becomes "H", the potential of the bit line BLi is sensed, and .phi.RP becomes "L" and .phi.RN become "H", and the sensed data is latched. The latched read data is output to the input / output lines IO and / IO when the column selection signal CSLi becomes "H".

FIG. 7 shows the operation during write pulse application / write verify. After the write data is latched by the CMOS flip-flop FF from the input / output lines IO and / IO, the voltage VMB changes from Vcc to the intermediate potential VMBL.
(~ 8V). After that, the signal φF changes to VMWL (-10
V), and the bit line BLi depends on the latched data.
Is 0V or VMBL. 0V when writing "1",
In the case of writing "0", it is VMBL. At this time, the select gate SG1 is VMWL, SG2 is 0V, and the control gate is C
When G2 is selected, CG1 is VMWL, CG2 is the high voltage Vpp (~ 20V), and CG3 to CG8 are VMWL.

Select gates SG1 and SG2, control gate C
When G1 to CG8 are reset to 0V, the signal .phi.F becomes "L", and then the verify read operation is started.

In the verify read operation, like the normal read operation, first, the precharge signal φP becomes "H", and only the bit line BLi corresponding to the "1" write is precharged to (Vcc-Vthn). In this case, since the bit line BLi corresponding to the "0" write is at a voltage of about 8V, the transistor Qn11 connected to the "0" write bit line has a gate voltage Vcc, a source voltage Vcc and a drain voltage 8V (normally , Vcc <8V),
When the threshold voltage Vthn of Qn11> 0V, Qn1
Since 1 is off, the corresponding bit line is held at 8V.

Thereafter, the row decoder 5 drives the selection gate and the control gate. Here, the select gate and the control gate are biased to the voltage at the time of write verify in the following (Table 2). At this time, the voltage of the bit line connected to the NAND cell whose threshold voltage of the selected memory cell is 0.5V or less is discharged to 0V potential (8V
The bit line at the potential is also discharged to 0 V when the threshold voltage of the corresponding selected memory cell is 0.5 V or less).

[0056]

[Table 2]

Select gates SG1 and SG2, control gate C
After G1 to CG8 are reset, verify signal φV
Becomes "H", which is lower than (Vcc-Vthn), and (Vcc-Vth) is output only to the bit line BLi in which "0" is written. This is because the node N1 is "H" only when "0" is written.
After this, φSP and φRP go to “H”, φSN and φRN go to “L”, and φF goes to “H”. After the signal φSP becomes “L” and φSN becomes “H” to sense the bit line potential, the signal φ
RP becomes “L” and φRN becomes “H”, and rewrite data is latched. At this time, the relationship among the write data, the memory cell data, and the rewrite data is as described above (Table 1)
It is as follows.

After the data writing to all the "1" write memory cells is completed, that is, when the latch data in all the flip-flops FF becomes "1" (the node N1 corresponds to the "H" level). , The data writing is completed, the bit line is reset, and then the process ends.

The write operation is repeated by the number of times of the above-described verify read / rewrite (write pulse application operation from the second time onward), and is completed. For example, 100 times. According to this verify read / rewrite,
After writing "1", the data in the memory cell is "0"
If so, "1" is rewritten. That is, when the threshold value of the memory cell is not 0.5 V or more, "1" write is performed to raise the threshold value again. If the data in the memory cell is "1" after writing "1", "0" is rewritten. That is, when the threshold voltage of the memory cell is 0.5 V or higher, the "0" write operation is performed so that the threshold voltage of the memory cell does not increase any more when rewriting.
When rewriting after writing "0", "0" rewriting is always performed.

In this way, only when the threshold value of the memory cell to which "1" is written has not reached 0.5 V, "1" is written again, and the memory cell to which "1" is written is unnecessary. It is possible to suppress an increase in the threshold value.

Erase, write pulse application, write verify read, control gates CG1 to CG at the time of read
8 and the potentials of the selection gates SG1 and SG2 are as described above (Table 2).
As shown in. In Table 2, power supply voltage Vcc = 3
It shows the potential relationship when V and the control gate CG2 are selected.

In the above embodiment, the threshold value evaluation reference in the verify operation is set to 0.5V, but this can be set to another appropriate value in relation to the allowable threshold value distribution. . The same applies to the one-time writing time,
For example, in order to make the final threshold distribution smaller, the write time for one time may be shortened and the write / verify operation may be repeated in small steps.
Further, in the embodiment, the NAND cell type EEPROM using tunnel injection has been described. However, even if another method such as hot electron injection is used, NAN
The present invention is effective as long as it is a D-cell type EEPROM.

In the operation system shown in FIG. 7, the bit line corresponding to the selected memory cell of the "0" write bit line whose threshold voltage is higher than 0.5 V is once charged to 8 V during the write pulse applying operation. After that, since the potential does not drop from 8V during both the write pulse application operation and the write verify read operation, it is 8V before the bit line reset operation (see the algorithm of FIG. 8).
It remains fixed at the electric potential.

In the write verify read operation, it is essential that the "0" write bit line is always read as "H" regardless of the corresponding selected memory cell data, and the "0" write bit line potential is previously set. It is possible to set the write-verify read result (rewrite data) to "0" regardless of whether the potential is 8V or (Vcc-Vthn). In addition, since only the "0" write bit line becomes 8V potential during the write pulse application operation, it is not necessary to lower the "0" write bit line potential from 8V before the write verify.
The operation system as shown in FIG. 7 becomes possible.

FIG. 8 is a flow chart showing an algorithm for writing data to the memory cell when the operation timing of FIG. 7 is used. In the method of FIG. 7,
The voltage of the bit line connected to the memory cell in which the threshold voltage of the memory cell is higher than 0.5V among the memory cells in which "0" is written is about 8V after the write pulse application operation is performed once. Is on the voltage.

If the data read operation (corresponding to the operation of FIG. 6) continues after the write sequence is completed when the write sequence is completed while maintaining this state, during the bit line precharge operation (φP is during the data read operation). Since the bit line does not drop from the 8V potential even during the "H" operation), the data determination of the memory cell is performed while the bit line is kept at the voltage of about 8V. It may be the cause. In other words, since the bit line potential at the time of determining the data of the memory cell is about 8 V, which is higher than the (Vcc-Vthn) potential at the normal time, the risk of erroneous reading increases.

In order to prevent this state, it is necessary to set the bit line to a voltage equal to or lower than the bit line precharge voltage (Vcc-Vthn) potential during the normal read operation before the write sequence is completed. To realize this, FIG.
There is a bit line potential reset operation item in the middle, and this operation item corresponds to FIG. 8 (S7). However, in FIG. 7, all bit line potentials are set to 0V during the bit line potential reset operation.
However, the present invention is not limited to this operation method. For example, when all bit line potentials are set to (Vcc-Vthn) potential at the time of bit line reset operation, At the completion (when "YES" in FIG. 8 (S6)), only the bit lines having a voltage higher than the (Vcc-Vthn) potential are lowered to 0V potential or the (Vcc-Vthn) potential. is there.

FIG. 9 shows a modification of the bit line control circuit shown in FIG. 9, the portion different from the circuit of FIG. 5 is the portion for precharging the bit line during the data read operation, that is, the portion of the transistor Qn11 in FIG.
It is being replaced with transistors Qd1 and Qp5. Therefore, in FIG. 9, the bit line potential is precharged to Vcc during the data read operation. FIG. 10 shows an operation timing chart in the data read operation using FIG. 9, and FIG. 11 shows an operation in the write pulse application / write verify operation.

Further, the potentials of the control gate, the selection gate, the bit line, and the p well (or substrate) at the time of each operation using FIGS. 9, 10 and 11 are shown in the following (Table 3). In Table 3, the power supply voltage Vcc is 3V and the control gate CG is
The potential relationship when 2 is selected is shown.

[0070]

[Table 3]

Compared to the operation timing shown in FIG. 6, the data read operation timing of FIG. 10 drives the portion where the bit line precharge potential level becomes Vcc potential and the bit line precharge transistors Qd1 and Qp5. Since only the signals φP and / φP are different and the other operations are the same, the operation can be understood similarly to the operation of FIG.

The operation timing of FIG. 11 is basically the same as the operation timing of FIG. The operation timing of FIG. 11 differs from the operation timing of FIG.
The voltage applied to the bit line for "0" writing during the write pulse application operation is Vcc, the bit line precharge voltage during the write verify read is the Vcc potential, and "H" during the write pulse application operation for the signal φF. "The level potential is the VH1 potential, the signal VMB is fixed at the Vcc potential, and the bit line reset operation is not performed. However, since the VH1 potential is higher than the (Vcc + Vthn) potential, it is possible to charge the bit line to the Vcc potential via the transistor Qn7 when the node N1 is at the Vcc potential. As shown in FIG. 11, the voltage applied to the “0” write bit line during the write pulse application operation is V
The present invention is also effective in the case of cc.

At the operation timings of FIGS. 10 and 11, since both the "H" level of the bit line is the Vcc potential, the bit line "H" level potential is lowered by the bit line reset operation shown in FIGS. 7 and 8. It is not necessary to do so, so the algorithm for writing data can omit the bit line reset operation as in FIG.
The bit line reset operation is not shown therein.

The operation timings of FIGS. 10 and 11 will be described below.

FIG. 10 shows the operation timing at the time of reading. The signal .phi.F becomes "L", and the bit line BLi and the CMOS flip-flop FF are disconnected. The bit lines BLi are precharged to Vcc by setting the precharge signals .phi.P and /.phi.P to "H" and "L", respectively. After this, select gates SG1 and SG2, control gate C
A voltage is output from the row decoder 5 to G1 to CG8.
For example, if CG2 is selected, SG1, SG2, C
G1 and CG3 to CG8 are Vcc, and CG2 is 0V. When the data in the memory cell is "0", the bit line BLi is at "L" level, and when the data is "1", it remains at "H" level.

After the selection gate and the control gate are reset to 0V, the signals φSP and φRP are set to “H”, φSN and φRN are set to “L”, and the CMOS flip-flop FF is inactivated. φF becomes "H", and the potential of the bit line BLi is transmitted to the output line of the CMOS flip-flop FF. Then, .phi.SP becomes "L", .phi.SN becomes "H", the potential of the bit line BLi is sensed, and .phi.RP becomes "L" and .phi.RN become "H", and the sensed data is latched. The latched read data is output to the input / output lines IO and / IO when the column selection signal CSLi becomes "H".

FIG. 11 shows the operation during write pulse application / write verify. Write data is transferred from the input / output lines IO and / IO to the CMOS flip-flop FF.
After being latched at, the signal φF becomes VH1, and the bit line BLi becomes 0V or Vcc depending on the latched data.
It is 0 V when "1" is written, and Vcc when "0" is written. At this time, the select gate SG1 is set to VMWL, S
When G2 is 0V and CG2 is selected as the control gate, CG1 is VMWL and CG2 is a high voltage Vpp (~ 20V).
CG3 to CG8 are VMWL.

Select gates SG1 and SG2, control gate C
After G1 to CG8 are reset to 0V, the signal .phi.F becomes "L", and then the verify read operation is started.

In the verify read operation, as in the normal read operation, first, the precharge signal φP is "H", / φ.
P becomes "L", and the bit line BLi corresponding to "1" data writing is precharged to Vcc. At this time, the bit line corresponding to the "1" data write is already V
Since it is at the cc potential, it is kept at the Vcc potential. Thereafter, the row decoder 5 drives the selection gate and the control gate. Select gates SG1 and SG2, control gate CG
After 1 to CG8 are reset, the verify signal .phi.V becomes "H" and Vcc-Vthn is output only to the bit line BLi in which "0" is written.

After that, φSP and φRP are “H”, φSN and φRN
Becomes "L" and φF becomes "H". After the signal .phi.SP is "L" and .phi.SN is "H" to sense the bit line potential, the signal .phi.RP is "L" and .phi.RN is "H" and the rewrite data is latched. At this time, the relation between write data, memory cell data, and rewrite data is
This is as described in (Table 1) in the above embodiment.

The write pulse application / write verify operation is repeated, for example, about 100 times and completed. Table 3 shows the potentials of the bit line BLi, the select gates SG1 and SG2, and the control gates CG1 to CG8 at the time of erasing, writing, reading, and verify reading in this embodiment. Here, a case where CG2 is selected is shown.

Here, the effect of using the above-described embodiment, that is, an advantage that is superior to the case of using the conventional method will be described. The operation timing chart in the conventional method when the circuit of FIG. 5 is used is as shown in FIG.
The difference in operation timing between FIG. 7 and FIG. 24 is only in the signal φP, the signal φR, and the potential of the bit line BLi.

The feature of this conventional system is that it includes an operation (corresponding to FIG. 24A) of setting all the bit lines to 0 V at the end of the write pulse applying operation. During the write verify read operation, it is necessary to set the bit line to the “H” level in advance before reading the data of the memory cell to the bit line. Therefore, the bit line potential is set to all bit lines at the beginning of the write verify read operation. (Vcc
An operation of charging to the −Vthn) potential is required. FIG.
If the operation method of (3) is used, all the "0" write bit lines must be reciprocated between 8V and 0V in the cycle of the write pulse application operation / write verify read operation.

Therefore, 8 V is applied during the write pulse application operation.
After discharging all the bit lines charged up to 0V once,
During the next write pulse applying operation, all the "0" write bit lines must be charged up to 8V. That is, since the number of bit lines that perform charging / discharging between 0V and 8V during the write pulse application operation / write verify read operation increases, the power consumption becomes very large and the bit line charging / discharging operation 0V → (Vcc -Vthn),
The time required for each operation of (Vcc-Vthn) → 8V, 8V → 0V becomes long. Therefore, there has conventionally been a problem that the time required for the write pulse application operation and the write sequence becomes long.

On the other hand, in the operation system shown in FIG. 7, in the bit line where the threshold voltage of the corresponding selected memory cell in the "0" write bit line is higher than 0.5V, the voltage is once charged to 8V during the write pulse application operation. After that, the potential does not drop from 8V during both the write pulse application operation and the write verify read operation, so it is fixed at 8V potential before the bit line reset operation (see the algorithm in FIG. 8). It remains.

This is characterized in that the "0" write bit line is determined to be at the "H" level in the write verify read operation, and even if the "0" write bit line potential is 8 V in advance (Vcc This is because there is no influence on the write verify read result (rewrite data) if it is determined to be at the “H” level even at the −Vthn) potential. Further, since all the bit lines that are at the 8V potential during the write pulse application operation are “0” write bit lines, it is not necessary to lower the “0” write bit line potential from 8V before the write verify. Such an operation method is possible.

Therefore, in the operation method of FIG.
Since there is no operation to discharge all the bit lines to 0V as in (a), the bit lines that need to be charged to 8V at the time of applying the write pulse are set to a voltage lower than 8V among all the "0" write bit lines. Only a certain bit line is needed. That is, as compared with the method of FIG. 13 in which all the “0” write bit lines are charged to 8 V each time the write pulse application operation is performed,
Since the number of bit lines for charging and discharging between V and 8V can be significantly reduced, power consumption can be significantly reduced.
In addition, since the number of charge / discharge bit lines is small, 0V → (V
Since the time required for the charge / discharge operation of (cc-Vthn), (Vcc-Vthn) → 8V, 8V → 0V can be greatly shortened, the time required for the write pulse application operation and the write sequence operation can be greatly shortened.

The present invention is also effective when the operation timing shown in FIG. 11 is used. In the operation method of FIG. 11, as in the operation method of FIG. 7, there is no operation of simultaneously discharging all bit lines during the write pulse application operation or the write verify read operation. Therefore, in the bit line where the threshold voltage of the corresponding selected memory cell is positive among the "0" write bit lines, after reaching the Vcc potential during the first write pulse application operation, the write sequence ends (see FIG. 24 (a)) It remains fixed at the Vcc potential.

Therefore, in the operation system of FIG. 11, unnecessary discharge of the bit line potential is not performed. That is, the bit lines to be discharged are "1" write bit line (during write pulse application operation) and the threshold voltage of the selected memory cell is 0.
Only the bit line of 5 V or less (during write verify read operation) is used. Also in this case, as in the operation of FIG. 7, it is possible to reduce the number of bit lines that are charged / discharged in the write pulse application operation / write verify read operation, and therefore the power consumption can be significantly reduced.
Further, since the time required for the charge / discharge operation of 0V → Vcc and Vcc → 0V can be greatly shortened, the time required for the write pulse application operation and the write sequence operation can be greatly shortened.

In addition to the effects described above, the use of the above embodiment can eliminate the operation of FIG.
The write verify read operation required time can be shortened by the operation required time shown in FIG.
In the operation method of 1, the operation speed can be increased by this factor.

FIG. 13 is a diagram showing another configuration example of the bit line control circuit 2. As a data latch and sense amplifier, E type p-channel MOS transistors Qp7, Qp
It has a CMOS flip-flop FF2 composed of 8, Qp9, Qp10 and E type n-channel MOS transistors Qn17, Qn18. This flip-flop FF
Two bits are provided for each bit line.

The node N1 on the bit line side of the CMOS flip-flop FF2 is connected to the bit line BL via a series circuit of an E type n channel MOS transistor Qn20 and a D type n channel MOS transistor Qd2. n
The channel MOS transistors Qn20 and Qd2 are controlled by the control signals BLCD and BLTR, respectively, and the CMO
The S flip-flop FF2 and the bit line are connected or disconnected. The signals BLTR and BLCD are temporarily connected to the VMWL node at the time of writing, and at this time VMWL = 10V, BLTR and BLC
D also becomes 10V, and the bit line BL is set to the same potential as the node N1.

Further, the signals BLTR and BLCD become Vcc and 0V at the time of reading, respectively, to transfer the bit line potential to the node N3, and at the same time, to the nodes N3 and N.
There is no conduction between 1 and 2.

The precharge signal BL is applied to the bit line BL.
An E type n channel MOS transistor Qn12 for bit line precharge controlled by the CU is provided. The bit line BL is set during the precharge operation via the transistor Qn12.

The node N2 of the flip-flop FF2 is
A series circuit of E type n-channel MOS transistors Qn15 and Qn16 is provided between the ground potential and 0V. Among these, the gate of the MOS transistor Qn15 receives the bit line potential sense signal BLSEN which becomes "H" at the time of sensing the bit line potential, and the remaining MOS transistors Qn15.
The gate of n16 is controlled by the node N3 between the transistors Qn20 and Qd2.

These MOS transistors set the latch data of the flip-flop FF2 according to the bit line potential during the read operation. Specifically, if the bit line is "H", the nodes N1 and N2 are "H" and "L", respectively, and if the bit line is "L", the nodes N1 and N2 are "L" and "L", respectively. H ".

Further, the node N of the flip-flop FF2
An E type n-channel MOS transistor Qn19 is provided between 1 and the ground potential 0V. In this transistor Qn19, the reset signal LRST of the flip-flop which becomes "H" during the reset operation of the flip-flop FF2.
Is input to the gate, and the reset operation is realized so that the nodes N1 and N2 are set to "L" and "H", respectively.

Signals SAP and 0V are input to the gates of the MOS transistors Qp9 and Qp7 forming the flip-flop FF2, respectively. The signal SAP becomes "H" during the reset operation of the flip-flop to turn off QP9, and Qp9, Qp10, Q during the reset operation.
It plays a role in preventing shoot-through current flowing in the n19 path. The signal SAP is kept in the "L" state except when the reset operation is performed, thereby realizing the data holding state of the flip-flop FF2.

Further, in VMM, n in which the p-channel MOS transistors Qp7 to 10 of the flip-flop FF2 are formed.
Type well and p-channel MOS transistors Qp7, Q
The potential applied to the common source node of p9, which is normally Vcc, is temporarily connected to the VMBL node during a write operation. At this time, since the VMBL node becomes 8V, the VMB node also becomes 8V. Further, the precharge potential BLCRL is normally at the Vcc potential and becomes 0V when the bit line is reset.

Next, the read operation will be described with reference to the timing chart of FIG. At the start of the read operation, the bit line potential is 0 V or more and (Vcc-Vthn) or less. In the read operation, first, the precharge signal BL
The CU changes from 0V to Vcc and the bit line becomes (Vcc-Vthn
), BLCU becomes 0 V, and the precharge operation ends. In addition, the signal SAP is 0V
From Vcc to Vcc, and then the signal LRST changes from 0V to Vcc, so that the node N1 in the flip-flop FF is
Is set to the "L" level, that is, 0V, so that the node N2 (not shown in FIG. 14) is set to the "H" level, that is, Vcc.
Becomes

In this case, since the signal SAP becomes Vcc earlier than the signal LRST becomes Vcc, the MOS transistor Q in the flip-flop FF2 of the circuit in FIG.
It is possible to prevent a shoot-through current in the path of p9, Qp10, Qn19, and to reduce the current consumption. After the nodes N1 all become 0V, the signals SAP and LRST both become 0V, and the setting of the latch data of the flip-flop FF2 is completed.

Of the control gates CG in the NAND cell including the selected memory cell, except the control gate corresponding to the gate electrode of the selected memory cell is charged to Vcc, for example, when CG2 is selected, CG1 and CG3. ~ 8 is Vcc
(Hereinafter, the selected memory cell is controlled by the control gate CG)
The case where 2 is used as the gate electrode will be described. CG2
The same operation can be realized when a control gate other than the above is selected. ). Further, the source line side select gate SG2 and the bit line contact side select gate SG1 are charged to Vcc.

After a fixed time (-10 μsec), all control gates C in the NAND cell including the selected memory cell are
G1 to 8 and both select gates SG1 and SG2 are 0V
Is set to This constant time means that the NAND cell (=
NAND cell including a selected memory cell of "0" data) is a value based on a time required for discharging, and normally, a NAND cell having the slowest discharge time among NAND cells including a selected memory cell of "0" data The bit line discharge time is set longer than the required time. At this point, the bit line potentials corresponding to the selected memory cell of "1" data are "H" and "0".
The bit line potential corresponding to the selected memory cell for data is "L".

Further, the bit line potential sense signal BLSEN
Changes from 0V to Vcc, and the bit line potential is sensed.
At this time, in the flip-flop FF2 corresponding to the bit line in "H", since both N3 and BLSEN are in "H", both Qn15 and Qn16 are turned on, so that the node N
2 becomes "L" (Qn15, Q rather than Qp7, Qp8 series circuit)
The n16 series circuit is set to have a larger current drive capacity. Therefore, when both Qn15 and Qn16 are turned on, the node N2 becomes "L". Therefore, the node N1 becomes "H". On the other hand, in the flip-flop FF2 corresponding to the bit line in "L", Qn16 is in the off state because N3 is in "L".
The second node N2 remains "H" and the node N1 remains "L".

In this way, the data state of the flip-flop FF is changed or held according to the level of the bit line, the memory cell data is read to the flip-flop FF, and the read data is latched as it is. . After that, the signal BLSEN becomes 0V, and subsequently read data is output to the IO and / IO,
It is transmitted to the data output buffer 6 and taken out. This completes the read operation.

FIG. 15 shows the operation at the time of writing / writing confirmation. Write data is input / output lines IO, / I
After being latched by the CMOS flip-flop FF from O, the precharge signal BLCU becomes "H" and the bit line BLi is precharged to (Vcc-Vthn).

Then, the signal BLCD becomes Vcc, and the bit line is kept at (Vcc-Vthn) or becomes 0V depending on the latched data. The voltage is 0 V when "1" is written, and (Vcc-Vthn) when "0" is written. Subsequently, VMB becomes 8V, and the signal BLTR and the signal BLCD become 10V. At this time, the potential of the "0" write bit line becomes (Vcc-Vthn) → 8V. Subsequently, when the selection gate SG1 is 10V, the SG2 is 0V, and the control gate is CG2, CG1 is 10V.
V and CG2 are high voltage Vpp (~ 20V), CG3 ~ CG
8 becomes 10V, and this state is maintained for a while.

Select gates SG1 and SG2, control gate C
After G1 to CG8 are reset to 0V, signal BLCD
Becomes “L”. Then, the write confirmation operation is performed.

In the write confirmation operation, first, the precharge signal BLCU becomes "H", and only the bit line BLi corresponding to "1" write is precharged to (Vcc-Vthn). In this case, since the transistor Qn12 connected to the bit line corresponding to "0" write is in the off state, the bit line potential corresponding to "0" write is maintained at 8V (same as the case of FIG. 7). . After this, the row decoder 5
Drives the selection gate and the control gate. After the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset, the bit line potential detection signal BLSEN is "H".
Becomes At this time, the flip-flop FF in which the node N1 of the latch is "H" before the write confirmation operation
At 2, the latch data does not change regardless of the voltage of the bit line, and the node N1 remains "H".

Further, the flip-flop FF2 in which the node N1 of the latch is "L" before the write confirmation operation is performed.
Then, when the voltage of the bit line is lower than the threshold voltage of the transistor Qn16, the node N1 is kept at "L", and when the voltage of the bit line is higher than the threshold voltage of the transistor Qn16, the transistor Qn16. Is turned on, and the node N1 goes from "L" to "H" (because the node N2 goes from "H" to "L").

In this way, the rewritten data is read and latched by the flip-flop FF2. At this time, the relationship among the write data, the memory cell data, and the rewrite data is as described above (Table 1).

After the data writing to all the "1" write memory cells is completed, that is, when the latch data in all the flip-flops FF2 becomes "1" (the node N1 corresponds to the "H" level), " After the data writing is completed ”and the bit line reset operation is performed,
finish.

The potentials of the erase, write pulse application, write verify read, control gate at the time of data read, etc. are as shown in (Table 2) above. However, (Table 2) shows the potential relationship when the power supply voltage Vcc is 3 V and the control gate CG2 is selected.

When the method of FIG. 15 is used, the "0" write bit line is set to 8V during the write sequence, and is 8V higher than the bit line precharge voltage (Vcc-Vthn) during the data read operation. Is a high voltage, a bit line reset operation is required before the end of the write sequence as in the case of FIG.
FIG. 8 shows the algorithm at the time of writing when the method of FIG.

The operation method of FIG. 15 has the same effect as the case of using the operation method of FIG. That is, in the bit line of the "0" write bit line in which the threshold voltage of the corresponding selected memory cell is positive, the potential does not drop from 8V during both the write pulse application operation and the write verify read operation. Therefore, after being charged to 8V by the first write pulse application operation, it remains fixed at 8V potential before the bit line reset operation (see the algorithm of FIG. 8).

This is a flip-flop FF having "0" write data in the write verify read operation.
2 is because the node N2 is at the "L" level, so that the latch data after the write verification of the flip-flop FF2 has the "0" write data regardless of the voltage of the bit line. Therefore, even if the "0" write bit line potential is 8 V (Vcc-Vthn) in advance, there is no influence on the write verify read result (rewrite data). In addition, since only the "0" write bit line becomes 8V potential during the write pulse application operation, it is not necessary to lower the "0" write bit line potential from 8V before the write verify. Such an operation method is possible.

Therefore, even when the operation system shown in FIG. 15 is used, there is no operation for discharging all the bit lines to 0 V as shown in FIG.
The bit lines that need to be charged up to V need only be the bit lines that are at a voltage lower than 8V among all the "0" write bit lines, and therefore, all the "0" write bit lines must be written with each write pulse application operation. Compared with the method of FIG. 24 that charges up to 8V, the number of bit lines that charge and discharge between 0V and 8V can be significantly reduced, so that power consumption can be significantly reduced. Moreover, since the number of charge / discharge bit lines is small, 0V → (Vcc-Vthn), (Vcc-Vthn) → 8
Since the time required for the charge / discharge operation of V, 8V → 0V can be greatly shortened, the time required for the write pulse application operation and the write sequence operation can be greatly shortened.

In addition to the effects described above, the use of the above embodiment can eliminate the operation of FIG.
There is an advantage in that the time required for the write verify read operation can be shortened by the time required for the operation shown in FIG.

In the above embodiments, the NAND cell type EEP is used.
Although the present invention has been described by exemplifying the case where the present invention is applied to the data writing sequence to the ROM, the present invention is not limited to the above-described embodiment and can be variously modified. For example, the present invention can be applied to the data erasing sequence of the NOR cell type EEPROM as shown in FIG. Below, this NOR cell type EE
An embodiment in which the present invention is applied to a PROM data erasing sequence will be described.

FIG. 17 is a flowchart showing an algorithm for erasing data in the NOR cell type EEPROM. Further, FIG. 18 shows a NOR cell type EEPR.
The bit line control circuit used when the present invention is applied to the OM data erase sequence is shown. The circuit of FIG. 18 is shown in FIG.
This circuit has a circuit configuration in which the transistors Qn8 and Qn9 are removed from the circuit shown in FIG. 7, and has a smaller number of elements than the bit line control circuit in FIGS. 5 and 9. However, by using this circuit, In addition, whether or not to apply the erase pulse can be controlled for each bit line, that is, for each selected memory cell. That is, the verify erase operation for each bit can be realized.

FIG. 19 shows the data read operation timing when the circuit of FIG. 18 is used, and FIG. 20 shows the erase pulse application / erase verify read operation timing.

FIG. 19 shows the operation timing at the time of reading. The signal .phi.F becomes "L" and the bit line BLI and the CMOS flip-flop FF are disconnected. The bit lines BLi are precharged to Vcc by setting the precharge signals .phi.P and /.phi.P to "H" and "L", respectively. After this, a voltage is output from the row decoder 5 to the word line, and the word line becomes Vcc. When the data in the memory cell is "0", the bit line BLi becomes "L" level,
When the data is "1", it remains at "H" level.

After the word line is reset to 0V, the signals φSP and φRP are set to “H”, φSN and φRN are set to “L”, and C
After the MOS flip-flop FF becomes inactive,
The signal φF becomes "H" and the potential of the bit line BLi is CM.
It is transmitted to the output line of the OS flip-flop FF. Then, φSP becomes “L” and φSN becomes “H”, and the bit line BLi
Is sensed, φRP becomes “L” and φRN becomes “H”, and the sensed data is latched. The latched read data is output to the input / output lines IO and / IO when the column selection signal CSLi becomes "H".

FIG. 20 shows the operation during erase pulse application / erase verify. Erase data is input / output line IO,
After being latched from / IO to the CMOS flip-flop FF, the signal φF becomes VH1, and the bit line BLi becomes 0V or Vcc depending on the latched data. It is 0V for "1" erase and Vcc for "0" erase. At this time, the word line is at -12V.

When the word line WL is reset to 0V,
The signal .phi.F becomes "L", and then the erase verify read operation is started. At this time, the "0" erase bit line is V
At the cc potential, the "1" erase bit line is at 0V. Therefore,
In the erase verify read operation, only the data in the "0" erase memory cell is read. Then, the row decoder 5 drives the word line WL.

Thereafter, φSP and φRP are “H”, φSN and φRN.
Becomes "L" and φF becomes "H". After the signal φSP is “L” and φSN is “H” to sense the bit line potential, the signal φRP is “L” and φRN is “H”, and the re-erase data is latched. At this time, the relationship among erased data, memory cell data, and re-erased data is as shown in (Table 4).

[0127]

[Table 4]

The erase pulse application / erase verify operation is
For example, the process is repeated about 100 times and the process ends. The potentials of the bit line BLi and the word line WL at the time of erasing, writing, reading, and verify reading in this embodiment are shown in (Table 5) below. Here, the case where Vcc = 3V is shown.

[0129]

[Table 5]

Here, the circuit configuration of the bit line control circuit according to the conventional example in the NOR cell type EEPROM is shown in FIG.
FIG. 26 shows the operation timing of erase pulse application / erase verify read when the conventional method is used.

The circuit configuration of FIG. 25 differs from the circuit configuration of FIG. 18 in that transistors Qn21 and Qn22 are present. In the conventional method, when the erase verify read operation is started following the erase pulse application operation, the bit line collective charging operation of charging all the bit lines to the Vcc potential is performed, and then the memory cell data is verified. In this system, all the "1" data erase bit lines are changed from 0V to Vcc at every erase verify read operation.
After being charged to the potential, it will be discharged to 0V again.

In comparison with this, in the embodiment shown in FIG. 20, the state when the erase pulse applying operation is completed, that is, the voltage of the bit line corresponding to "0" data erase is Vcc potential, and "1" data erase is performed. The voltage of the bit line corresponding to is 0V
Even after the erase-verify read operation is started, the word line WL is maintained until the word line WL becomes the “H” level potential. And
Only the bit line corresponding to the memory cell in which the data of the memory cell in which the "0" data is erased becomes "0", that is, the memory cell in which the data has been erased is changed from the "H" level potential (Vcc) to "L". It will fall to the level potential (0V potential). Further, the bit line once lowered to the "L" level potential during the erase pulse application operation or the erase verify read operation is kept at the "L" level potential until the erase sequence operation is completed.

Therefore, as compared with the case of using the conventional method,
When the operation of FIG. 20 is used, the number of bit lines for charging / discharging between 0V and Vcc potential becomes much smaller,
Since the power consumption can be significantly reduced and the number of bit lines for charging / discharging is small, the operation time required for charging / discharging the bit lines can be shortened, and therefore high-speed data erasing can be realized.

In addition to the advantages described above, the present invention has the following advantages. The circuit shown in FIG. 25 is conventionally used for the bit-by-bit verify operation for erasing data, and the characteristic of this circuit is the transistors Qn21 and Qn22. The transistors Qn21 and Qn22 perform the operation of setting the potentials of all the bit lines corresponding to the "1" data erase to 0V when the signal φV during the erase verify read operation is at the "H" level. The data in the flip-flop FF corresponding to the data erase is set to "1".
, And the verify operation for each bit of the data erasing operation is realized (see Table 4).

That is, the memory cell for transferring the memory cell data to the flip-flop during the erase verify read, that is, the memory cell for reading the data is set to "0".
It is limited to memory cells that erase data. In order to realize this operation, the transistors Qn21 and Qn22 in FIG. 25 are necessary, and when the signal φV in FIG. 26 is at the “H” level, the bit line for erasing the “1” data is set to 0V. Action is required.

On the other hand, in the operation system shown in FIG. 20, the bit line potential during the erase pulse applying operation, that is, the Vcc potential in the bit line corresponding to "0" erase, and the 0V potential in the bit line corresponding to "1" erase. To the state where the word line becomes "H" during the erase verify read operation (corresponding to the state where the voltage of the bit line for "0" read starts to drop from Vcc for "0" erase in FIG. 20). To be kept. Therefore,
Since the bit line potential corresponding to "1" data erasing is 0 V potential before the word line potential becomes "H", the bit line potential corresponding to "1" data erasing is "0" regardless of the memory cell data. The memory cell sensed as the L level and corresponding to the "1" data erase is kept in the erase non-selected state, that is, the "1" data erase state. In this way,
The circuit shown in FIG. 18 and the operation shown in FIG. 20 realize the data-by-bit verify operation for each bit.

Using the method shown in FIGS. 18 and 20,
Compared with the method shown in FIGS. 25 and 26, the number of elements forming the bit line control circuit can be reduced (transistors Qn21 and Qn22 can be eliminated), and therefore the pattern area of the bit line control circuit can be reduced. It is possible to realize an inexpensive chip having a smaller chip area than ever before. Further, when the method shown in FIGS. 18 and 20 is used,
The operation can be reduced as compared with the method shown in FIG. That is, all bit lines in FIG.
Operation to set potential (signals φP and / φP are Vc
C, 0V) and "1" data erase bit line discharge operation (operation when signal φV is at Vcc potential) can be omitted, thus realizing a faster erase sequence than when using the conventional method. it can.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made. For example, FIG. 20 shows the case where the "0" data erase bit line is at the Vcc potential during the erase pulse applying operation or erase verify read operation.
The present invention is also effective when the data erase bit line is at the (Vcc-Vthn) potential (corresponding to a voltage lower than the VMB node at Vcc by the threshold voltage of the transfer gate Qn7) or a voltage higher than Vcc. Is. When the voltage is higher than Vcc, the VMB node (the "H" level voltage node of the flip-flop FF) is also V
This can be easily achieved by setting the voltage higher than cc.

In the above embodiment of the NAND cell type EEPROM, the case where the number of memory cells connected in series in one NAND cell is eight has been described, but the number of memory cells connected in series is eight. Instead, the present invention is also applicable to the case of 2, 4, 16, 32, 64, etc.

In the above, an embodiment in which the present invention is applied to a NAND cell type EEPROM or a NOR cell type EEPROM has been shown, but the present invention is also effective for other devices. For example, DINOR cell type EEP
The present invention can be applied to a ROM, an AND cell type EEPROM, a NOR cell type EEPROM with a selection transistor, and the like.

FIG. 21 shows an equivalent circuit diagram of the memory cell array in the DINOR cell type EEPROM. DINO
For details of the R cell type EEPROM, see "H. Onoda et a
L., IEDM Tech. Digest, 1992, pp. 599-602 ". Fig. 22 shows an equivalent circuit diagram of a memory cell array in an AND cell type EEPROM. AND cell type EEPR
For details of OM, see “H.Kume et al., IEDM Tech.Dige
St. 1992, pp. 991-993 ". Also, a memory cell equivalent circuit diagram in a NOR cell type EEPROM with a select transistor is shown in FIG.

Although the present invention has been described using the embodiments, the present invention can be variously modified and implemented without departing from the scope of the invention.

[0143]

As described above, according to the present invention, during the repetitive operation of the data rewriting (including both data writing and data erasing) pulse rewriting operation and the rewrite verify read operation, the rewriting pulse applying operation is performed. Since the voltage of the bit line at the "H" level is not discharged through a route other than the route through the memory cell, the number of bit lines for charging / discharging can be reduced as compared with the conventional one, and all bit lines can be reduced. Operations such as collective discharge operation can be omitted. Therefore, it is possible to realize a chip capable of low power consumption and high-speed operation.

Further, since the number of elements of the circuit for realizing the data-by-bit verify operation for data erasing can be reduced, a chip having a smaller chip area than the conventional one, that is, an inexpensive chip can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a NAND cell type EEPROM according to first, second, and third embodiments.

FIG. 2 is a plan view and an equivalent circuit diagram showing a NAND cell configuration of the embodiment.

FIG. 3 is a sectional view taken along line AA ′ and BB ′ of FIG.

FIG. 4 is an equivalent circuit diagram of the memory cell array.

FIG. 5 is a diagram showing a configuration of a bit line control circuit according to the first embodiment.

FIG. 6 is a timing chart of a data read operation according to the first embodiment.

FIG. 7 is a timing chart of a write pulse application operation / write verify read operation according to the first embodiment.

FIG. 8 is a view showing a flowchart showing an algorithm at the time of writing data in the first and third embodiments.

FIG. 9 is a diagram showing a configuration of a bit line control circuit according to the second embodiment.

FIG. 10 is a timing chart of a data read operation according to the second embodiment.

FIG. 11 is a timing diagram of a write pulse application operation / write verify read operation according to the second embodiment.

FIG. 12 is a view showing a flowchart showing an algorithm at the time of writing data in the second embodiment.

FIG. 13 is a diagram showing a configuration of a bit line control circuit according to a third embodiment.

FIG. 14 is a timing chart of a data read operation according to the third embodiment.

FIG. 15 is a timing diagram of a write pulse application operation / write verify read operation according to the third embodiment.

FIG. 16 is an equivalent circuit diagram of a memory cell array in a NOR cell type EEPROM.

FIG. 17 is a diagram showing a flowchart showing an algorithm at the time of erasing data in the fourth embodiment.

FIG. 18 is a diagram showing a configuration of a bit line control circuit according to a fourth embodiment.

FIG. 19 is a timing chart of a data read operation according to the fourth embodiment.

FIG. 20 shows an erase pulse application operation in the fourth embodiment /
Erase verify read operation timing chart.

FIG. 21 is an equivalent circuit diagram of a memory cell array in a DINOR cell type EEPROM.

FIG. 22 is an equivalent circuit diagram of a memory cell array in an AND cell type EEPROM.

FIG. 23: NOR cell type EEPROM with select transistor
The equivalent circuit diagram of the memory cell array in M.

FIG. 24 is a timing diagram of a write pulse application operation / write verify read operation in the first conventional example.

FIG. 25 is a diagram showing a configuration of a bit line control circuit according to a second conventional example.

FIG. 26 is an erase pulse application operation in the second conventional example /
Erase verify read operation timing chart.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Bit line control circuit 3 ... Column decoder 4 ... Address buffer 5 ... Row decoder 6 ... Data input / output buffer 7 ... Substrate bias circuit 8 ... High-voltage generation circuit 9 ... Intermediate voltage generation circuit FF, FF2 ... Flip-flop The

Claims (4)

[Claims] 1. A memory cell array in which memory cells or memory cell units having a plurality of connected memory cells are arranged in an array, column selecting means for selecting bit lines of the memory cell array, and bit line direction of the memory cell array. A data latch / sense amplifier which is provided at one end of the memory cell for performing a sense operation and a latch operation of rewrite data, a first operation for applying a voltage for data rewrite to a selected memory cell, and the application of the voltage A second operation for inspecting the data rewriting state of the memory cell, and an operation sequence in which the first operation and the second operation are alternately repeated to rewrite the data in the memory cell; And a means for automatically setting rewriting data in the following first operation bit by bit. The amplifier is a CMOS flip-flop, one node of which is connected to the bit line through the transfer gate, and after the first operation, all the bit lines are not set to the first voltage all at once, A nonvolatile semiconductor memory device characterized by being selected and performing a second operation. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the first voltage is a voltage between 0V and Vcc. 3. The non-volatile semiconductor memory device according to claim 1, wherein the first voltage is 0 V or Vcc. 4. The memory cell unit comprises a NAND cell formed by connecting a plurality of memory cells in series, or an AND cell or a DINO formed by connecting a plurality of memory cells in parallel.
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is an R cell.