CN101071640B - Methods of Verifying Flash Memory Devices - Google Patents

Abstract

A method of verifying a flash memory device, comprising: discharging memory cell strings respectively connected to even bit lines and odd bit lines; then, applying a voltage to the memory cell strings respectively connected to even bit lines and odd bit lines, thereby to memory cell strings are precharged; memory cell strings connected to even bit lines are verified as erased by sensing the state of each memory cell string connected to the even bit lines; and memory cell strings connected to odd bit lines are verified as erased; The state of the memory cell strings is sensed to verify that each memory cell string connected to an odd bit line is erased.

Description

Methods of Verifying Flash Memory Devices

technical field

This patent generally relates to a flash memory device, and more particularly, to a method of verifying a flash memory device using a page buffer, in which the verification time for programming or erasing can be reduced and the total driving time can be shortened.

Background technique

In recent years, demand has increased for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function of rewriting data every once in a while. In addition, in order to develop a memory device having a large capacity capable of storing a large amount of data, a high integration technology of memory cells has been developed.

To increase the integration of memory cells, a NAND flash memory device may have multiple cells that are connected in series to form one string and two strings that share a contact. In a NAND flash memory device, programming and erasing are performed by controlling a threshold voltage of a memory cell while injecting electrons into a floating gate by F-N tunneling and releasing electrons from the floating gate.

Therefore, the erased cell has a negative threshold voltage due to the discharge of electrons of the floating gate from the erased cell. A programmed cell has a positive threshold voltage due to the injection of electrons into the floating gate of the programmed cell. However, in the case of NAND flash memory devices, failures may occur due to charge gain or charge loss. Some validation can be performed with respect to these properties. In order to verify that programming and erasing have been performed normally, the page buffer is used.

The page buffer is used to receive a large amount of data from the I/O pad and supply the received data to the memory unit or store the data of the memory unit and then output the stored data. In the past, the page buffer consisted of a single register to temporarily store data. Now, the page buffer includes double registers in order to increase the speed of programming when programming large-capacity data in the NAND flash memory device.

In order to perform erase verification on a NAND flash memory device having a page buffer of a double register structure, a column scan method is used to determine whether all cells are turned on by applying a voltage of 0V to all word lines. In this column scan method, a failure is determined if a cell is turned off.

For erase verification, erase verification is performed on a selected bit line through three steps including precharge, evaluation, and sensing in the same manner as a normal read operation. In the column scan method described above, erasure verification is realized by dividing bit lines into even bit lines and odd bit lines. Accordingly, after the even bit lines are verified, the odd bit lines are verified. Therefore, it is determined whether erasure has been performed by two verification processes. This results in long erase verification times.

Meanwhile, in a multi-level cell, the threshold voltage distribution of erased cells has an influence on the threshold voltage of programmed cells. Therefore, a post program is executed on the erased cells. The post procedure is performed by adopting the ISPP method and the erasure verification is performed after the post procedure. Therefore, if the erase verification time becomes longer, the total erase time is extended.

Also, at the time of programming, the program verification time is extended in the same manner as above. Therefore, the total programming time becomes longer.

Contents of the invention

Therefore, this patent solves the above-mentioned problems and discloses a method of verifying a flash memory device in which the verification time can be shortened and the total driving time can be shortened.

This patent also discloses a method of verifying a flash memory device, in which even and odd bit lines are precharged and evaluated simultaneously, and then sensed sequentially, thereby reducing verification time.

This patent also discloses a method of verifying a flash memory device by simultaneously precharging and estimating even and odd bit lines and then sequentially sensing even and odd bit lines, compared to the prior art The verification time can be cut in half compared to the present method, and thus the total drive time can be reduced by 2/3 compared to the prior art.

According to an aspect of the present invention, there is provided a method for verifying a flash memory device, comprising the steps of: discharging memory cell strings respectively connected to even bit lines and odd bit lines; each memory cell string on the line, thereby precharging the memory cell string; verifying whether the memory cell string connected to the even bit line has been erased by sensing the state of the memory cell string connected to the even bit line ; and verify whether the memory cell string connected to the odd bit line has been erased by sensing the state of the memory cell string connected to the odd bit line.

Also described in this patent is a method of verifying a flash memory device comprising: discharging memory cell strings respectively connected to even and odd bit lines; applying voltages to memory cell strings respectively connected to even and odd bit lines cell strings, thereby precharging the memory cell strings; verifying whether the memory cell strings connected to the even bit lines have been programmed by sensing the state of the memory cell strings connected to the even bit lines; The state of the memory cell strings of the bit lines is sensed to verify whether the memory cell strings connected to the odd bit lines have been programmed.

This patent also describes a method of verifying a flash memory device, wherein the flash memory device includes: a first transistor for supplying a verification signal to a memory cell array through an even bit line and an odd bit line in response to a first control signal; a transistor for connecting the memory cell array and the first node through an even bit line and an odd bit line in response to a second control signal; a third transistor for supplying a current to the first node in response to a third control signal; a latch , for storing output data from selected cells of the memory cell array; and a fourth transistor, for controlling the state of the latch according to the voltage level of the first node and the fourth control signal. The method includes: discharging memory cell strings respectively connected to even and odd bit lines in response to a first control signal, and at the same time, supplying a voltage to the first node in response to a third control signal, and at the same time, responding to the first voltage The second control signal of the level supplies the voltage of the first node to the memory cell strings respectively connected to the even bit lines and the odd bit lines, thereby precharging the memory cell strings; in response to the second control signal of the second voltage level by Storing the states of the memory cell strings connected to the even bit lines to verify whether the memory cell strings connected to the even bit lines have been erased; The state of the memory cell strings is used to verify whether the memory cell strings connected to the odd bit lines have been erased.

The first control signal may maintain a voltage level of 1.6 to 5.5V or a power supply voltage Vcc.

The second control signal of the first voltage level can be maintained at a voltage level of 1.0 to 5.5V or the power supply voltage Vcc, and the second control signal of the second voltage level and the third voltage level can be maintained at a voltage of 1.0 to 2.2V level, and the second voltage level may be maintained at the same or higher voltage level as the first voltage level.

The application time of the second control signal of the second voltage level may be set to be longer than the application time of the second control signal of the third voltage level.

Description of drawings

1 is a circuit diagram of a page buffer used in a method for verifying a NAND flash memory device according to an embodiment of the present invention; and

FIG. 2 is an operation waveform of a page buffer for illustrating a method of verifying a NAND flash memory device according to an embodiment of the present invention.

Detailed ways

Embodiments according to this patent will now be described with reference to the accompanying drawings. Since these embodiments are provided for those skilled in the art to understand this patent, they can be modified in various ways and the scope of this patent is not limited by each embodiment described later.

FIG. 1 is a circuit diagram of a page buffer used in a method of verifying a NAND flash memory device according to an embodiment of the present invention. FIG. 1 shows a circuit diagram of a main register in a page buffer having a dual register structure of a main register and a cache register.

Referring to FIG. 1, the bit line selection unit 120 includes a plurality of transistors. The first and second NMOS transistors N101 and N102 are driven in response to the even and odd discharge signals DISCHe and DISCHo, respectively, and correspondingly apply the verification voltage VIRPWR to the memory cell array 110 connected to the even bit line BLe or the odd bit line BLo. string of memory cells. The third and fourth NMOS transistors N103 and N104 are driven in response to the even and odd bit line selection signals BSLe and BSLo, respectively, and connect the bit lines of the memory cell array 110 and the sense node SO accordingly.

The PMOS transistor P101 is driven in response to the precharge signal PRECHb, thereby applying a voltage to the sense node SO.

During the copy-back process, the fifth NMOS transistor 105 is connected to the sense node SO and the output node QAb of the latch 130 in response to the copy-back signal COPYBACK. The latch 130 temporarily stores output data output from the memory cell array 110 and externally supplied data. The sixth NMOS transistor N106 is driven according to the voltage level of the sensing node SO. The seventh NMOS transistor N107 is driven in response to the read signal READ_L, and thus connects the output node QAb of the latch 130 and the ground terminal Vss.

The eighth NMOS transistor N108 is driven in response to the signal DI_L, and thus connects the I/O terminal YA and the output node QAb of the latch 130 . The ninth NMOS transistor N109 is driven in response to the signal nDI_L, and thus connects the I/O terminal YA and the input node QA of the latch 130 . The tenth NMOS transistor N110 is driven in response to a reset signal RESET_L and thus resets the latch 130 . The eleventh NMOS transistor N111 is driven in response to the signal PROGRAM_L in a program operation, and thus transmits information to be programmed to a selected bit line.

The twelfth NMOS transistor N112 is driven in response to the signal PBDO_L and thus outputs the voltage level of the program node NA. In addition, the inverter I101 inverts the voltage level of the output node QAb of the latch 130 and transmits the inverted voltage level to the program node NA.

FIG. 2 is an operation waveform of a page buffer for illustrating a method for verifying a NAND flash memory device according to an embodiment of the present invention. An erasure verification method for a NAND flash memory device according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2 .

1) Period A: discharge

During the same period, the even and odd discharge signals DISCHe and DISCHo of a high level of 1.6V to 5.5V or the power supply voltage Vcc are simultaneously applied, thereby turning on the first and second NMOS transistors N101 and N102 . Accordingly, the voltage level of the verification signal VIRPWR is supplied to the bit lines BLe and BLo through the first and second NMOS transistors N101 and N102. The verification signal VIRPWR maintains a voltage level of 0V at the time of erase verification. Therefore, the even and odd bit lines BLe and BLo are applied with a voltage of 0V. In addition, the reset signal RESET_L is applied as a pulse of a high level, thereby turning on the tenth NMOS transistor N110. Therefore, node QA becomes low level and node QAb maintains high level. As a result, latch 130 is reset. At this time, all the word lines WL0 to WL31 are applied with a voltage of 0 to 1V, and the drain selection line DSL and the source selection line SSL are also applied with a voltage of 0V.

2) Period B: pre-charging

When the even and odd discharge signals DISCHe and DISCHo are applied at a low level, the first and second NMOS transistors N101 and N102 are turned off. In addition, since the precharge signal PRECHb is applied to a low level, the first PMOS transistor P101 is turned on. Accordingly, the power supply voltage Vcc is applied to the sensing node SO such that the sensing node SO maintains a high level. In addition, the even and odd bit line selection signals BSLe and BSLo are applied at a voltage level of 1.0 to 5.5V or a first voltage V1 approximately of a power supply voltage Vcc. Accordingly, the even and odd bit lines BLe and BLo are respectively applied with the first voltage V1 and the voltage (V1-Vt) in which the threshold voltage Vt of the third or fourth NMOS transistor N103 or N104 is subtracted from the first voltage V1. In this case, a voltage is applied to the drain select line DSL.

3) Period C: Estimation

Since the even and odd bit line selection signals BSLe and BSLo are applied to a low level, the third and fourth NMOS transistors N103 and N104 are turned off. Accordingly, power supply to the even and odd bit lines BLe and BLo is stopped, and the voltage levels of the even and odd bit lines BLe and BLo are respectively controlled according to states of memory cells connected to the even and odd bit lines BLe and BLo. That is, if the memory cell is not in the erased state, the voltage level of the even or odd bit line BLe or BLo remains at the voltage level of V1-Vt. However, if the memory cell is in an erased state, the voltage levels of the even or odd bit lines BLe and BLo gradually decrease from V1-Vt and then remain at a low level. At this time, since the first PMOS transistor P101 is kept turned on by the precharge signal PRECHb of a low level, the sensing node SO maintains a high level. At the same time, a high-level signal is applied through the drain selection line DSL and the source selection line SSL. The cell evaluation period is set to hold for 10 μs or less.

4) Period D: even cell sensing

Since the precharge signal PRECHb is applied to a high level, the first PMOS transistor P101 is turned off. Since the even bit line selection signal BSLe is applied as the second voltage V2 maintaining a voltage level of about 1.0 to 2.2V, the third NMOS transistor N103 is turned on. If the memory cell is not an erased cell, the voltage level of the even bit line BLe is maintained at a voltage level of V1-Vt, and the voltage level of the sense node SO is maintained at a high level. If the memory cell is not an erased cell, the voltage level of the even bit line Ble remains at the voltage level of V1-Vt and the voltage level of the sensing node SO remains at the high level. If the memory cell is in an erased state, the voltage level of the even bit line Ble gradually decreases and then remains at a low level. In this state, if the read signal READ_L is applied as a high level pulse of 1.0 to 10 μs, the sense node SO remains at a high level when the memory cell is not an erased cell. Therefore, in response to the read signal READ_L of the high pulse, the sixth NMOS transistor N106 is turned on and the seventh NMOS transistor N107 is turned on. As a result, node QAb remains at low level and node QA remains at high level. On the contrary, if the memory cell is an erased cell, the sense node SO remains at a low level and the seventh NMOS transistor N107 is turned off. Therefore, node QAb is held at high level and node QA is held at low level. Therefore, the voltage level of the node QA is detected in order to sense the state of the even-numbered cells.

5) Period E: odd cell sensing

Since the even bit line selection signal BSLe is applied to a low level, the third NMOS transistor N103 is turned off. Since the odd bit line selection signal BSLo is applied as the third voltage V3 maintained to a voltage level of about 1.0 to 2.2V, the fourth NMOS transistor N104 is turned on. It is required that the third voltage V3 is less than or equal to the second voltage V2 and the application time of the third voltage V3 is shorter than the application time of the second voltage V2. If the memory cell is not an erased cell, the voltage level of the odd bit line BLo is maintained at a voltage level of V1-Vt, and the voltage level of the sense node SO is maintained at a high level.

However, if the memory cell is in an erased state, the voltage level of the odd bit line BLo gradually decreases and then remains at a low level, and the voltage level of the sense node SO remains at a low level. In this state, the read signal READ_L is applied as a 1.0 to 10 μs high-level pulse. If the memory cell is not in the erased unit, the sense node SO remains at a high level. Therefore, in response to the read signal READ_L of the high pulse, the sixth NMOS transistor N106 is turned on and the seventh NMOS transistor N107 is turned on. Since node QAb remains at low level, node QA remains at high level. On the contrary, if the memory cell is an erased cell, the sense node SO remains at a low level, and the seventh NMOS transistor N107 is turned off. Therefore, node QAb remains at high level and node QA remains at low level. Therefore, the voltage level of node QA is detected in order to sense the state of odd cells.

The erasure verification method of the NAND flash memory device according to the embodiment of the present invention has been described above. However, this method can be applied to the program verification method in the same manner. Therefore, a detailed description of this method is omitted.

As described above, the even and odd bit lines are precharged and evaluated simultaneously and then sensed sequentially. Therefore, the erase verification time can be reduced by at most half compared with the prior art, and the total erase time can be reduced by 2/3 compared with the prior art. Therefore, the operating speed of the device can be increased. In addition, the present invention can be applied to program verification in the same manner. Programming times can thus also be reduced.

Although the foregoing description has been made with respect to various embodiments, it should be understood that changes and modifications to this patent can be made by those skilled in the art without departing from the spirit and scope of this patent and the appended claims.

Description of main component symbols

110 memory cell array

120 bit line selection unit

130 latches

Ble even bit line

Blo Odd Bit Line BLo

BSLe even bit line selection signal

BSLo odd bit line select signal

COPYBACK back copy signal

DI_L signal

DISChe even discharge signal

DISCHo odd discharge signal

DSL Drain Select Line

I101 Inverter

N101 first NMOS transistor

N102 second NMOS transistor

N103 third NMOS transistor

N104 fourth NMOS transistor

N105th NMOS transistor

N106 sixth NMOS transistor

N107 seventh NMOS transistor

N108 eighth NMOS transistor

N109 ninth NMOS transistor

N110 tenth NMOS transistor

N111 eleventh NMOS transistor

N112 Twelfth NMOS transistor

NA programming node

nDI_L signal

P101PMOS transistor

P201 first PMOS transistor

PRECHb precharge signal

PROGRAM_L signal

QA input node

QAb output node

READ_L read signal

RESET_L reset signal

SO sensing node

SSL source select line

V1 first voltage

V2 second voltage

V3 third voltage

Vcc supply voltage

VIRPWR verification signal

Vss ground terminal

Vt threshold voltage

WL0-WL31 word line

YA I/O terminal

Claims (9)

1. A method of verifying a flash memory device, comprising: discharging the strings of memory cells respectively connected to the even and odd bit lines; applying a voltage to the strings of memory cells respectively connected to the even bit lines and the odd bit lines, thereby precharging the strings of memory cells; verifying whether each memory cell string connected to the even bit line has been erased by sensing the state of the memory cell string connected to the even bit line; Whether each string of memory cells connected to the odd bit line has been erased is verified by sensing the state of the string of memory cells connected to the odd bit line. 2. A method for verifying a flash memory device, said flash memory device comprising: a first transistor for supplying a verification signal to the memory cell array through even and odd bit lines in response to a first control signal; a second transistor for connecting the memory cell array and the first node through the even and odd bit lines in response to a second control signal; a third transistor for supplying current to the first node in response to a third control signal; a latch for storing output data from selected cells of said memory cell array; a fourth transistor, configured to control the state of the latch according to the voltage level of the first node and a fourth control signal, The methods include: discharging strings of memory cells respectively connected to the even bit lines and the odd bit lines in response to the first control signal; supplying a voltage to the first node in response to the third control signal, and simultaneously supplying the voltage of the first node to the even nodes connected respectively in response to the second control signal of the first voltage level. bit lines and the memory cell strings of the odd bit lines, thereby precharging the memory cell strings; verifying whether each string of memory cells connected to the even bit line has been erased by storing a state of each string of memory cells connected to the even bit line in response to the second control signal at a second voltage level except; and verifying whether each string of memory cells connected to the odd bit line has been erased by storing a state of each string of memory cells connected to the odd bit line in response to the second control signal at a third voltage level . 3. The method of claim 2, wherein the first control signal is maintained at a voltage level of 1.6 to 5.5V or at a voltage level of a power supply voltage Vcc. 4. The method of claim 2, wherein said second control signal of said first voltage level is maintained at a voltage level of 1.0 to 5.5V or at a supply voltage Vcc. 5. The method of claim 2, wherein said second control signal of said second voltage level is maintained at a voltage level of 1.0 to 2.2V. 6. The method of claim 2, wherein said second control signal of said third voltage level is maintained at a voltage level of 1.0 to 2.2V. 7. The method of claim 2, wherein the second voltage level is maintained at a voltage level greater than or equal to the third voltage level. 8. The method of claim 2, wherein an application time of the second control signal of the second voltage level is set to be longer than an application time of the second control signal of the third voltage level. 9. A method of verifying a flash memory device comprising: discharging the strings of memory cells respectively connected to the even and odd bit lines; applying a voltage to each string of memory cells respectively connected to the even and odd bit lines, thereby precharging the strings of memory cells; verifying whether each string of memory cells connected to the even bit line has been programmed by sensing a state of each string of memory cells connected to the even bit line; and Whether each string of memory cells connected to the odd bit line has been programmed is verified by sensing the state of each string of memory cells connected to the odd bit line.

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