JPH0961409A - Ultrasonic signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the ratio of the signal and noise of receiving signal by a means integrating the receiving signal rotated in phase and a means setting the integrated signal to a single frequency band. SOLUTION: Adders 161-16p add mutual receiving signals of the phase correction values to output receiving signals to phase rotation circuits 171-17p and the circuits 171-17p output real components 171i-17pi to an adder 181 and imapinary parts 171q-17pq to an adder 182. A band-pass circuit 190 sets the complex signal outputs of the adders 181-182 to the single signal band on the complex frequency space. In order to obtain the envelop signal of phasing adding output, a circuit operating the sum square root of the outputs I, Q of the circuit 190 is connected. By this constitution, the phasing of extremely many parallel receiving signals can be performed with high accuracy inclusive phase connection and an apparatus can be simplified and can be reduced in cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrasonic signal processing device.

[0002]

2. Description of the Related Art There has been proposed an ultrasonic imaging system in water or a living body. In such an apparatus, the method of constructing the reception phasing unit that performs the delay and addition processing of the received signals is the most important in determining the scale of the entire apparatus.
With the rapid development of integrated circuit technology in recent years, the quantized phasing method is becoming the main technique for the phasing section.

As a configuration using digital signal processing technology, quadrature sampling based on a carrier frequency is performed.
ng) and a minute time movement less than the sampling period are approximated by phase rotation of the carrier wave. This phasing method is, for example, “IEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control (IEEE Transaction
s on Ultrasonics, Ferroelectrics, and Frequency Co
ntrol), Vol. 40, No. 3, MAY 1993 ”and the like.

This phasing method will be described with reference to FIG.
The reception signal input 2001 becomes an input to the mixers 2021 and 2022, and sine wave signals 2023 and 2020 whose phases are orthogonal to each other.
Frequency mixing is performed with each of the 24. Due to frequency mixing, the received signal is the envelope signal component (baseband component)
And have harmonic components. The results of the frequency mixing pass through the low-frequency pass filters 2031 and 2032, respectively, and become the signals leaving the envelope signal band near DC, and are input to the samplers 2041 and 2042. Sampler 20
41 and 2042 are analog-digital converters,
Basically, it suffices to operate at a sampling frequency that satisfies the Nyquist condition of the envelope signal band. Sampling digital signals are sequentially stored in the storage circuits 2051 and 2052, and a read address in the storage space is changed according to a necessary time relationship, so that a desired delay is given to a signal having a sampling cycle as a unit. be able to. Storage circuit 205
The signal that has passed through 1,2052 is input to the phase rotation unit 2067.

The phase rotator corrects the phase change of the carrier wave that should be possessed by the envelope signal component of the received signal obtained in complex by complex multiplication, and depends on the received signal carrier wave frequency and the target delay amount which is not quantized. decide. By the reference signals 2065 and 2066 having the phase ψ calculated from the delay amount and the angular frequency of the carrier, the quantization error due to the sampling period of the delay amount is corrected centering on the carrier period. The correction results are added by the adders 2071 and 2072 of the real part and the imaginary part for each receiving element. The addition result is converted into an envelope signal by a square sum square root calculator 2008.

[0006]

If a large number of parallel received signals are to be phased by using the above-mentioned phasing method, the scale of the frequency shift processing section becomes very large. Immediately after each mixer that handles the real and imaginary parts, a low-pass filter and an analog-to-digital converter for the purpose of filtering the double-frequency signal band generated by multiplication are required. Normally, this filter is required to have strict cutoff characteristics and attenuation characteristics in the stopband. Therefore, it is difficult to realize in an ultrasonic reception signal processing device that processes many reception signals in parallel in real time, because the circuit scale increases. there were.

Further, in particular, when it is not necessary to provide the phase rotation section 2067 with the reference signals 2065 and 2066 having high phase accuracy of the phase ψ, a discrete value of the phase ψ can be prepared. At this time, most of the parallel reception signals perform the same phase rotation operation at a specific phase ψ on the basis of the uniformity in a probabilistic sense, so it is not possible to attach a phase rotation unit to all the parallel reception signals. Not desirable.

An object of the present invention is to solve this problem and provide an ultrasonic signal processing apparatus suitable for simplification of the apparatus and cost reduction.

[0009]

As a first means for achieving the above object, the ultrasonic signal processing apparatus of the present invention is
Means for sampling each received signal, means for converting each sampled signal into a different time relationship, means for adding the values of the time-converted signals at the same time, and reception of the addition results individually It includes means for compensating for phase rotation of the carrier wave of the signal, means for integrating the phase-rotated received signals, and means for making the integrated signal a single frequency band. As a second means for achieving the above object, the ultrasonic signal processing device of the present invention is, in the first means, a means for compensating for the phase rotation, a sine function value determined for a set of predetermined phases. And a cosine function value as means for obtaining two outputs by multiplying the addition result of the time-converted signals at the same time, and means for accumulating the phase-rotated received signals is a plurality of the two outputs Are integrated on each side to obtain a pair of outputs.

As a third means for achieving the above object, in the ultrasonic signal processing device of the present invention, in the first means, the means for setting the single frequency band is the carrier frequency of the received signal. A means for performing a complex frequency shift and a filter means for passing a low frequency component of the signal after the frequency shift are provided.

As a fourth means for achieving the above object, in the ultrasonic signal processing device of the present invention, in the first means, the means for setting the single frequency band is positive or negative of the received signal. It has a bandpass filter configuration centered on the carrier frequency of.

As a fifth means for achieving the above object, in the ultrasonic signal processing apparatus of the present invention, in the above first means, the output of the means for sampling each received signal is the carrier frequency of the received signal. The configuration for providing a single frequency band further includes a means for performing complex frequency shift, and a filter configuration for passing a low frequency component of the frequency-shifted signal is provided.

As a sixth means for achieving the above object, in the ultrasonic signal processing apparatus of the present invention, in the above first means, the means for sampling the received signal is four times the carrier wave period of the received signal. The configuration is such that the operation of sampling at a time interval of one-half can be repeated every predetermined period.

As a seventh means for achieving the above object, in the ultrasonic signal processing apparatus of the present invention, in the sixth means, the means for setting the single frequency band is the carrier frequency of the received signal. A means for performing a complex frequency shift and a filter means for passing a low frequency component of the signal after the frequency shift are provided.

As an eighth means for achieving the above object, in the ultrasonic signal processing device of the present invention, in the sixth means, the means for setting the single frequency band is positive or negative for the received signal. Band pass filter means centered on the carrier frequency of

[0016]

According to the first means of the present invention, each received signal is sampled and converted into a different time relationship, and the same time is added to each other, and the addition results are individually compensated for the phase rotation of the carrier wave of the received signal. The time shift of the sampling period or less is realized by the phase rotation of the carrier wave of the received signal, and the means for integrating the phase-rotated received signal and the means for integrating the integrated signal into a single frequency band The signal to noise ratio is improved.

In the second means of the present invention, the first means is
The phase rotation amount of the carrier wave is compensated by multiplying the addition result of the time-converted signals at the same time with the sine function value and cosine function value that are determined for a predetermined set of phases to obtain two outputs. The time shift of less than the sampling period is realized, and the means for integrating the received signals whose phases have been rotated is such that a plurality of the two outputs obtained are integrated one by one to obtain a pair of outputs. Processing as a complex component becomes possible.

In the third means of the present invention, by the second means, a complex frequency shift is performed with a sine wave signal having carrier wave frequencies of mutually orthogonal phases of the received signal, so that the added received signal is a direct current. Is a signal band centered on the above, and a single frequency band can be formed by a filter that passes low frequency components including only this signal band.

In the fourth means of the present invention, the second means is provided with a bandpass filter centering on the positive or negative carrier frequency of the received signal, whereby a single frequency band can be obtained. .

In a fifth means of the present invention, the output of sampling each received signal is subjected to complex frequency shift by the carrier frequency of the received signal by the above first means, and the frequency-shifted signal is moved. A single frequency band is obtained by finally providing a filter for passing the low frequency component of.

In a sixth means of the present invention, the means for sampling the received signal according to the above-mentioned first means performs an operation of sampling at a time interval of a quarter of the carrier wave cycle of the received signal for a predetermined period. By the operation repeated every time, it means that the signals in which the phase of the carrier wave is different by 90 degrees are approximately sampled.

In the seventh means of the present invention, the added reception signal is converted into a direct current by performing a complex frequency shift by a sinusoidal signal having carrier wave frequencies of mutually orthogonal phases of the reception signal in the sixth means. Is a signal band centered on the above, and a single frequency band can be formed by a filter that passes low frequency components including only this signal band.

In the eighth means of the present invention, a single frequency band can be obtained by providing a bandpass filter centering on the positive or negative carrier frequency of the received signal in the sixth means. .

[0024]

[Embodiment] Rc (t) is a signal received by an element which is a reference for phasing.
And is represented by the equation 1.

[0025]

## EQU1 ## Rc (t) = A (t) cos (ωs t) (Equation 1) where ωs is the angular frequency of the carrier and A (t) is the envelope waveform.

In the phasing, it is assumed that the received signals of the respective elements are signals which differ only in the time t of the equation 1. Let Ru (t) be the received signal of the u-th element, which has a delay time τu to be given in phasing. Ru (t) can be expressed as in Equation 2.

[0027]

## EQU00002 ## Ru (t) = A (t + .tau.u) cos (.omega.s (t + .tau.u)) = A (t + .tau.u) [exp {j.omega.s (t + .tau.u)} + exp {-j.omega.s (t + .tau.u)}] (Equation 2) where j Is an imaginary unit. Quantization delay unit for digital processing is Ts, G is an integer, and τu = G ·
It is assumed that Ts + εu, 0 ≦ εu <Ts.

The waveform Du (t) obtained as a result of applying the quantization delay G · Ts to Equation 2 can be expressed by Equation 3.

[0029]

## EQU00003 ## Du (t) = Ru (t−G · Ts) = A (t + τu−G · Ts) [exp {jωs (t + τu−G · Ts)} + exp {−jωs (t + τu−G · Ts)} ] = A (t + εu) [exp {jωs (t + εu)} + exp {-jωs (t + εu)}] (Equation 3) The result B given the phase correction exp (-jωs εu)
u (t) can be expressed by Equation 4.

[0030]

Bu (t) = Bu (t) exp (−jωs εu) = A (t + εu) [exp {jωs (t + εu)} + exp {−jωs (t + εu)}] exp (−jωs εu) = A ( t + εu) exp {jωs t} + A (t + εu) exp {-jωs (t + 2εu)} (Equation 4) If the second term of Equation 4 is sufficiently attenuated by the complex bandpass filter, only the time error is generated in the envelope. Phased waveform P with
(t) is obtained. If the impulse response of such a bandpass filter is H (t), and its group delay is δ and * is a convolution operation, then P (t) is approximately given by Equation 5.

[0031]

## EQU00005 ## P (t) = Bu (t) * H (t) .apprxeq.A (t + .epsilon.u-.delta.) Exp {j.omega.s (t-.delta.)} (Equation 5) where .delta. Is common to all received signals. There is no problem in the phasing addition result because it remains. Alternatively, a method may be used in which the second term of Equation 4 is complexly frequency-shifted to be converted into a baseband and then sufficiently attenuated using a low-pass filter. In this case, E (t) is obtained in the envelope having only the time error. If the impulse response of such a low-pass filter is H '(t) and its group delay is δ', E (t) becomes as shown in Equation 6 in the same process.

[0032]

## EQU6 ## E (t) = <Bu (t) exp (-j (ωs t + φ))> * H '(t) = <A (t + εu) exp (-jφ) + A (t + εu) exp {-jωs ( 2t + 2εu + φ)}〉 * H ′ (t) ≈A (t + εu−δ ′) exp (−jφ) (Equation 6) Since δ ′ remains common to all received signals, there is no problem in the phasing addition result. . Further, the same processing can be realized for a signal pair that is delayed by a Hilbert transform or a 90-degree phase difference of carrier waves. Such a signal is a complex signal, and is expressed by Equation 7.

[0033]

## EQU00007 ## R'u (t) = A (t + .tau.u) exp {j.omega.s (t + .tau.u)} (Equation 7) Since such a signal has only a single signal band on the positive and negative frequency axes of the complex, By performing the same processing as in the case of the equations 3 and 4, the target signal B′u as shown in the equation 8 is directly obtained.
(t) is obtained.

[0034]

B′u (t) = R′u (t−G · Ts) exp (−jωs εu) = A (t + τu−G · Ts) exp {jωs (t + τu−G · Ts)} exp (− jωs εu) = A (t + εu) exp {jωs (t + εu)} exp (−jωsεu) = A (t + εu) exp (jωst) (Equation 8) Further, the frequency shift process is realized by the process previously performed. You can also Result of complex frequency shift on Ru (t) M
u (t) is shown in Equation 9.

[0035]

[Equation 9] Mu (t) = Ru (t) exp (−j (ωs t + φ)) = A (t + τu) [exp {j (ωsτu−φ)} + exp {−j (ωs (2t + τu) + φ)}] (Equation 9) Waveform D′ u as a result of applying the quantization delay G · Ts to Equation 9
(t) can be expressed by Equation 10.

[0036]

D′ u (t) = Mu (t−G · Ts) = A (t + τu−G · Ts) [exp {j (ωsτu−φ)} + exp {−j (ωs (2 (t−G・ Ts) + τu) + φ)}] = A (t + εu) [exp {j (ωs τu−φ)} + exp {−j (ωs (2 (t−G · Ts) + τu) + φ)}] (Number) 10) The result B′u (t) obtained by applying the phase correction exp (−jωs τu) to this is expressed by the equation 11.

[0037]

B′u (t) = D′ u (t) exp (−jωsτu) = A (t + εu) [exp {j (ωsτu−φ)} + exp {−j (ωs (2 (t− G · Ts) + τu) + φ)}] exp (−jωs τu) = A (t + εu) exp {−jφ} + A (t + εu) exp {−j (ωs (2 (t + εu) + φ)} (Equation 11) Next Then, the second term component of the equation (11) is sufficiently attenuated by using a low-pass filter, and the impulse response of such a low-pass filter is H '(t) and its group delay is δ'.
In the same process, (t) becomes like Equation 12.

[0038]

E ′ (t) = B′u (t) * H ′ (t) = <A (t + εu) exp {−jφ} + A (t + εu) exp {−j (ωs (2 (t + εu) + φ) }〉 * H ′ (t) ≈A (t + εu−δ ′) exp (−jφ) (Equation 12) Here, since δ ′ remains common to all received signals, there is no problem in the phasing addition result.

In each of the above signal processing steps, the phase correction exp (-jωs τu) or exp (-jωs after the quantization delay is performed.
The process of complex multiplication of εu) is the function exp with θ as a real number.
By using the periodicity of (−jθ), it is possible to prepare a value with required angular accuracy. In actual digital signal processing, it is desirable to prepare the value of exp (-jθ) in a table reference format. When the total number of received signals is significantly larger than the size of the value table prepared with the required angle accuracy, exp (-jωs τu) or exp (-jω
It is possible to reduce the scale of the apparatus by providing a complex multiplying means for exp (-jθ) corresponding to each angle value prepared in the table, rather than providing a means for multiplying s εu). Therefore, the signal after the quantization delay is given before the complex multiplication means of exp (−jθ) corresponding to each angle value,
It is possible to efficiently realize phasing addition by once adding all and performing complex multiplication of exp (−jθ) on the addition result and subsequent addition of all elements.

A first embodiment of the present invention is shown in FIG. FIG.
Then, phasing addition is performed based on the signal processing procedure of equations 1 to 6. The reception signal groups S1 to Sn generated by the reception elements 111 to 11n are input to the sampling circuits 121 to 12n.
The sampling circuits 121 to 12n sample each of the reception signal groups S1 to Sn in units of the sampling cycle Ts and serve as inputs to the quantization delay circuit 14. Here, n is the number of receiving elements. The quantizing delay circuit 14 gives a quantizing delay to each received signal in units of the sampling period Ts from the time relationship of each received signal with respect to the target reflected signal. The output of the quantization delay circuit 14 becomes the input of the selector 15. The selector 15 is the quantization delay circuit 14
The output of the above is distributed to the input of the adders 161 to 16p. Here, p is a natural number smaller than n.

The adders 161 to 16p add the received signals having the same phase correction value to each other and output the delayed received signals to the phase rotation circuits 171 to 17p. Hereinafter, the partial SUM including the selector 15 and the adders 161 to 16p will be referred to as a phase distributor. The phase rotation circuits 171 to 17p add their real part (in-phase) component outputs 171i to 17pi to the adder 18
The imaginary part (orthogonal) component outputs 171q to 17pq are output to the adder 182. These added outputs are input to the band pass circuit 190. The band pass circuit 190 is an adder 18
The complex signal outputs of 1,182 are set as a single signal band in the complex frequency space. Envelope signal of phasing addition output (detection signal)
To obtain, a circuit (not shown in FIG. 1) for calculating the square root sum of squares of the outputs I and Q of the bandpass circuit 190 is connected.

Each of the sampling circuits 121 to 12n shown in FIG. 1 is shown in FIG. The received signal Sn is input to the amplifier 21 whose amplification factor is variable with time. The output of the amplifier 21 passes through the anti-aliasing filter 22 whose cutoff frequency is set based on the upper limit of the band of the received signal, and the analog / digital converter 23, which is the input of the analog / digital converter 23, is common to all received signals not shown. The received signal is sampled every sampling period Ts according to the sampling clock signal of. The sampling output becomes a digital signal and becomes the input of the quantization delay circuit 14 of FIG.

The quantization delay circuit 14 of FIG. 1 will be described with reference to FIG. The quantization delay circuit 14 is a storage circuit 321.
.About.32n and address storage circuits 341 to 34n for storing the read addresses. The sampling circuit groups 121 to 121 in FIG.
The outputs 311 to 31n of the 12n are sequentially stored in the storage circuits 321 to 32n sequentially for each sampling period. The storage start is controlled by the write command W. Further, the write address is reset according to the write command W, and is circulated at a predetermined maximum value by a counting circuit attached to the memory circuits 321 to 32n by a clock input (not shown). The delay is realized by making the address at the time of writing the signal different from the address at the time of reading the signal. The read time is controlled by the read commands R1 to Rn, and the read address is AD.
It is specified by R1 to ADRn. Read output 331 to 3
3n is an input to the phase distributor SUM in FIG. Memory circuit 3
21-32n are comprised with RAM, a FIFO memory, etc. The read commands R1 to Rn control the time point when the phasing addition is started, if necessary. Read address signal ADR
1 to ADRn are obtained as read outputs from the address storage circuits 341 to 34n. This reading is controlled by a clear signal CLR designating the start of reading and a read clock RCLK for sequentially increasing the read address. The address storage circuits 341 to 34n are additionally provided with a counting circuit (not shown), and the read addresses in the address storage circuits 341 to 34n are sequentially counted according to the read clock RCLK. The address storage circuits 341 to 34n are composed of ROMs.

The phase distributor SUM of FIG. 1 is shown in FIG. The phase distributor SUM is a unit selector 41 forming the selector 15.
1 to 41n and adders 161 to 16p. The read outputs 331 to 33n in FIG. 3 are the unit selectors 411 to 41n.
Will be input. The unit selectors 411 to 41n output 331 to 33n to the adders individually selected for each received signal. In FIG. 4, the signal 331 is output to the adder 162, 332 is output to the adder 161, and 33n is output to the adder 16p. In addition, different signals may be added to the same adder at the same time because the signals and the adders are associated with each other.

Next, the adder 16p is shown in FIG. The addition inputs ap1 to apn are calculated by the cascade connection of the adders 511 to 51n to obtain the final output 43p.

Next, the phase rotation circuits 171 to 17p shown in FIG. 1 will be described with reference to FIG. FIG. 6 shows 17p. Adder 16
A pair of correction coefficients cosψp, sinψ for the output 43p of p
Multiply p by multipliers 631 and 632. Correction coefficient cos ψ
p and sin ψp are multipliers 6 from the coefficient generation circuits 621 and 622.
It is output to 31, 632, which is configured by a register whose retentive value is rewritable as necessary, or a fixed logic circuit. The multiplication result is that the real part component 17pi is the input of the adder 181 that calculates the sum of the real parts of FIG. 1, and the imaginary part component 17pq is the input of the adder 182 that calculates the sum of the imaginary parts. Becomes

Next, the band pass circuit of FIG. 1 will be described with reference to FIG. The band pass circuit 190 includes the complex frequency shifter 700.
And a filter unit 701. First, number 1 to number 4, number 6
700, 701 when processing in the signal processing process of
Both are used. The complex frequency shifter 700 realizes multiplication of mutually orthogonal reference wave signals and complex numbers. The real part sum output 191 of the adder 181 and the imaginary part sum output 192 of the adder 182 of FIG. 1 are input to the multipliers 721 to 724, respectively.

Reference wave signals cosωst and sinωst having the same frequency as the carrier wave of the received signal are sine wave signal generation circuits 711 and
712. These are realized by sequentially reading the waveform values stored in the ROM. The multiplication result is input to the adders 731 and 732, the real part and the imaginary part are calculated, and the addition result is input to the filter unit 701.

The addition outputs of the adders 731 and 732 are sequentially input to the shift registers SHR1 and SHR2, respectively. The length of the shift register is m. Shift register SHR
1 and SHR2 are stored in the coefficient register MR.
1 and each of the coefficient values held in MR2 and the multiplier 74
1 to 74 m and 751 to 75 m are multiplied, and the adders 761 and 762 add them simultaneously. The shift registers SHR1 and SHR2 sequentially transfer by the transfer clock C4a, and the adders 731 and 732 operate by the addition clock C4b. At this time, the addition clock C4b
The period can be a long period that is an integral multiple of the period of C4a. Each of the coefficient registers MR1 and MR2 has a function VI (t), V that can be expressed as a function of time t.
A value based on Q (t) is retained.

In the signal processing steps of the equations 1 to 4 and 6
(t) and VQ (t) are exactly the same function, and the coefficient register M
The same coefficient value is held in R1 and MR2. An example of VI (t) or VQ (t) is shown at 81 in FIG. This is an impulse time response of a filter characteristic having a rectangular band-pass characteristic in frequency space, truncated at a finite number of points m. This is a sampling function Sin (πt / Tw) / (πt / Tw) determined by an appropriate time period Tw, and an integer d =
Based on −m / 2, −m / 2 + 1,0, m / 2-1 and m / 2 and the sampling period Ts of the sampling circuit of FIG. 2, t = dTs is substituted into the function to obtain the coefficient value 801, It is possible to sequentially obtain 802 to 80 m. In this configuration, the coefficient register M
Since exactly the same coefficients are held in R1 and MR2, M
R1 and MR2 can be commonly used.

Furthermore, in the signal processing steps of the equations 1 to 5,
The complex frequency moving unit 700 may be omitted. In this case, the inputs 191 and 192 of FIG. 7 become the sequential inputs of the shift registers SHR1 and SHR2, respectively. The filter unit 701 remains the same, and the coefficient registers MR1 and M
R2 has a real part response function 91 (corresponding to VI (t)) shown in FIG. 9 and an imaginary part response function 1001 (VQ (t) shown in FIG.
Corresponding to the coefficient values 911, 912 to 91m, 1
021, 1022-102m is held. This is calculated by multiplying each of the coefficient groups 801, 802 to 80m in FIG. 8 by the sine waves cosωst and sinωst having the same angular frequency ωs as the received signal carrier, whose phases are orthogonal to each other.

In the signal processing steps of the equations 1 to 5 and the equations 1 to 4 and 6, the output of FIG.
A square sum square root arithmetic circuit as shown in 1 is connected. This is provided in order to obtain the envelope signal of the signal obtained in complex, and removes the phase component of the phasing addition signal. The inputs I and Q are squared by the multipliers 1101 and 1102, respectively, and are input to the adder 1103. The addition result is input to the square root calculator 1104. Square root calculator 110
Reference numeral 4 outputs the function value stored in the ROM (not shown) based on the data value of the addition result.

Another embodiment of the present invention is shown in FIG. FIG.
2, the phasing addition is performed based on the signal processing procedure of the equations 1, 2 and 9 to 12. The reception signal groups S1 to Sn generated by the reception elements 111 to 11n are complex frequency shift circuits 122.
It becomes an input of 1-122n. Complex frequency shift circuit 122
1-122n samples each of the reception signal groups S1 to Sn in units of a sampling period Ts, multiplies each by a reference wave signal whose phase is orthogonal to each other, and has the same carrier and angular frequency. Is the input to the quantization delay circuit 1204. Here, n is the number of receiving elements. Quantization delay circuit 12
Numeral 04 gives each received signal a quantization delay in units of sampling period Ts based on the time relationship of each received signal with respect to the target reflected signal. The output of the quantization delay circuit 1204 is the selector 12
It becomes the input of 05.

The selector 1205 is a quantization delay circuit 1204.
The output of the above is distributed to the inputs of the adders 1261 to 126p.
Here, p is a natural number smaller than n. Adder 126
1-126p are real parts of received signals having the same phase correction value,
The imaginary parts are added independently, and the phase rotation circuits 1271-1 to 127-1 are added.
The delayed reception signal is output to 27p.

The quantization delay circuit 1204 can parallelize the quantization delay circuit 14 of FIG. 1 independently of the real part and the imaginary part. Also,
The part combining the selector 1205 and the adders 1261 to 126p can be realized by parallelizing the phase distributing unit SUM of FIG. 1 independently of the real part and the imaginary part. Phase rotation circuit 1271-12
7p outputs its real part (in-phase) component outputs 1271i to 127pi to the adder 1281, and outputs the imaginary part (quadrature) component output 1271q to.
127 pq is output to the adder 1282. These addition outputs are input to the band pass circuit 1290. The band pass circuit 1290 makes the complex signal outputs of the adders 1281 and 1282 into a single signal band in the complex frequency space. In order to obtain the envelope signal (detection signal) of the phasing addition output, a circuit as shown in FIG. 11 for calculating the square root of the sum of squares of the outputs I and Q of the band pass circuit 1290 is connected.

Complex frequency shift circuits 1221-1 to 1221-1 of FIG.
Each of the 22n is shown in FIG. The reception signal Sn is input to the amplifier 1301 whose amplification factor is variable with time. amplifier
The output of 1301 passes through the anti-aliasing filter 1302 whose cutoff frequency is set based on the upper limit of the band of the received signal, and the analog / digital converter 1303 which is the input of the analog / digital converter 1303 is common to all received signals not shown. The received signal is sampled every sampling period Ts according to the sampling clock signal. The sampling output becomes a digital signal and is input to the multipliers 1341 and 1342. The multipliers 1341 and 1342 are respectively multiplied by sinωct1344 and reference wave signal cosωct1343 having the same angular frequency ωc as the carrier wave of the received signal. The reference wave signals 1343 and 1344 may be common to all received signals. Outputs 1351 and 1352 of the respective multipliers are inputs to the quantization delay circuit 1204 in FIG.

Next, the phase rotation circuits 1271-12 of FIG.
7p will be described with reference to FIG. A description will be given by taking 127p connected to the output of the adder 126p. Adder 12
6p real part output 1400i and imaginary part output 1400q are multiplied by a pair of correction coefficients cos ψp and sin ψp by multipliers 1421 to 1424.
Get on. The correction coefficients cos ψp and sin ψp are output from the coefficient generation circuits 1411 and 1412 to the multipliers 1421 to 1424, which are configured by a register whose retentive value is rewritable or a fixed logic circuit as necessary. The four multiplication results are input to the adder 1431 for the real part component and the adder 1432 for the imaginary part component, and the outputs of these adders are the outputs 127pi and 127pq in FIG.

Further, the bandpass circuit 1290 of FIG. 11 may have the same structure as only the filter unit 701 of FIG. Also,
The coefficient group can be realized by the same one as in FIG.

Yet another embodiment of the present invention is shown in FIG. In FIG. 15, phasing addition is performed based on the signal processing procedure of the equations 7 and 8. The reception signal groups S1 to Sn generated by the reception elements 111 to 11n are secondary sampling circuits 1521 to 152.
It becomes the input of n. Each of the secondary sampling circuits 1521 to 152n is the same as the sampling circuit of FIG. 2, but the sampling cycle required by the sampling clock (sampling command) given to the analog-digital converter 23 is 1 of the carrier wave period. /
The difference is that they are shifted by 4 and overlapped. That is, FIG.
Sampling is performed for each pulse of either one of the sampling clocks SCL1 and SCL2.

This situation will be described with reference to FIG. Now, it is assumed that the frequency of the envelope 1601 is sufficiently lower than the carrier frequency of the received waveform 160. A point group (including a point 1602) indicated by white points on the waveform is sampled in accordance with the sampling clock SCL1 for each sampling period Ts, and a point indicated by a black point (including a point 1603) on the waveform is sampled according to the sampling clock SCL2. The group is sampled. The cycles of the sampling clocks SCL1 and SCL2 are common to Ts, but Tc / 4 (Tc: reception signal carrier wave cycle) between them.
There is a delay. Hereinafter, the signal sampled by the sampling clock SCL1 is treated as the real part component of the received signal, and the signal sampled by the sampling clock SCL2 is treated as the imaginary part component of the received signal. Such an approximation is possible because the frequency of the envelope 1601 is sufficiently lower than the carrier frequency of the received waveform 160, so that the envelope component is approximately time-dependent between sampling points at different times Tc / 4. It utilizes the fact that it does not change dynamically. This is extremely advantageous in that it is possible to simply obtain only one signal band in the frequency space without providing a large-scale circuit such as a Hilbert filter for each received signal.

Each of the reception signal groups S1 to Sn is subjected to complex sampling in the secondary sampling circuits 1521 to 152n in units of the sampling period Ts, and the imaginary part signal is quantized in a state delayed by Tc / 4 from the real part signal. It becomes the input of the digitalization delay circuit 1504. Here, n is the number of receiving elements. The quantization delay circuit 1504 gives a quantization delay to each reception signal in units of the sampling cycle Ts from the time relationship of each reception signal with respect to the target reflected signal. The delay is given for both the real and imaginary signals input in pairs. The output of the quantization delay circuit 1504 becomes the input of the selector 1505. The selector 1505 distributes the output of the quantization delay circuit 1504 to the inputs of the adders 1561 to 156p. Here, p is a natural number smaller than n. The adders 1561 to 156p independently add the received signals having the same phase correction value to each other in the real part and the imaginary part, and output the delayed received signals to the phase rotation circuits 1571 to 157p. From the quantization delay circuit 1504 to the adders 1561 to 15
Up to 6p, sampling clocks SCL1, SCL2
The operation is controlled by a clock pair (not shown) that is delayed. As a result, independent processing for each real part and imaginary part can be performed without duplicating the signal line.

The phase rotation circuits 1571 to 157p add their real part (in-phase) component outputs 1571i to 157pi to the adder 1
581, imaginary part (orthogonal) component outputs 1571q to 157p
q is output in parallel to the adder 1582. Phase rotation circuit 15
After the output from 71 to 157p, the real part and the imaginary part are processed in parallel. These added outputs are input to the band pass circuit 1590. The band pass circuit 1590 includes adders 1581 and 158.
It is used to improve the S / N of the signal by attenuating the frequency component of the part other than the single signal band in the complex frequency space by the output of the complex signal of 2, but it may be omitted according to the purpose. To obtain the envelope signal (detection signal) of the phasing addition output,
A circuit as shown in FIG. 11 for calculating a complex signal output of the adders 1581 and 1582 or a square root sum of squares of outputs I and Q of the band pass circuit 1290 is connected.

Next, the phase rotation circuits 1571 to 1571 shown in FIG.
7p will be described with reference to FIG. Here, the adder 156
A description will be given by taking 157p connected to the output of p.
The output of the adder 156p becomes the input 170, and the multipliers 1701 and 1702 multiply the pair of correction coefficients cos ψp and sin ψp. The correction coefficients cos ψp and sin ψp are the coefficient generation circuit 1710,
Output from 1720 to multipliers 1701 and 1702, which is composed of a register whose retentive value is rewritable as necessary, or a fixed logic circuit. The input 170 is input first with the real part and then with the imaginary part. As a result, the multipliers 1701 and 1702 output two multiplication results, but the real part of the first 170 and the correction coefficient cos ψp, sin
The product of ψp is held by the latch circuits 1703 and 1704 and is input to the adder 1705 of the real part component and the adder 1706 of the imaginary part component. Latch circuits 1703 and 1704
Detects the rising edge of the clock CK and holds the value.
The outputs of those adders are latch circuits 1707 and 17
It is held at 08. The latch circuits 1707 and 1708 detect the falling edge of the clock CK and hold the value. These outputs are the outputs 157pi and 157pq in FIG. Signal reference points (170, 1703in, 1 in FIG. 17)
The change of data at 704 in, CV, SV, 157 pi, 157 pq) is shown in FIG.

Further, the bandpass circuit 1590 of FIG. 15 may be the same as that of FIG. That is, both the complex frequency moving unit 700 and the filter unit 701 are provided, or the filter unit 701 is provided.
Only equipped. Further, the band pass circuit 1590 may be omitted.

As described in the above embodiment, the phase rotation circuits 171 to 17p, 1271 to 127p, 1571 to 157.
coefficient generating circuits 621, 622, 1411, 1412, 1710, which output correction coefficients cos ψ p, sin ψ p, etc. in p
A part of 1720 can be configured by a register whose holding value is rewritable. Now, assume that there are f phase values ψ prepared based on the required phasing accuracy. Also, 1 <f <p. When the histogram of the number of received signals corresponding to ψ1 to ψf is distributed as shown in the graph of 19a in FIG. 19, adders 161 to 16f, 1261 to 126f, and 1561 to 15 just before the phase correction circuit corresponding to each ψ are distributed.
If all 6f are realized with the same scale and configuration, ψ2 of 19a
It is necessary to have a parallel addition capability adapted to the maximum frequency such as. Rather than such a state in which the frequencies are significantly biased, it is desirable in terms of circuit implementation that the individual parallel addition capabilities are relatively evenly distributed.

Therefore, pf additional phase correction circuits are provided, and the phase values ψf + 1 to ψp thereof are made variable by a rewritable register. As shown in the graph of 19b, ψf +
If 1 = ψf + 2 = ... = ψp = ψ2 and the original integrated amount of ψ2 is distributed, 161 to 16p, 1261 to 126
It is possible to remarkably reduce the parallelism of each adder such as p, 1561 to 156p. Since the state of such a histogram differs at each time point of the received signal, it is necessary to calculate the minimum necessary addition parallelism from the entire phasing condition.

[0067]

According to the present invention, an extremely large number of parallel received signals can be phased with high accuracy including phase correction. As a result, it is possible to provide an ultrasonic signal processing device suitable for simplification of the device and cost reduction.

[Brief description of drawings]

FIG. 1 is a basic block diagram of a first device.

FIG. 2 is a sampling circuit diagram.

FIG. 3 is a quantization delay circuit diagram.

FIG. 4 is a block diagram of a phase distributor.

FIG. 5 is an explanatory diagram of an in-phase adder.

6 is a phase correction circuit diagram of FIG.

FIG. 7 is a block diagram of a bandpass circuit unit.

FIG. 8 is an explanatory diagram of low frequency pass filter coefficients.

FIG. 9 is an explanatory diagram of a real part of a bandpass filter coefficient.

FIG. 10 is an explanatory diagram of an imaginary part of a bandpass filter coefficient.

FIG. 11 is an explanatory diagram of a square sum square root calculation circuit.

FIG. 12 is a basic block diagram of a second device.

13 is a block diagram of the complex frequency shift circuit of FIG.

14 is an explanatory diagram of the phase rotation circuit of FIG.

FIG. 15 is a basic block diagram of a third device.

16 is an explanatory diagram of the secondary sampling in FIG.

17 is a block diagram of the phase rotation circuit of FIG.

18 is an explanatory diagram of data change and operation of the phase rotation circuit of FIG.

FIG. 19 is an explanatory diagram of a partially variable operation of phase correction data.

FIG. 20 is an explanatory diagram of a conventional phase-correction type conventional phasing technique.

[Explanation of symbols]

111 to 11n ... Receiving element, S1 to Sn ... Received signal group,
121 to 12n ... Sampling circuit, Ts ... Sampling period, 14
... Quantization delay circuit, 15 ... Selector, 161 to 16p ... Adder, 171 to 17p ... Phase rotation circuit, 181, 182
... adder, 190 ... band pass circuit.

Claims (8)

[Claims] 1. An apparatus having a plurality of receiving elements for phasing and adding an ultrasonic signal, means for sampling each received signal,
Means for converting each sampled signal into a different time relationship, means for adding the values of the time-converted signals at the same time, and means for individually compensating the phase rotation of the carrier wave of the received signal of the addition results. An ultrasonic signal processing apparatus comprising: means for accumulating phase-rotated received signals; and means for allowing a single frequency band of the integrated signals to pass. 2. The means for compensating for phase rotation according to claim 1, wherein the sine function value and cosine function value determined for a predetermined phase set are added to the result of addition of the time-converted signals at the same time. An ultrasonic signal processing apparatus, wherein the means for multiplying to obtain two outputs, and the means for integrating the phase-rotated received signals obtains a pair of outputs by integrating the above-mentioned two outputs obtained one by one. 3. The means for passing the single frequency band according to claim 1, wherein the means for performing a complex frequency shift at the carrier frequency of the received signal and the filter for passing a low frequency component of the signal after the frequency shift. An ultrasonic signal processing apparatus including means. 4. The ultrasonic signal processing apparatus according to claim 1, wherein the means for passing the single frequency band includes band-pass filter means centering on a positive or negative carrier frequency of the received signal. 5. The means according to claim 1, further comprising means for performing complex frequency shift of the output of the means for sampling each received signal at the carrier frequency of the received signal, wherein the means for passing the single frequency band comprises: An ultrasonic signal processing apparatus comprising a filter means for passing a low frequency component of a frequency-shifted signal. 6. The means for sampling the received signal according to claim 1, wherein the operation of sampling at a time interval of a quarter of the carrier wave cycle of the received signal can be repeated every predetermined cycle. Ultrasonic signal processing device as means. 7. The means for making the single frequency band according to claim 6, wherein the means for performing a complex frequency shift at the carrier frequency of the received signal and the filter means for passing a low frequency component of the signal after the frequency shift. An ultrasonic signal processing device equipped with. 8. The ultrasonic signal processing apparatus according to claim 6, wherein the means for setting the single frequency band includes band-pass filter means centering on a positive or negative carrier frequency of a received signal.