JPH0945014A - Error correction apparatus for recording/reproducing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To share an error correction device among a recording system and a reproducing system and reduce costs when four errors of a C2 system at most are erased/corrected, by using a double Reed-Solomon code. SOLUTION: A circuit for correcting errors of signal inputs through an input/ output terminal 1 is roughly divided to a syndrome operation block 22, a latch block 23 and a correction block 26. These blocks are controlled by an address block 24 and an instruction block 25. While an error correction process at the recording time and an error correction process at the reproducing time are carried out, a program of the same software is executed for common parts in the processes and jumped for different parts if necessary. At the recording time, a position detection operation at the reproducing time to detect a position of an error is replaced with a position-setting operation to set a position of a parity, thereby to calculate a parity, and moreover errors up to the maximum of 4 are erased/corrected during a C2 sequence error correction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device using a double Reed-Solomon code, and more particularly to an MD.
The present invention relates to an error correction device suitable for reproducing an audio signal recorded on a (mini disc) or recording on the MD.

[0002]

2. Description of the Related Art Generally, in MD, a double Reed-Solomon (RS) code mainly consisting of a C1 sequence for random error correction and a C2 sequence mainly for burst error correction is cross-interleaved. The MD C1 series is composed of 32 words W0 to W31, and the C2 series is composed of 28 words W0 to W27. Further, the parity of MD is 4 words for both C1 and C2 series, and the erasure correction for the C2 series during the recording mode and the reproduction is up to 4 erasure correction.

In error correction during MD reproduction, the C1 series is first corrected, and in this C1 correction, 1 error correction, 2 error corrections and 3 or more error detections are performed. A C1 flag (C1F = F) indicating "no error correction", "1 error correction", "2 error correction", and "3 or more errors not corrected" as a pointer
0, F1, F2) is set, and this C1 flag C1F is used as information indicating an error position in C2 correction.

[0004]

[Table 1]

In the C2 correction, when the error position is known by the C1 correction, that is, 28 in the C2 series.
When it is known which of the words W0 to W27 is in error, the error is corrected, so-called erasure correction is performed. Here, 28 words W0 of C2 series
Since W27 belongs to any block in the C1 series, in erasure correction, for each word of the C2 series, the C of the block of the C1 series to which the word belongs
The 1 flag C1F is read to perform 1 error correction, 2 error correction, and detection of 3 or more errors. Subsequently, the position of the C1 flag C1F is regarded as an error position, and erasure correction of up to 4 words is performed. If the position cannot be corrected, the interpolation flag is set.

Further, at the time of recording, parity calculation is performed for each series of C1 and C2 according to a predetermined flow. Since this operation is different from the error correction during playback described above,
In a recording / reproducing apparatus having a recording unit and a reproducing unit, the recording system and the reproducing system were separate and independent in terms of hardware and software.

[0007]

In such a conventional recording / reproducing error correction device for MD, the error correcting process using the Reed-Solomon code in the recording unit and the reproducing unit is independently performed. Both hardware and software are prepared separately. Therefore, the number of parts is large, space is required, and parts cost, assembly cost, software creation cost, etc. are high.

Therefore, the present invention uses C2, such as MD.
To provide a recording / reproducing error correction device capable of reducing the number of parts, saving space, and reducing various manufacturing costs when performing erasure correction of up to 4 at the time of series error correction. With the goal.

[0009]

In order to achieve the above-mentioned object, the present invention executes the same software program in the steps of the error correction processing during recording and the error correction processing during reproduction. However, when different from each other, a jump is made as necessary, and at the time of recording, the error position detecting operation at the time of reproduction is replaced with the position detecting operation of the parity to perform parity calculation, and at the time of C2 error correction, a maximum of 4 I am trying to correct the erasure up to.

That is, according to the present invention, the C1 series and the C2 series are
An error correction device for recording / reproduction, which employs a double Reed-Solomon code of a series, comprising: a mode discriminating means for discriminating between a recording mode and a reproducing mode; Means for detecting the position of the error and correcting the error, and when the mode determining means determines the recording mode, the error position detecting operation in the error correcting means is replaced with the parity position setting operation. And a means for performing error correction, wherein the means for performing error correction corrects an error in each block of the C1 series and stores an error flag for each block, and the C1 series error correction means. The error flag corresponding to each word of the C2 series stored by is read and the error of each block of the C2 series is read. Recording and reproducing error correction device is provided having a C2 sequence error correcting means for correcting.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a recording / reproducing error correction apparatus of the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram showing an embodiment of an error correction device according to the present invention, FIG. 2 is a flowchart for explaining a routine for correcting a C1 sequence of a Reed-Solomon code, and FIG. 3 is a flowchart for correcting a C2 sequence of a Reed-Solomon code. 6 is a flowchart for explaining a routine to be executed.

First, the circuit shown in FIG. 1 will be briefly described. The circuits 2 to 20 are configured to correct an error of a signal input from the input terminal 1, and a part 2 constituting the error correction circuit. .. to 20 are roughly divided into a syndrome calculation block 22 including circuits 2 to 8, a latch block 23 including circuits 9 to 14 and a correction block 26 including circuits 15 to 20. The blocks 22, 23 and 26 are controlled by an address block 24 and an instruction block 25.

The error flag detection circuit 2 uses C2 during reproduction.
A circuit for evaluating a C1 error flag for erasure correction of a series, reading a C1 error flag corresponding to each word of the C2 series, and detecting a 2-word error of C1 and 3
Detects the position and number of errors of more than word. The circuit 2 also generates and outputs a RAM address for reading the error flag.

The parity location setting circuit 3 outputs the parity position to the location selection circuit 4 in accordance with each sequence of C1 and C2 in order to calculate the parity by using erasure correction during recording. Location selection circuit 4
Selects the error position from the error flag position detection circuit 2 in the reproduction mode, selects the parity position from the parity location setting circuit 3 in the recording mode, and outputs it to the register output selection circuits 9 and 11.

The syndrome check circuit 5 receives data from a RAM (not shown) input from the input terminal 1 and calculates four syndromes S0 to S3 in the C1 series and four in the C2 series, as will be described later. The syndromes Sq0 to Sq3 are calculated and output to the syndrome selection circuit 6. The syndrome selection circuit 6 selects the syndrome from the syndrome selection circuit 6 and the output from the register 19 or 16 and converts it into an α in the table for converting into an exponent.
-I Output to the conversion ROM 7.

The syndrome storage register 8 stores α-i
The conversion ROM 7 stores the α-i converted syndrome, and this register 8 also outputs a flag “1” when all the stored syndromes are “00”. The register output selection circuits 9 and 11 select the syndrome stored in the syndrome storage register 8, the data selected by the location selection circuit 4 and the data stored in the register 14 and output them to the adder circuit 12, and also make corrections. The data symbol address latch circuit 10 stores the error position obtained by the operation when executing the error correction, and outputs it to the RAM address output circuit 24.

The adder circuit 12 is a register output selection circuit 9,
The data selected by 11 is added. Since this addition is addition of the exponent part of α, the instruction is multiplication. The register input / output selection circuit 13 is the addition circuit 1
The output of 2 or the syndrome which is α-i converted by the ROM 7 is selected and stored in the register 14 in the subsequent stage. The register 14 is used to temporarily store the data during the calculation and output it to the register output selection circuits 9 and 11.

The i-α conversion circuit 15 performs an i-α conversion on the output of the adder circuit 12, and this data is added to the data stored in the register 19 by the exclusive OR circuit 17 and stored again in the register 19. It Register 16, Z ² + Z + X = 0 the solution was stored converted by entering a value of "X" in order to obtain the "Z" to the value "Z" is output when two words corrected. The corrected data output circuit 20 outputs the corrected data obtained by the exclusive OR circuit 18 from the data from the i-α conversion circuit 15 and the error data on the data bus onto the data bus.

The RAM address output circuit 24 includes a C1 series RAM address (C1RAMAD), a C1 series error flag RAM address (C1FLGAD), and a C1 series RAM address.
2 series RAM addresses (C2RAMAD) and C2 series error flag RAM addresses (C2FLGAD)
And error flag data of each series (ERFLGBUF)
Is generated and output.

Next, the instruction circuit 25 will be described in detail. First, the clock generator (CLOCKGE).
N) generates various clocks used in this device from each input signal. Instruction counter (I
NSTCNT) is the C1 and C2 syndrome operation and C
This is a 10-bit counter for one error flag evaluation instruction, and the output of this counter is the address of the instruction ROM (INSTROM) 25a. One step of this instruction is from the rising edge of the clock to the rising edge, and is counted up by the clock. The jump of this instruction is performed by loading the following jump destination address into this counter.

The instruction ROM 25a outputs 16-bit data with the count value output from the instruction counter (INSTCNT) as an address, and this data determines the processing operation in each step of the instruction. The instruction selector (INSTSEL) is an instruction ROM 25a.
Output destinations of the 16-bit data output from are distributed according to the type of processing (syndrome calculation, error flag processing, etc.). This output is output at the clock timing. Further, this selector outputs a signal for stopping the instruction when accessing the RAM.

The load address generator (LOADAD) reads the data in which the count value output from the instruction counter (INSTCNT) is latched, and when this data is an address for jumping, determines the jump destination address according to each input condition. Output to the instruction counter (INSTCNT).

Here, although the instruction of the syndrome calculation and the instruction of the correction process are proceeding at the same time, the RAM cannot be accessed at the same time. Therefore, the instruction controller (INSTCONT) monitors the address so that the RAM access does not collide. It controls the instruction counter (INSTCNT). In addition, although the syndrome calculation and the correction process are performed at the same time, since the sequence being corrected is the syndrome one sequence before the syndrome calculation performed at the same time, the flag controller (FLGCONT) stores the information and the flag related to the syndrome calculation. , This information and flags are used in the correction process.

Next, the error correction process and the erasure correction process in FIGS. 2 and 3 will be described. 1. Error correction Error correction is performed on the received data by performing a syndrome operation (hereinafter referred to as syndrome check).
Correcting the position and value of the data based on the result. In this case, one error data has two unknowns (position and value), and since both C1 and C2 sequences have four parities, error correction of up to 2 words is possible. Here, in the MD, the syndromes S0 to S3 of the C1 series and the syndromes Sq0 to Sq of the C2 series.
3 is calculated as in the following equations (Equation 1 and Equation 2).

[0025]

[Equation 1]

[0026]

[Equation 2]

The one-word and two-word error correction will be described below. 1-1.1 Error correction When there is one error, the result of the thin check (S0
S3) is as follows, where Ei is the error magnitude and Xi is the error position. S0 = Ei S1 = Xi * Ei S2 = Xi ² * Ei S3 = Xi ³ * Ei

When Ei and Xi are obtained by using S0 to S3, Xi = S1 / S0 Ei = S0 If an erroneous received data value is Di and a correct data value is Wi.

[0029]

(Equation 3)

The correction process is performed by the data D at the memory address Xi.
i is read and the result of adding Ei is the memory address X
It ends by writing to i. 1-2.2 Error correction The syndrome when there are two errors has Ei and Ej as error magnitudes and Xi and Xj as error positions.

[0031]

(Equation 4)

## EQU1 ## There is also a method of obtaining four unknowns by solving these four simultaneous equations, but here, the equation of the root of the position is introduced to reduce the processing steps. First, the sum and product of error positions are defined.

[0033]

(Equation 5)

These Xi and Xj are the roots of the following equation F (Y).

[0035]

(Equation 6)

Expanding this equation,

[0037]

(Equation 7)

Since it is not possible to refer to the table in this format, if the variable is transformed into Y = C1 * Z, the above equation becomes

[0039]

(Equation 8)

It is possible to obtain Zi by obtaining Z by the contrast ROM 7 of C2 / C1 ² and Z and Xi = C1 * Z Xj = C2 / Xi. Also, C1,
C2 is given as a function of the syndromes S0 to S3.

[0041]

[Equation 9]

In the actual correction work, C1 and C2 are obtained, the result is referred to the control ROM 7, and the reference result is multiplied by C1 to obtain Xi. The error magnitudes Ei and Ej are

[0043]

(Equation 10)

The error correction of 2 words is completed by rewriting the data in the memory based on the above calculation result.

2. Erasure correction Erasure correction is a correction method in which the position of an error is known in advance and only the error value is obtained. In MD, since the number of C2 sequence parities is 4, it is possible to perform erasure correction of a maximum of 4 words. it can. The erasure correction will be described in detail. Now, assuming four errors, the positions of these errors are X1, X2, X3, and X4, and the following calculation is performed.

[0046]

[Equation 11]

The error values corresponding to the error positions X1 to X4 are Y1, Y2, Y3, and Y4. T3 is defined by the following formula.

[0048]

(Equation 12)

Y4 is given by the following equation. Y4 = T3 / I4 With this, the fourth data can be corrected first.
The syndrome is then modified to find Y3 and Y4 is erased from the syndrome.

[0050]

(Equation 13)

From this modified syndrome, T2, Y
Ask for 3.

[0052]

[Equation 14]

Similar processing is performed for Y2.

[0054]

(Equation 15)

Finally, Y1 is calculated.

[0056]

(Equation 16)

With the above, erasure correction of 4 words is completed. Next, the C1 correction process will be described with reference to FIG. When the C1 correction process starts (step S1
01), first, the syndromes S0 to S3 are calculated by the above-mentioned formula (Equation 1) (step S102), and then the syndromes S0 to S3 are converted into α → i and stored in the register 8.

After step S102, it is determined whether the current operation mode is the recording mode (step 103).
This judgment is made by setting a predetermined flag when the recording mode is set by the operation switch of the target MD recording / reproducing apparatus and observing this flag.
If it is not in recording mode, it is regarded as playback mode. That is, all modes other than recording and reproduction such as rewinding are handled as reproduction modes. Step S below
The case in which the reproduction mode is determined in 103 will be described first.

In the reproduction mode, the syndromes S0 to S
It is determined whether all 3 are "0" (step 104), and Y
In the case of ES, "0" is written in each of the C1 error flags F0, F1, and F2 (step S105), and when all blocks are completed, the process proceeds to the C2 correction process shown in FIG. 3 (step S118). On the other hand, when all the syndromes S0 to S3 are not “0” in step S104, first,

[0060]

[Equation 17]

Based on the above, the modified syndromes σ1 to σ3 for detecting the one-word error are calculated (step S1
06) It is determined whether or not there is a one-word error (step S
107). In the case of a 1-word error, the 1-word correction described above is performed and the corrected data is written (step S10).
8) Then, based on Table 1 as well, "1" is written in the C1 error flag F0 (step S109). Next, when all the blocks are completed, the process proceeds to the C2 correction process shown in FIG. 3 (step S118).

On the other hand, if the one-word error is not detected in step S107, X1, X2, and φ1 to φ4 for detecting the two-word error are calculated (step S11).
0), and then it is determined whether or not there is a 2-word error (step S111). In the case of a two-word error, the two-word correction is performed as described above to obtain the corrected data Xi, X.
j is written (step S112), and then "1" is written in the C1 error flag F1 as shown in Table 1 (step S112). Next, when all the blocks are completed, the process proceeds to the C2 correction process shown in FIG. 3 (step S11).
8).

If it is not a 2-word error in step S111, "1" is written in the C1 error flag F2 as shown in Table 1 (step S114), and when all blocks are finished, C2 shown in FIG. Proceed to the correction process (step S118).

If the recording mode is determined in step S103, the parity position (S28 to S31) is loaded (step S115), pre-computation is performed (step S116), and 4 erasure correction is performed (step S1).
17). Next, when all the blocks are completed, the process proceeds to the C2 correction process shown in FIG. 3 (step S118).

Next, the C2 correction process will be described with reference to FIG. This C2 correction processing performs 1 error correction, 2 error correction, and 3 or more error detections. Also, C1
Erasure correction of up to 4 words is performed by regarding the flag position as an error position.

First, the C1 flag is read (step S
122). Here, the C1 flags of F0 and F1 indicate that 1 error correction and 2 error correction were performed in the C1 correction, and the C1 flag of F2 indicates that three or more errors were detected. There is a high probability of erroneously correcting 3 or more errors as 2 errors. Therefore, in the C2 correction, attention is paid to the numbers and positions of the F1 and F2 flags to perform the correction. Next, the syndromes Sq0 to Sq3 described above are calculated (step S122), and the syndromes Sq0 to Sq are calculated.
3 is α → i converted and stored in the register 8.

Then, similarly to the case of C1, it is judged whether or not the recording mode is set (step S124), and if it is the reproduction mode, the process proceeds to step S125 and thereafter. Step S125
In the following, it is determined whether or not the number of errors is "0" by determining whether or not all of the syndromes Sq0 to Sq3 are "0" (step S125), and if "0", the C2 error flags F0, F1, "0" is written in both F2 (step S126), and the C2 correction process is completed (step S127).

On the other hand, when the syndromes Sq0 to Sq3 are not all "0" in step S125, the modified syndromes σ1 to σ for detecting the one-word error.
3 is calculated (step S128), and then it is determined whether there is a one-word error (step S129). And
In the case of a 1-word error, 1-word correction is performed to write the corrected data (step S130), and then "0" is written to the C2 error flags F0, F1, and F2 (step S131), and the C2 correction process is completed (step S131). S127).

On the other hand, if the one-word error is not detected in step S129, the modified syndromes X1, X2, φ1 to φ4 for detecting the two-word error are calculated (step S132), and then it is determined whether or not there is a two-word error. It is determined (step 133). Then, in the case of a 2-word error, 2-word correction is performed to make correction data Xi, Xj.
Is written (step S134), and then "0" is written in the C2 error flags F0, F1, and F2 (step S135), and the C2 correction process is completed (step S1).
27).

If it is not a 2-word error in step S133, a maximum of 4 erasure processes are performed (step S136).
“0” is written in each of the error flags F0, F1, and F2 (step S137 → S138), and the C2 correction process is ended (step S127). In addition, step S137
C2 error flag F if not correctable in
“0”, “1”, “1” or “1” is written to 0, F1, and F2, respectively (step S138), and the C2 correction process ends (step S127).

In the recording mode in step S124, the parity position is loaded (step S14).
0), pre-calculation is performed (step S141), 4 erasure correction is performed, and parity calculation is performed (step S14).
2).

As described above, the reason why the recording mode is different from the reproducing mode is that the parities of the C1 and C2 series must be calculated during recording. Since the position of parity is known in advance, erasure correction is applied and parity calculation is performed instead of error correction. As described above, since the position of the error is unknown during reproduction, the error flag is written by C1 correction,
Although the position of the error was detected by reading it during C2 correction, the position of the parity was known at the time of recording, so that parity calculation can be performed using erasure correction even in the C1 series.

[0073]

As described above, according to the present invention, in the error correction apparatus using the Reed-Solomon code, the step of reading the C1 flag in the reproduction mode so that the processing of both the recording system and the reproduction system can be shared. Alternatively, in the recording mode, the parity position is loaded, and C1, C
Parity calculation is realized by performing both 4 erasure correction. Therefore, the recording system and the reproducing system can share a part of the program with the hardware, and the recording routine can be executed by switching the jump address of the program by switching the mode by providing the same software with a recording subroutine.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a recording / reproducing error correction device according to the present invention.

FIG. 2 is a flowchart illustrating a routine for correcting a C1 sequence of Reed-Solomon code.

FIG. 3 is a flowchart for explaining a routine for correcting a C2 sequence of Reed-Solomon code.

[Explanation of symbols]

 2 flag location circuit 22 syndrome operation block 23 latch block 24 address block 25 instruction block 26 correction block

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 25, 1995

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Title of the invention: Error correction device for recording and reproduction

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device using a double Reed-Solomon code, and more particularly to an MD
The present invention relates to an error correction device suitable for reproducing an audio signal recorded on a (mini disc) or recording on the MD.

[0002]

2. Description of the Related Art Generally, in MD, a double Reed-Solomon (RS) code mainly consisting of a C1 sequence for random error correction and a C2 sequence mainly for burst error correction is cross-interleaved. The MD C1 series is composed of 32 words W0 to W31, and the C2 series is composed of 28 words W0 to W27. Further, the parity of MD is 4 words for both C1 and C2 series, and the erasure correction for the C2 series during the recording mode and the reproduction is up to 4 erasure correction.

In error correction during MD reproduction, the C1 series is first corrected, and in this C1 correction, 1 error correction, 2 error corrections and 3 or more error detections are performed. A C1 flag (C1F = F) indicating "no error correction", "1 error correction", "2 error correction", and "3 or more errors not corrected" as a pointer
0, F1, F2) is set, and this C1 flag C1F is used as information indicating an error position in C2 correction.

[0004]

[Table 1]

In the C2 correction, when the error position is known by the C1 correction, that is, 28 in the C2 series.
When it is known which of the words W0 to W27 is in error, the error is corrected, so-called erasure correction is performed. Here, 28 words W0 of C2 series
Since W27 belongs to any block in the C1 series, in erasure correction, for each word of the C2 series, the C of the block of the C1 series to which the word belongs
The 1 flag C1F is read to perform 1 error correction, 2 error correction, and detection of 3 or more errors. Subsequently, the position of the C1 flag C1F is regarded as an error position, and erasure correction of up to 4 words is performed. If the position cannot be corrected, the interpolation flag is set.

Further, at the time of recording, parity calculation is performed for each series of C1 and C2 according to a predetermined flow. Since this operation is different from the error correction during playback described above,
In a recording / reproducing apparatus having a recording unit and a reproducing unit, the recording system and the reproducing system were separate and independent in terms of hardware and software.

[0007]

In such a conventional recording / reproducing error correction device for MD, the error correcting process using the Reed-Solomon code in the recording unit and the reproducing unit is independently performed. Both hardware and software are prepared separately. Therefore, the number of parts is large, space is required, and parts cost, assembly cost, software creation cost, etc. are high.

Therefore, the present invention uses C2, such as MD.
To provide a recording / reproducing error correction device capable of reducing the number of parts, saving space, and reducing various manufacturing costs when performing erasure correction of up to 4 at the time of series error correction. With the goal.

[0009]

In order to achieve the above-mentioned object, the present invention executes the same software program in the steps of the error correction processing during recording and the error correction processing during reproduction. However, when different from each other, a jump is made as needed, and at the time of recording, the error position detection operation at the time of reproduction is replaced with the parity position setting operation to perform parity calculation, and at the time of C2 series error correction, a maximum of four I am trying to correct the erasure up to.

That is, according to the present invention, the C1 series and the C2 series are
An error correction device for recording / reproduction, which employs a double Reed-Solomon code of a series, comprising: a mode discriminating means for discriminating between a recording mode and a reproducing mode; Means for detecting the position of the error and correcting the error, and when the mode determining means determines the recording mode, the error position detecting operation in the error correcting means is replaced with the parity position setting operation. And a means for performing error correction, wherein the means for performing error correction corrects an error in each block of the C1 series and stores an error flag for each block, and the C1 series error correction means. The error flag corresponding to each word of the C2 series stored by is read and the error of each block of the C2 series is read. Recording and reproducing error correction device is provided having a C2 sequence error correcting means for correcting.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a recording / reproducing error correction apparatus of the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram showing an embodiment of an error correction device according to the present invention, FIG. 2 is a flowchart for explaining a routine for correcting a C1 sequence of a Reed-Solomon code, and FIG. 3 is a flowchart for correcting a C2 sequence of a Reed-Solomon code. 6 is a flowchart for explaining a routine to be executed.

First, the circuit shown in FIG. 1 will be briefly described. The circuits 2 to 20 are configured to correct an error of a signal input from the input / output terminal 1, and a portion configuring the error correction circuit. 2 to 20 are syndrome calculation blocks 22 including circuits 2 to 8, a latch block 23 including circuits 9 to 14 and a correction block 26 including circuits 15 to 20.
It is roughly classified by. The blocks 22, 23 and 26 are controlled by an address block 24 and an instruction block 25.

The error flag detection circuit 2 uses C2 during reproduction.
A circuit for evaluating a C1 error flag for erasure correction of a series, reading a C1 error flag corresponding to each word of the C2 series, and detecting a 2-word error of C1 and 3
Detects the position and number of errors of more than word. The circuit 2 also generates and outputs a RAM address for reading the error flag.

The parity location setting circuit 3 outputs the parity position to the location selection circuit 4 in accordance with each sequence of C1 and C2 in order to calculate the parity by using erasure correction during recording. Location selection circuit 4
Selects the error position from the error flag position detection circuit 2 in the reproduction mode, selects the parity position from the parity location setting circuit 3 in the recording mode, and outputs it to the register output selection circuits 9 and 11.

The syndrome check circuit 5 receives data from a RAM (not shown) input from the input / output terminal 1 and calculates four syndromes S0 to S3 in the C1 series and 4 in the C2 series as described later. Syndrome selection circuit 6 by computing the syndromes Sq0 to Sq3
Output to The syndrome selection circuit 6 receives the syndrome, register 19 or 16 from the syndrome selection circuit 6.
To output to the α-i conversion ROM 7 of a table for converting into an exponent.

The syndrome storage register 8 stores α-i
The conversion ROM 7 stores the α-i converted syndrome, and this register 8 also outputs a flag “1” when all the stored syndromes are “00”. The register output selection circuits 9 and 11 select the syndrome stored in the syndrome storage register 8, the data selected by the location selection circuit 4 and the data stored in the register 14 and output them to the adder circuit 12, and also make corrections. The data symbol address latch circuit 10 stores the error position obtained by the operation when executing the error correction, and outputs it to the RAM address output circuit 24.

The adder circuit 12 is a register output selection circuit 9,
The data selected by 11 is added. Since this addition is addition of the exponent part of α, the instruction is multiplication. The register input / output selection circuit 13 is the addition circuit 1
The output of 2 or the syndrome which is α-i converted by the ROM 7 is selected and stored in the register 14 in the subsequent stage. The register 14 is used to temporarily store the data during the calculation and output it to the register output selection circuits 9 and 11.

The i-α conversion circuit 15 performs an i-α conversion on the output of the adder circuit 12, and this data is added to the data stored in the register 19 by the exclusive OR circuit 17 and stored again in the register 19. It Register 16, Z ² + Z + X = 0 the solution was stored converted by entering a value of "X" in order to obtain the "Z" to the value "Z" is output when two words corrected. The correction data output circuit 20 outputs the correction data obtained by the exclusive OR circuit 18 from the data from the i-α conversion circuit 15 and the error data on the data bus to the data bus and outputs it from the input / output terminal 1. .

The RAM address output circuit 24 includes a C1 series RAM address (C1RAMAD), a C1 series error flag RAM address (C1FLGAD), and a C1 series RAM address.
2 series RAM addresses (C2RAMAD) and C2 series error flag RAM addresses (C2FLGAD)
And error flag data of each series (ERFLGBUF)
Is generated and output.

Next, the instruction circuit 25 will be described in detail. First, the clock generator (CLOCKGE).
N) generates various clocks used in this device from each input signal. Instruction counter (I
NSTCNT) is the C1 and C2 syndrome operation and C
This is a 10-bit counter for one error flag evaluation instruction, and the output of this counter is the address of the instruction ROM (INSTROM) 25a. One step of this instruction is from the rising edge of the clock to the rising edge, and is counted up by the clock. The jump of this instruction is performed by loading the following jump destination address into this counter.

The instruction ROM 25a outputs 16-bit data with the count value output from the instruction counter (INSTCNT) as an address, and this data determines the processing operation in each step of the instruction. The instruction selector (INSTSEL) is an instruction ROM 25a.
Output destinations of the 16-bit data output from are distributed according to the type of processing (syndrome calculation, error flag processing, etc.). This output is output at the clock timing. Further, this selector outputs a signal for stopping the instruction when accessing the RAM.

The load address generator (LOADAD) reads the data in which the count value output from the instruction counter (INSTCNT) is latched, and when this data is an address for jumping, determines the jump destination address according to each input condition. Output to the instruction counter (INSTCNT).

Here, although the instruction of the syndrome calculation and the instruction of the correction process are proceeding at the same time, the RAM cannot be accessed at the same time. Therefore, the instruction controller (INSTCONT) monitors the address so that the RAM access does not collide. It controls the instruction counter (INSTCNT). In addition, although the syndrome calculation and the correction process are performed at the same time, since the sequence being corrected is the syndrome one sequence before the syndrome calculation performed at the same time, the flag controller (FLGCONT) stores the information and the flag related to the syndrome calculation. , This information and flags are used in the correction process.

Next, the error correction process and the erasure correction process in FIGS. 2 and 3 will be described. 1. Error correction Error correction is performed on the received data by performing a syndrome operation (hereinafter referred to as syndrome check).
Correcting the position and value of the data based on the result. In this case, one error data has two unknowns (position and value), and since both C1 and C2 sequences have four parities, error correction of up to 2 words is possible. Here, in the MD, the syndromes S0 to S3 of the C1 series and the syndromes Sq0 to Sq of the C2 series.
3 is calculated as in the following equations (Equation 1 and Equation 2).

[0025]

(Equation 1)

[0026]

(Equation 2)

The one-word and two-word error correction will be described below. 1-1.1 Error correction When there is one error, the result of the thin check (S0
S3) is as follows, where Ei is the error magnitude and Xi is the error position. S0 = Ei S1 = Xi * Ei S2 = Xi ² * Ei S3 = Xi ³ * Ei

When Ei and Xi are obtained by using S0 to S3, Xi = S1 / S0 Ei = S0 If an erroneous received data value is Di and a correct data value is Wi.

[0029]

(Equation 3)

The correction process is performed by the data D at the memory address Xi.
i is read and the result of adding Ei is the memory address X
It ends by writing to i. 1-2.2 Error correction The syndrome when there are two errors has Ei and Ej as error magnitudes and Xi and Xj as error positions.

[0031]

(Equation 4)

## EQU1 ## There is also a method of obtaining four unknowns by solving these four simultaneous equations, but here, the equation of the root of the position is introduced to reduce the processing steps. First, the sum and product of error positions are defined.

[0033]

(Equation 5)

These Xi and Xj are the roots of the following equation F (Y).

[0035]

(Equation 6)

Expanding this equation,

[0037]

(Equation 7)

Since it is not possible to refer to the table in this format, if the variable is transformed into Y = C1 * Z, the above equation becomes

[0039]

(Equation 8)

It is possible to obtain Zi by obtaining Z by the contrast ROM 7 of C2 / C1 ² and Z and Xi = C1 * Z Xj = C2 / Xi. Also, C1,
C2 is given as a function of the syndromes S0 to S3.

[0041]

[Equation 9]

In the actual correction work, C1 and C2 are obtained, the result is referred to the control ROM 7, and the reference result is multiplied by C1 to obtain Xi. The error magnitudes Ei and Ej are

[0043]

[Equation 10]

The error correction of 2 words is completed by rewriting the data in the memory based on the above calculation result.

2. Erasure correction Erasure correction is a correction method in which the position of an error is known in advance and only the error value is obtained. In MD, since the number of C2 sequence parities is 4, it is possible to perform erasure correction of a maximum of 4 words. it can. The erasure correction will be described in detail. Now, assuming four errors, the positions of these errors are X1, X2, X3, and X4, and the following calculation is performed.

[0046]

[Equation 11]

The error values corresponding to the error positions X1 to X4 are Y1, Y2, Y3, and Y4. T3 is defined by the following formula.

[0048]

[Equation 12]

Y4 is given by the following equation. Y4 = T3 / I4 With this, the fourth data can be corrected first.
The syndrome is then modified to find Y3 and Y4 is erased from the syndrome.

[0050]

[Equation 13]

From this modified syndrome, T2, Y
Ask for 3.

[0052]

[Equation 14]

Similar processing is performed for Y2.

[0054]

(Equation 15)

Finally, Y1 is calculated.

[0056]

[Equation 16]

With the above, erasure correction of 4 words is completed. Next, the C1 correction process will be described with reference to FIG. When the C1 correction process starts (step S1
01), first, the syndromes S0 to S3 are calculated by the above-mentioned formula (Equation 1) (step S102), and then the syndromes S0 to S3 are converted into α → i and stored in the register 8.

After step S102, it is determined whether the current operation mode is the recording mode (step 103).
This judgment is made by setting a predetermined flag when the recording mode is set by the operation switch of the target MD recording / reproducing apparatus and observing this flag.
If it is not in recording mode, it is regarded as playback mode. That is, all modes other than recording and reproduction such as rewinding are handled as reproduction modes. Step S below
The case in which the reproduction mode is determined in 103 will be described first.

In the reproduction mode, the syndromes S0 to S
It is determined whether all 3 are "0" (step 104), and Y
In the case of ES, "0" is written in each of the C1 error flags F0, F1, and F2 (step S105), and then the C2 correction process shown in FIG. 3 is performed (step S118). On the other hand, in steps S104, the syndromes S0 to S3 are
If all are not "0", first,

[0060]

[Equation 17]

Based on the above, the modified syndromes σ1 to σ3 for detecting the one-word error are calculated (step S1
06) It is determined whether or not there is a one-word error (step S
107). In the case of a 1-word error, the 1-word correction described above is performed and the corrected data is written (step S10).
8) Then, based on Table 1 as well, "1" is written in the C1 error flag F0 (step S109). Then, FIG.
The process proceeds to the C2 correction process shown in (step S118).

On the other hand, if it is determined in step S107 that there is no one-word error, X1, X2, φ1, and φ2 for detecting a two-word error are calculated according to the equation (18) (step S110). It is determined whether or not (step S111).

[0063]

(Equation 18)

In the case of a 2-word error, 2-word correction is performed as described above and the corrected data is written (step S112), and then "1" is written in the C1 error flag F1 as shown in Table 1 (step S112). S11
3). Then, the process proceeds to the C2 correction process shown in FIG. 3 (step S118).

If it is not a 2-word error in step S111, "1" is written in the C1 error flag F2 as shown in Table 1 (step S114), and then the process proceeds to the C2 correction process shown in FIG. 3 (step S11).
8).

If the recording mode is determined in step S103, the parity position (S28 to S31) is loaded (step S115), pre-computation is performed (step S116), and 4 erasure correction is performed (step S1).
17). Then, the process proceeds to the C2 correction process shown in FIG. 3 (step S118).

Next, the C2 correction process will be described with reference to FIG. This C2 correction processing performs 1 error correction, 2 error correction, and 3 or more error detections. Also, C1
Erasure correction of up to 4 words is performed by regarding the flag position as an error position.

First, the C1 flag is read (step S
122). Here, the C1 flags of F0 and F1 indicate that 1 error correction and 2 error correction were performed in the C1 correction, and the C1 flag of F2 indicates that three or more errors were detected. There is a high probability of erroneously correcting 3 or more errors as 2 errors. Therefore, in the C2 correction, attention is paid to the numbers and positions of the F1 and F2 flags to perform the correction. Next, the syndromes Sq0 to Sq3 described above are calculated (step S123), and the syndromes Sq0 to Sq are calculated.
3 is α → i converted and stored in the register 8.

Then, similarly to the case of C1, it is judged whether or not the recording mode is set (step S124), and if it is the reproduction mode, the process proceeds to step S125 and thereafter. Step S125
In the following, it is determined whether or not the number of errors is "0" by determining whether or not all of the syndromes Sq0 to Sq3 are "0" (step S125), and if "0", the C2 error flags F0, F1, "0" is written in both F2 (step S126), and the C2 correction process is completed (step S127).

On the other hand, if the syndromes Sq0 to Sq3 are not all "0" in step S125, the modified syndromes σ1 to σ for detecting the one-word error.
3 is calculated (step S128), and then it is determined whether there is a one-word error (step S129). And
In the case of a 1-word error, 1-word correction is performed to write the corrected data (step S130), and then "0" is written to the C2 error flags F0, F1, and F2 (step S131), and the C2 correction process is completed (step S131). S127).

On the other hand, if the one-word error is not detected in step S129, the modified syndromes X1, X2, φ1 and φ2 for detecting the two-word error are calculated (step S132), and then it is determined whether or not there is a two-word error. It is determined (step 133). Then, in the case of a 2-word error, 2-word correction is performed to write the corrected data (step S134), and then the C2 error flag F
Write "0" to both 0, F1, and F2 (step S
135) The C2 correction process ends (step S12).
7).

If it is not a 2-word error in step S133, a maximum of 4 erasure corrections are performed (step S136).
“0” is written in each of the error flags F0, F1, and F2 (step S137 → S138), and the C2 correction process is ended (step S127). In addition, step S137
C2 error flag F if not correctable in
“0”, “1”, “1” or “1” is written to 0, F1, and F2, respectively (step S139), and the C2 correction process ends (step S127).

In the recording mode in step S124, the parity position is loaded (step S14).
0), pre-calculation is performed (step S141), 4 erasure correction is performed, and parity calculation is performed (step S14).
2).

As described above, the reason why the recording mode is different from the reproducing mode is that the parities of the C1 and C2 series must be calculated during recording. Since the position of parity is known in advance, erasure correction is applied and parity calculation is performed instead of error correction. As described above, since the position of the error is unknown during reproduction, the error flag is written by C1 correction,
Although the position of the error was detected by reading it during C2 correction, the position of the parity was known at the time of recording, so that parity calculation can be performed using erasure correction even in the C1 series.

[0075]

As described above, according to the present invention, in the error correction apparatus using the Reed-Solomon code, the step of reading the C1 flag in the reproduction mode so that the processing of both the recording system and the reproduction system can be shared. Alternatively, in the recording mode, the parity position is loaded, and C1, C
Parity calculation is realized by performing both 4 erasure correction. Therefore, the recording system and the reproducing system can share a part of the program with the hardware, and the recording routine can be executed by switching the jump address of the program by switching the mode by providing the same software with a recording subroutine.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a recording / reproducing error correction device according to the present invention.

FIG. 2 is a flowchart illustrating a routine for correcting a C1 sequence of Reed-Solomon code.

FIG. 3 is a flowchart for explaining a routine for correcting a C2 sequence of Reed-Solomon code.

[Explanation of Codes] 2 Flag Location Circuit 22 Syndrome Operation Block 23 Latch Block 24 Address Block 25 Instruction Block 26 Correction Block

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H03M 13/00 H03M 13/00

Claims (1)

[Claims] 1. A recording / reproducing error correction device employing a double Reed-Solomon code of C1 series and C2 series, comprising: a mode determining means for determining whether a recording mode or a reproducing mode, and the mode determining means. When the reproduction mode is determined, an error position is detected by an error position detection means, and when the mode determination means determines the recording mode, the error position detection operation in the error correction means is performed by a parity check. C1 series error correction, which has a means for performing parity calculation in place of the position setting operation, wherein the means for performing error correction corrects an error in each block of the C1 series and stores an error flag for each block. Means and C2 stored by the C1 series error correction means
An error correction device for recording / reproduction having C2 series error correction means for reading out an error flag corresponding to each word of the series and correcting an error in each block of the C2 series.