JPH07296527A - Recording/reproducing error correction device - Google Patents

Abstract

PURPOSE:To reduce the number of parts, to save space and to reduce a manufacturing cost by sharing an error correction device using a double Reed Solomon code to a recording system/a reproducing system. CONSTITUTION:This device is provided with a mode discrimination means 170, means 108-120 correcting an error and the means 174, 175 calculating parity. The mode discrimination means 170 discriminates whether a recording/ reproducing device becoming an object is a recording mode or a reproducing mode, and the means 108-120 correcting the error detects the position of the error and corrects the error when the device is discriminated as the reproducing mode by the mode discrimination means 170. The means 174, 175 calculating the parity calculates the parity by replacing the position detection operation of the error in the means 108-120 correcting the error to the position detection operation 173 of the parity when the device is discriminated as the recording mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device which employs a double Reed-Solomon code, and particularly reproduces an audio signal recorded on a DCC (digital compact cassette) or records on the DCC. In this case, the present invention relates to an error correction device.

[0002]

2. Description of the Related Art Generally, in DCC, a double Reed-Solomon (RS) code mainly consisting of a C1 sequence for random error correction and a C2 sequence mainly for burst error correction is cross-interleaved. For example, in DCC, one frame of main data is composed of 12288 words (1 word = 8 bits), and this data has two rules (C
Based on 1, C2 interleaving, correction is performed by dividing into two series of C1 series of 24 words per series (block) and C2 series of 32 words per block. That is, in DCC, 12288 data are C1
Both C and C2 are classified.

In the error correction during reproduction of the DCC system, the C1 series is first corrected. In the C1 series, one block is composed of data s0 to s23 of 24 words, and one frame is a block W (= 512 (12288 ÷ 24)) (=
0 to 511). In the C1 correction, the error is divided into four types of 0 word, 1 word, 2 words, 3 words or more for one block, and according to the result, as shown in Table 1, as error flags, "00" and " Each 8-bit data of "01", "03", and "07" is written in the memory. Therefore, since the error flag data of C1 is one in one block,
A total of 512 pieces are written in the memory per frame.

[0004]

[Table 1]

The last block of the C1 series (W = 51
When the correction of 1) is completed, the correction of the C2 series is started. C
In the 2 series, one block has 32 words of data t0 to t31
, One frame is 384 (12288/3)
2) Block V (= 0 to 383).
In the C2 correction, the error is corrected when the error position is known by the C1 correction, that is, when it is known which of the 32 word data t0 to t31 in the C2 series is the error, a so-called Perform erasure correction.

Here, 32-word data t0 of C2 series
Up to t31, any block (W
= 0 to 511), so in erasure correction, C1 data to which C2 series data belongs
The error flag data of the block W of the series is read, and the C1 block is corrected by two words (error flag “0
3 ") or an error of 3 words or more (error flag" 07 "), the erasure correction is performed assuming that the C2 data is an error.

Conventionally, in this type of error correction device, C2
All 384 blocks V when the sequence is corrected
With respect to, the error flag in the correction of the C1 series is read and evaluated. That is, in the erasure correction of the conventional DCC system, the error flag is set 12288 times (384 blocks × 32) per frame.
(Word) read.

Further, at the time of recording, parity calculation is performed for each series of C1 and C2 according to a predetermined flow. Since this operation is different from the error correction during playback described above,
In a recording / reproducing apparatus having a recording unit and a reproducing unit, the recording system and the reproducing system were separate and independent in terms of hardware and software.

[0009]

In such a conventional recording / reproducing error correcting apparatus, since the error correcting process using the Reed-Solomon code is independently performed in the recording unit and the reproducing unit, the hardware Both software are prepared separately. Therefore, the number of parts is large, space is required, and parts cost, assembly cost, software creation cost, etc. are high.

Therefore, it is an object of the present invention to provide a recording / reproducing error correction device capable of reducing the number of parts, saving space, and reducing manufacturing costs.

[0011]

In order to achieve the above object, according to the present invention, the same software program is executed in the steps of the error correction processing at the time of recording and the error correction processing at the time of reproduction. However, jumps are made as necessary in different areas, and during recording, parity position calculation is performed by replacing the error position detection operation during reproduction with the parity position detection operation.

That is, according to the present invention, the C1 series and the C2 series are
An error correction device for recording / reproduction, which employs a double Reed-Solomon code of a series, wherein a mode discriminating means for discriminating between a recording mode and a reproducing mode and a reproducing mode by the mode discriminating means. When the recording mode is discriminated by the means for detecting the error position and correcting the error and the mode discriminating means, the error position detecting operation in the error correcting means is placed in the parity position detecting operation. Instead, a means for performing parity calculation,
There is provided a recording / reproducing error correction device having the following.

[0013]

Since the present invention has the above-described structure, the error correction device of the recording / reproducing device such as the target DCC can be used for both the recording system and the reproducing system by jumping the program.
Low cost and space saving can be realized.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing an error correction method at the time of reproduction in an embodiment of the recording / reproducing error correction device according to the present invention, and FIG. 2 is an explanatory diagram showing the relationship between C1 series words and C2 series words. 3 is an explanatory view showing the relationship between the 0th to 95th series of the C2 series and the C1 series, and FIG. 4 is an explanatory view showing the relationship between the 96th to 191st series of the C2 series and the C1 series.

Although the present invention is an error correction device that can be used for both recording and reproduction, a portion related to both recording and reproduction and a portion related only to reproduction will be described first. The relationship between each word of the C1 series and the C2 series will be described with reference to FIGS. As described above, the C1 and C2 sequences of the main data of the DCC system are C1: GF (2 ⁸ ) Reed Solomon Code (24, 20,
5) C2: GF (2 ⁸ ) Reed Solomon Code (32, 26,
It is composed of the code system of 7). Also, 1 frame is 1
It is composed of 2288 words (1 word = 8 bits), and one frame of C1 and C2 series is 512 series (block) of C1: W = 0 to 511, respectively, and 384 series (block) of C2: V = 0 to 383. It is composed of.

As shown in FIG. 2, the relationship between each word of the C1 series and the C2 series is (1) V = 0 of the C2 series, each word data of 24 series of 4 to 46 (t = 0 to 31) are sequentially arranged in the vertical direction from the first symbol (t = 0), and each word data of the same symbol number (t = 0 to 31) of each C2 series is set to V = 0, 2, 4 to 46. When arranged in sequence in the horizontal direction, each word data in the horizontal direction of this C2 sequence has W = 0, 26, 36, 62 to 492 of the C1 sequence,
It becomes the same as each word data (s0 to s23) of 502.

That is, for example, each horizontal word data of C2 symbol t = 0 is the same as each W = 0 word data s0 to s23 of the C1 series, and each horizontal word data of C2 symbol t = 1 is It is the same as the W = 26 word data s0 to s23 of the C1 sequence, and the C2 symbol t =
The horizontal word data 3 is the same as the C1 series W = 62 word data s0 to s23. More specifically, the word data of the 0th symbol (t = 0) of the 0th sequence (V = 0) in the C2 sequence is W = 0 in the C1 sequence.
And the word data of the second symbol (t = 2) of the fourth series (V = 4) in the C2 series is W = 36 word data s2 of the C1 series.

Similarly, as shown in FIG. 3, C2 series (2) V = 1, 3, 5, 45, 47 (3) V = 48, 50-92, 94 (4) V = 49, 51- 93, 95 Further, as shown in FIG. 4, C5 series (5) V = 96, 98 to 140, 142 (6) V = 97, 99 to 141, 143 (7) V = 144, 146 to 188, 190 (8) Each word data (t = 0 to 3) of 24 series of V = 145, 147 to 189, and 191 respectively.
When 1) is sequentially arranged in the vertical direction from the first symbol (t = 0) as in FIG. 2, and each word data having the same symbol number (t = 0 to 31) of each C2 series is arranged in the horizontal direction in the order of series. Each horizontal word data of the C2 series is the same as each word data (s0 to s23) of the C1 series of the number W shown in FIGS. 3 and 4.

Although not shown in the figure, (9) V = 192, 194 to 236, 238 (10) V = 193, 195 to 237, 239 (11) V = 240, 242 to 284 of the C2 series. 286 (12) V = 241, 243-285, 287 (13) V = 288, 290-332, 334 (14) V = 289, 291-333, 335 (15) V = 336, 338-380, 382 (16) Similarly, in the case of V = 337, 339 to 381, 383, each word data in the horizontal direction of this C2 series is each word data of another C1 series (s0 to s23).
Is the same as

That is, in the DCC system, one frame of C1 series is composed of 512 series of W = 0 to 511,
Since one frame of the C2 series is composed of 384 series of V = 0 to 383, the block V of the C2 series overlaps the word of the C1 series based on the cyclicity of the word of the C1 series and the word of the C2 series. 16 for each series
(= 384/16) groups can be made (in this specification, "group" is used to distinguish from the above blocks). Needless to say, V =
Since each series of 0 to 383 has each data word of t = 0 to 31, 32 × 16 = 512 C1 series in one frame, which is one frame of the C1 series.

Here, in the correction of the C1 series, as will be described later, when an error is detected and the correction is actually performed, or when an error of 3 words or more cannot be detected and corrected, the word has an error. Is stored in the memory, and in the subsequent C2 series correction, all the data included in the C1 series word that had an error in the C1 series correction is regarded as an error and is corrected (erasure correction). However, in this erasure correction of the C2 series, so-called C1 flag evaluation is performed, in which the correction result in the correction of the C1 series is read out as a flag before the correction.

For example, as indicated by "x" in FIG.
When there is an error in one sequence of W = 0, 36, 492, in each of the C2 sequence of V = 0, 2 to 44, and 46, the symbol t = 0, 2, 30 of 32 words Three
Erasure correction is performed by regarding the word as an error. As described above, for example, when there is an error of 3 words or more in the sequence of W = 36 in the correction of the C1 sequence, the error flag “07” is stored.

Therefore, in this embodiment, V = 0, 2 to 4
In the first group of Nos. 4 and 46, all error flags read when performing erasure correction of each series are not read, and V =
By reading the C1 error flag of only the 0 series, performing the C1 flag evaluation, and counting and storing the position and the number of the error, the error flag is set in the erasure correction of each series of V = 2 to 44 and 46. I try not to read it.

Similarly, in the erasure corrections of the second to sixteenth groups, V = 1, 48, and
49, 96, 97, 144, 145, 192, 193,
By reading the error flags of only the 240, 241, 288, 289, 336, and 337 series, performing the C1 flag evaluation, and counting and storing the position and number of the errors, the other C1 error flags are stored in the same group. Erasure correction of all C2 series can be performed without reading. Therefore, according to the present embodiment, the C1 flag evaluation for one frame is performed once for each group in total.
6 times is enough.

Next, an apparatus for implementing the above error correction method will be described. FIG. 5 is a block diagram showing an embodiment of the error correction device according to the present invention, FIG. 6 is a flowchart for explaining a routine for correcting the C1 sequence of the Reed-Solomon code, and FIG. 7 is for correcting the C2 sequence of the Reed-Solomon code. 8 is a flow chart for explaining an erasure routine of the C2 series correction routine of FIG. 7, and FIG. 9 is a flow chart for explaining a syndrome correction routine. The C1 error flag evaluation described with reference to FIGS. 1 to 4 is performed by the flag location setting circuit 2 shown in FIG.
Further, step 12 of the C2 series correction routine shown in FIG.
4 is executed.

First, the circuit shown in FIG. 5 will be briefly described. The circuits 2 to 20 are configured to correct the error of the signal input from the input terminal 1, and the portion 2 which constitutes the error correction circuit. .. to 20 are roughly divided into a syndrome calculation block 22 including circuits 2 to 8, a latch block 23 including circuits 9 to 14 and a correction block 26 including circuits 15 to 20. The blocks 22, 23 and 26 are controlled by an address block 24, an instruction block 25 and an auxiliary track interrupt block 27.
23 and 26 are DCC main tracks C1 and C2
Interrupt processing is performed so as to selectively correct the C1 series of the series and the auxiliary track.

The flag location setting circuit 2 is a circuit for evaluating a C1 error flag for erasure correction at the time of reproduction. The flag location setting circuit 2 reads the C1 error flag once for 24 series of C2, and detects the 2-word error and 3-word error of C1. Detect position and number. The circuit 2 also generates and outputs a RAM address for reading the error flag.

The parity location setting circuit 3 outputs the parity position to the location selection circuit 4 according to each of the main track series C1 and C2 and the auxiliary track series AUXC1 in order to calculate the parity by using erasure correction during recording. To do. The location selection circuit 4 is
The error position from the flag location setting circuit 2 is selected in the reproduction mode, and the parity position from the parity location setting circuit 3 is selected in the recording mode and output to the register output selection circuits 9 and 11.

The syndrome check circuit 5 receives data from a RAM (not shown) input from the input terminal 1 and calculates four syndromes S0 to S3 in the C1 series and six in the C2 series as described later. The syndromes S0 to S5 are calculated and output to the syndrome selection circuit 6. The syndrome selection circuit 6 selects the syndrome from the syndrome selection circuit 6 and the output from the register 19 or 16 and converts it into an index α-i of the table.
Output to the conversion ROM 7.

The syndrome storage register 8 stores α-i
The conversion ROM 7 stores the α-i converted syndrome, and this register 8 also outputs a flag “1” when all the stored syndromes are “00”. The register output selection circuits 9 and 11 select the syndrome stored in the syndrome storage register 8, the data selected by the location selection circuit 4 and the data stored in the register 14 and output them to the adder circuit 12, and also make corrections. The data symbol address latch circuit 10 stores the error position obtained by the calculation when executing the error correction, and outputs it to the RAM address output circuit 24.

The adder circuit 12 is a register output selection circuit 9,
The data selected by 11 is added. Since this addition is addition of the exponent part of α, the instruction is multiplication. The register input / output selection circuit 13 is the addition circuit 1
The output of 2 or the syndrome which is α-i converted by the ROM 7 is selected and stored in the register 14 in the subsequent stage. The register 14 is used to temporarily store the data during the calculation and output it to the register output selection circuits 9 and 11.

The i-α conversion circuit 15 performs an i-α conversion on the output of the adder circuit 12, and this data is added to the data stored in the register 19 by the exclusive OR circuit 17 and stored again in the register 19. It Register 16, Z ² + Z + X = 0 the solution was stored converted by entering a value of "X" in order to obtain the "Z" to the value "Z" is output when two words corrected. The corrected data output circuit 20 outputs the corrected data obtained by the exclusive OR circuit 18 from the data from the i-α conversion circuit 15 and the error data on the data bus onto the data bus.

The RAM address output circuit 24 stores the main data C1 series RAM address (C1RAMAD),
RAM address (C1FLGAD) of main data C1 series error flag and main data C2 series RAM
Address (C2RAMAD) and RAM address of main data C1 series error flag (C2FLGAD)
And error flag data of each series (ERFLGBUF)
Is generated and output.

Since the AUX information is not synchronized with the main data C1 and C2 at the time of reproduction, the auxiliary track interrupt detection circuit 27 performs calculation and correction in the form of interrupt, and detects the change point of the input signal at the time of reproduction. To output the interrupt flag. There are four change points of the input signal in one frame, and each time the auxiliary track data is processed in two series. Auxiliary track interrupt detection circuit 27
In addition, the auxiliary track data AUXC1 series RAM address (AXC1AD) and the auxiliary track data AUX
RAM address of C1 series error flag (AXFLG
AD) is generated and output.

Next, the instruction circuit 25 will be described in detail. First, the clock generator (CLOCKGE).
N) generates various clocks used in this device from each input signal. Instruction counter (I
NSTCNT) is a 10-bit counter for C1, C2, and AUXC1 syndrome operations and C1 error flag evaluation instructions, and the output of this counter is the address of the instruction ROM (INSTROM) 25a. One step of this instruction is from clock rise to rise
Count up by the clock. Further, the jump of this instruction is performed by loading the following jump destination address.

The instruction ROM 25a outputs 16-bit data with the count value output from the instruction counter (INSTCNT) as an address, and this data determines the processing operation in each step of the instruction. The instruction selector (INSTSEL) is an instruction ROM 25a.
The output destination of the 16-bit data output from is distributed according to the type of processing (syndrome operation, error flag processing, etc.), and this output is output at the clock timing. Further, this selector outputs a signal for stopping the instruction when accessing the RAM.

The load address generator (LOADAD) reads the data in which the count value output from the instruction counter (INSTCNT) is latched, and when this data is an address for jumping, determines the jump destination address according to each input condition. Output to the instruction counter (INSTCNT).

Here, although the instruction of the syndrome operation and the instruction of the correction process are in progress at the same time, since the RAM cannot be accessed at the same time, the instruction controller (INSTCONT) monitors the address so that the RAM access does not collide. It controls the instruction counter (INSTCNT). Further, although the syndrome calculation and the correction process are performed at the same time, since the sequence being corrected is the syndrome one sequence before the syndrome calculation that is performed at the same time, the flag controller (FLGCONT) stores the information and the flag related to the syndrome calculation. , This information and flags are used in the correction process.

Next, the C1 correction process will be described with reference to FIG. When the C1 correction process starts (step 101), first, the expression [C1] shown in the upper part of the following expression (Equation 1) is given.
To check the syndromes S0 to S3 (step 102), and then the syndrome S shown in the following equation (Equation 2).
0 to S3 are converted from α to i and stored in the register 8 (step 103).

[0040]

[C1] S0 = W0 + W1 + W2 + ... + W23 S1 = α ²³ W0 + α ²² W1 + α ²¹ W2 + ... + W23 S2 = α ⁴⁶ W0 + α ⁴⁴ W1 + α ⁴² W2 + ・ ・ ・ ・ ・ + W23 S3 = α ⁶⁹ W0 + α ⁶⁶ W1 + α ⁶³ W2 + ... + W23 [C2] S0 = W0 + W1 + W2 + ... + W31 S1 = α ³¹ W0 + α ³⁰ W1 + α ²⁹ W2 + ・ ・ ・ ・ ・ + W31 S2 = α ⁶² W0 + α ⁶⁰ W1 + α ⁵⁸ W2 + ... + W31 S3 = α ⁹³ W0 + α ⁹⁰ W1 + α ⁸⁷ W2 + ・ ・ ・ ・ ・ + W31 S4 = α ¹²⁴ W0 + α ¹²⁰ W1 + α ¹¹⁶ W2 + ・ ・ ・ ・ ・ + W31 S5 = α ¹⁵⁵ W0 + α ¹⁵⁰ W1 + α ¹⁴⁵ W2 + ・ ・ ・ ・・ + W31

[0041]

## EQU00002 ## C1: S0 S1 S2 S3 C2: S0 S1 S2 S3 S4 S5

After step 103, it is determined whether the current operation mode is the recording mode (step 170). This determination is made by setting a predetermined flag when the recording mode is set by the operation switch of the target DCC recording / reproducing device and observing this flag.
If it is not in recording mode, it is regarded as playback mode. In other words, for modes such as rewinding other than recording and playback,
Treat all as playback mode. Step 170 below
The case where it is determined to be the reproduction mode will be described first.

In the reproduction mode, the syndromes S0 to S
It is determined whether all 3 are "0" (step 104), and Y
In the case of ES, "0" is written in each of the C1 error flags F0, F1 and F2 (step 105), and then the block address is incremented by 1 (step 10).
6) If all blocks (W = 0 to 511) are not completed, the process returns to step 102, and if completed, the process proceeds to the C2 correction process shown in FIG. 7 (step 107).

On the other hand, if all of the syndromes S0 to S3 are not "0" in step 104, first, the modified syndromes σ1 to σ3 for detecting a one-word error are calculated based on the following equation (Equation 3) ( Step 10
8) Then, it is determined by the following equation (Equation 4) whether or not there is a one-word error (step 109).

[0045]

Σ1 = S1 ² + S0 * S2 σ2 = S2 ² + S1 * S3 σ3 = S1 * S2 + S0 * S3

[0046]

Σ1 + σ2 + σ3 = 0 1 word error σ1 + σ2 + σ3 ≠ 0 1 word error or more

In the case of a 1-word error, 1-word correction is performed based on the following equation (Equation 5) and the corrected data is written (step 110). Then, based on Table 1, C1 error flag F0 is set to "1". Write (step 111).
Next, the block address is incremented by 1 (step 112) and the process proceeds to step 107.

[0048]

[Equation 5] [1 word correction] Error position: Xi = S1 / S0 Error value: Ei = S0 Correction: Wi = S0 + Di (Di ... error data)

On the other hand, if the one-word error is not found in step 109, X1, X2, φ1 to φ3 for detecting the two-word error are calculated by the following equation (Equation 6) (step 113), and then the following equation It is determined by (Equation 7) whether or not there is a 2-word error (step 114).

[0050]

[Equation 6]

[0051]

(7) φ1 + φ2 + φ3 = 0 2 word error φ1 + φ2 + φ3 ≠ 0 2 word error or more

In the case of a 2-word error, 2-word correction is performed based on the following equation (Equation 8) (step 1
15) Write the corrected data Wi and Wj by the following equation (Equation 9) (step 116), and then write C1 as shown in Table 1.
"1" is written in the error flags F0 and F1 (step 117). Next, the block address is incremented by 1 (step 118) and the process proceeds to step 107.

[0053]

[Equation 8]

[0054]

[Correction of Wi and Wj] From S0 = Ei + Ej S1 = Xi * Ei + Xj * Ej Xj * S0 + S1 = (Xi + Xj) * Ei Ei = (Xj * S0 + S1) / C1 Ej = S0 + Ei Wi = Ei + DiWjDi

If no 2-word error occurs in step 114, "1" is written in both C1 error flags F0, F1, and F2 as shown in Table 1 (step 1
19), then the block address is incremented by 1 (step 120) and the routine proceeds to step 107.

When it is determined in step 170 that the recording mode is set, it is determined whether the block address W is 0 (step 172). If 0, that is, if it is the head block, the parity position (s20 to s23). Is loaded (step 173) and pre-computation is performed (step 17
4) Perform 4 erasure correction (step 175). On the other hand, when W ≠ 0, steps 173 and 174 are not performed, and the process proceeds to step 175 to perform 4 erasure correction,
Perform parity calculation. After step 175, the process returns to the above-mentioned step 106, and moves to the C2 correction flow via step 107.

Next, the C2 correction process will be described with reference to FIGS. This C2 correction processing is started after performing C1 correction for all blocks (W = 0 to 511) (step 121), and first, the syndromes S0 to S5 are checked by the lower stage [C2] of the above equation (Equation 1) ( Step 122), and then the syndromes S0 to S5 shown in the lower stage of the above equation (Equation 2) are subjected to α → i conversion to register 8
(Step 123). Then, as in the case of C1, it is judged whether or not the recording mode is set (step 18).
0), in the reproduction mode, it is judged whether or not it is the head of the group (step 181), and if it is the head, the C1 error flag is read and the number N (E) of error flags and the error are calculated by the following equation (Equation 10). The position Xi is detected (step 12)
4). On the other hand, if it is not the head of the group, step 1
Go to 26.

[0058]

[C1 Flag Calculate] Read: C1 Flag Location Count: C1 Flag Number Register: C1 Flag Location X1, X2, X3,
X4, X5, X6

Here, as described with reference to FIGS. 1 to 4, in step 124, V = 0, 1, 48, 49, 9
6, 97, 144, 145, 192, 193, 240,
In the blocks 241, 288, 289, 336, and 337, the C1 error flag is read, the C1 flag is evaluated, and the position and number of the error are counted and stored.
The C1 error flag is not read in other blocks. In the following step 125, pre-calculation as shown in the following equation (Equation 11) is performed.

[0060]

X1 + X2 = B1 X1 * X2 = B2 B1 + X3 = C1 B1 * X3 + B2 = C2 B2 * X3 = C3 C1 + X4 = D1 C1 * X4 + C2 = D2 C2 * X4 + C3 = D3 C3 * X1 * D4 = D4 = D4 X5 + D2 = E2 D2 * X5 + D3 = E3 D3 * X5 + D4 = E4 D4 * X5 = E5 (X1 + X6) * (X2 + X6) (X3 + X6) (X4 + X6) (X5 + X6) = X3 + X5) (X3 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X2 + X5) (X1 + X4) (X2 + X4) (X3 + X4) = I4 (X1 + X3) (X2 + X3) = I3 (X1 + X2) = I2

Then, it is determined whether the number of errors is "0" by determining whether all the syndromes S0 to S5 are "0" (step 126).
2 “0” is written to the error flags F0 and F1 (step 127), the block address is incremented by 1 (step 128), and all blocks (V = 0 to 38)
If step 3) is not completed, the process returns to step 122, and if it is completed, the C2 correction process is completed (step 1).
29).

On the other hand, when all the syndromes S0 to S5 are not "0" in step 126, the modified syndromes σ1 to σ3 for detecting the one-word error are calculated based on the above equation (Equation 3) (step 131). ), And then it is determined by the above equation (Equation 4) whether or not there is a one-word error (step 132). Then, in the case of a 1-word error, 1-word correction is performed based on the above equation (Equation 5) to write the corrected data (step 133), and then "0" is written to the C2 error flags F0 and F1 (step 1).
34). Then, the block address is incremented by 1 (step 135) and the process proceeds to step 129.

On the other hand, if the one-word error is not found in step 132, the modified syndromes X1, X2, φ1 for detecting the two-word error by the above equation (Equation 6).
.About..phi.3 is calculated (step 136), and then it is determined by the above equation (Equation 7) whether or not there is a 2-word error (step 137).

In the case of 2-word error, 2-word correction is performed based on the above equation (Equation 8) (step 1
38) Write the correction data Wi, Wj by the above equation (Equation 9) (step 139), and then the C2 error flag F0,
Write "0" to F1 (step 140). Then
Increment the block address by 1 (step 1
41) and the procedure goes to step 129. In addition, step 137
If it is not a 2-word error at, the process proceeds to the erasure routine shown in FIG.

In step 180, in the recording mode, it is judged whether or not the block address V is 0 (step 183). If it is 0, that is, if it is the head block, the parity positions t0, t7, t8, t16. , T23,
Then, t24 is loaded (step 187), pre-computation is performed (step 185), 6 erasure correction is performed, and parity calculation is performed (step 186). On the other hand, when V ≠ 0, the parity positions t0, t8, t are determined in step 184.
Load 15, t16, t24, t31 and step 1
Go to 85.

As is clear from the above description, at the time of reproduction, the correction is first performed in the sequence of C1 and then C2. If the C1 correction determines that there are two errors, the error flag “0
If it is determined that there are three or more "3", the error flag "07" is written (in C1 correction, the position where the error is from s0 to s23 can be detected up to two errors in one series. If there are three or more errors, it can be determined that there is an error, but the position cannot be detected.) In the subsequent C2 correction, each data of the C2 series (t0 to t31)
The error flag of the C1 series “W” to which the data belongs is read, and if this is “03” or “07”, the data is regarded as an error and correction is performed (erasure correction).
Therefore, in order to perform erasure correction, it must be known in advance where the error is. In the example of FIG. 1, each sequence of C2 V = 0, 2, 4, 6, ... 46 t0,
Correction is made assuming that t1 and t30 are errors.

As described above, the reason why the recording mode is different from the reproduction mode is that the parities of the C1 and C2 series must be calculated during recording. C
1 parity is s20 to s23, C2 parity is when "V" is an even number t0, t7, t8, t16, t23, t2
4, when odd number t0, t8, t15, t16, t2
4, t31. In this way, since the position of the parity is known in advance, erasure correction is applied to perform parity calculation instead of error correction. As described above, since the error position is not known during reproduction, the error position was detected by writing an error flag by C1 correction and reading it during C2 correction, but the position of parity was known during recording. Therefore, the parity calculation can be performed using the erasure correction even in the C1 series.

Next, the erasure routine will be described. First, it is determined whether or not the number of C1 error flags F1 is "0" (step 144), and if NO, it is determined whether or not the number of C1 error flags F1 is 5 or less (step 14).
5) If 5 or less, it is determined whether or not 5 (step 146). If the number of C1 error flags F1 is not 5, the syndrome correction routine shown in detail in FIG. 9 is executed. On the other hand, if the number is 5, the erasure of N = 5-1 is executed by the following equation (step 147). , Then the block address is incremented by 1 (step 14
8) and returns to step 121.

If the number of C1 error flags F1 is "0" in step 144, "1" is written in the C2 error flag F0 (step 149), and then the block address is incremented by 1 (step 14).
7) and returns to step 121. If the number of C1 error flags F1 is not 5 or less in step 145, the process branches to step 152 and below.

When the number of C1 error flags F2 is "0" in step 152, "1" is written in the C2 error flag F1 (step 153), and then the block address is incremented by 1 (step 154).
Return to step 121. If the number of C1 error flags F2 is 3 or less in step 152, the syndrome correction routine shown in detail in FIG. 9 is executed. If the number of C2 error flags F2 is 5 or less in step 156, The N erasure of N = 5-1 is executed, the block address is incremented by 1 (step 158), and the process returns to step 121.

If the number of C2 error flags F2 is not 6 in step 159, the C2 error flag F2
"1" is written in 1 (step 160), and then the block address is incremented by 1 (step 16).
1) and returns to step 121. When the number of C2 error flags F2 is 6 in step 162, N erasure of N = 6-1 is executed by the following equation (step 16
3) Then, the block address is incremented by 1 (step 164) and the process returns to step 121. Detailed description of the syndrome correction routine shown in FIG. 9 will be omitted.

[0072]

[Equation 12] [6 Erasure, Y6] T5 = S5 + E1 * S4 + E2 * S3 + E3 * S2 + E
4 * S1 + E5 * S0 Y6 = T5 / I6 [Syndrome correction] S0 + Y6 → S0 S1 + Y6 * X6 → S1 S2 + Y6 * X6 ² → S2 S3 + Y6 * X6 ³ → S3 S4 + Y6 * X6 ⁴ → S4

[0073]

[Equation 13] [5Erasure, Y5] T4 = S4 + D1 * S3 + D2 * S2 + D3 * S1 + D
4 * S0 Y5 = T4 / I5 [Syndrome correction] S0 + Y5 → S0 S1 + Y5 * X5 → S1 S2 + Y5 * X5 ² → S2 S3 + Y5 * X5 ³ → S3

[0074]

[4Erasure, Y4] T3 = S3 + C1 * S2 + C2 * S1 + C3 * S0 Y4 = T3 / I4 [Syndrome correction] S0 + Y4 → S0 S1 + Y4 * X4 → S1 S2 + Y4 * X4 ² → S2

[0075]

[3 Erasure, Y3] T2 = S2 + B1 * S1 + B2 * S0 Y3 = T2 / I3 [Syndrome correction] S0 + Y3 → S0 S1 + Y3 * X3 → S1

[0076]

[2Erasure, Y2] [1Erasure, Y1] T1 = S1 + X1 * S0 Y2 = T1 / I2 Y1 = S0 + Y2

[0077]

As described above, according to the present invention, in the error correction apparatus using the Reed-Solomon code, the step of reading the C1 flag in the reproduction mode so that the processing of both the recording system and the reproduction system can be shared. Instead of this, in the recording mode, the parity position is loaded, and 4 erasure correction is performed in the case of C1 and 6 erasure correction is performed in the case of C2, thereby realizing the parity calculation. Therefore, the recording system and the reproducing system can share a part of the program with the hardware, and the recording routine can be executed by switching the jump address of the program by switching the mode by making the same software have a recording subroutine. In the reproducing system, one frame of data is a C1 sequence composed of s words × W blocks, and
When the C2 sequence is error-corrected using the C2 sequence double Reed-Solomon code in which the frame data is composed of t words × V blocks, C2 is determined based on the cyclicity of the C1 sequence word and the C2 sequence word. A series block is C1
Since the error flags at the time of error correction of the C1 series are read once for each group by grouping the series words into overlapping groups, the error at the time of error correction of the C1 series in the other blocks of the grouped C2 series. It is not necessary to read the flag, and therefore error correction can be performed at high speed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an error correction method in an embodiment of a recording / reproducing error correction device according to the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a C1 series word and a C2 series word.

FIG. 3 is an explanatory diagram showing a relationship between 0th to 95th sequences of C2 sequence and C1 sequence.

FIG. 4 is an explanatory diagram showing the relationship between the 96th to 191st C2 series and the C1 series.

FIG. 5 is a block diagram showing an embodiment of a recording / reproducing error correction device according to the present invention.

FIG. 6 is a flowchart for explaining a routine for correcting a C1 sequence of Reed-Solomon code.

FIG. 7 is a flowchart for explaining a routine for correcting a C2 sequence of Reed-Solomon code.

8 is a flow chart for explaining an erasure routine of the C2 series correction routine of FIG.

FIG. 9 is a flowchart illustrating a syndrome correction routine.

[Explanation of symbols]

 2 flag location circuit 22 syndrome operation block 23 latch block 24 address block 25 instruction block 26 correction block

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11B 20/18 572 B 8940-5D G 8940-5D H03M 13/00 8730-5J

Claims (2)

[Claims] 1. A recording / reproducing error correction device employing a double Reed-Solomon code of C1 series and C2 series, comprising: a mode determining means for determining whether a recording mode or a reproducing mode, and the mode determining means. When the reproduction mode is determined, the error position is detected and error correction is performed, and when the recording mode is determined by the mode determination unit, the error position detection is performed by the error correction unit. A recording / reproducing error correction device having means for performing parity calculation by replacing the operation with the position detection operation of the parity. 2. A C1 series error correcting means for correcting an error in each block of the C1 series and storing an error flag for each block in which the error has occurred, and a C1 series word. Based on the cyclicity of the C2-series words, the C2-series blocks are grouped into groups in which the C1-series words overlap, and an error flag corresponding to each C2-series word is stored by the C1-series error correction means. Read once for each of the groups
2. The recording / reproducing error correction device according to claim 1, further comprising: C2 series error correction means for correcting an error in each block of the series.