JPH09320272A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics and reliability by reducing the number of transistors for pre-charge and balance, corresponding to plural bit line pairs respectively and relaxing the restrictions for the transistors. SOLUTION: Each of balancer circuits 21-2n is made a circuit, including transistors T21, T22 in which each one side out of a source and a drain is connected correspondingly to first and second bit lines BLj1, BLj2 (j=1-n) and the other side is connected to them in common, and a control signal EQ1 is inputted to a gate. One pre-charge circuit 30 is provided at the outside of a forming region of a memory cell array block for balancer circuits 21-2n, and the circuit 30 is made a circuit including a transistor T30, in which a power source potential Vcc is supplied to a source and a control signal EQ2 is inputted, a drain is connected to the other side common connection point of a source and a drain of transistors T21, T22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having means for precharging and balancing a bit line pair to a predetermined level at a predetermined timing.

[0002]

2. Description of the Related Art In a semiconductor memory device, particularly a static semiconductor memory device, first and second data input / output terminals of one memory cell are connected to a pair of first and second bit lines, Data is written to and read from the memory cell through the first and second bit lines forming the pair (hereinafter referred to as a bit line pair, if necessary). Further, in the dynamic type semiconductor memory device, although one bit line is connected to one memory cell, it is combined with another bit line of the reference potential to form a pair, and a memory is connected through the pair of bit lines. Writing data to cells,
In many cases, reading is performed.

In such a semiconductor memory device, when reading data from a memory cell, a pair of first and second bit lines (including a dynamic type) are set to a predetermined level at a predetermined timing. While charging
Balancing the potentials of these first and second bit lines,
It is generally equipped with a precharge circuit and a balancer circuit. Various examples of the semiconductor memory device including the precharge circuit and the balancer circuit will be described below.

FIG. 11 is a circuit diagram showing a first example of a conventional semiconductor memory device of this type.

The semiconductor memory device of the first example includes a memory cell array 10 including a plurality of static type memory cells M11 to Mmn arranged in a matrix in a plurality of rows (m rows) and a plurality of columns (n columns). , Memory cells M11 to Mmn
A plurality of word lines WL1 provided corresponding to each of the plurality of rows and for selecting the memory cells of the corresponding row in a row unit
To WLm and corresponding to a plurality of columns of the memory cells M11 to Mmn, respectively, and correspondingly connected to the first and second data input / output terminals of the memory cells of the corresponding columns to transfer the data of the selected memory cells. A plurality of paired first and second pairs
Bit lines BL11, BL12 to BLn1, BLn2
And a plurality of pairs of first and second bit lines BL11,
A balancer circuit 21x for balancing the potentials of the paired first and second bit lines at a predetermined timing, which is provided with a transistor T20 connected between BL12 and BLn1 and BLn2 and turned on and off according to the first control signal EQ1.
~ 2nx and a plurality of pairs of first and second bit lines B
L1 and BL12 to BLn1 and BLn2 are respectively connected and correspondingly provided with transistors T31x and T32x which are turned on / off in accordance with a second control signal EQ2n, so that a pair of first and second bit lines have a predetermined potential (predetermined timing). For example, precharge circuits 31 to 3n for precharging to the power supply potential VCC) and a plurality of memory cells MC11 to M
Sense amplifier 5 provided corresponding to each of the plurality of examples of Cmn and amplifies and outputs the transmitted data of the corresponding column.
1 to 5n and switch circuits 41 to 1 for transmitting the data of the corresponding columns to the sense amplifiers according to the column selection signals Y1 to Yn.
4n and a plurality of pairs of first and second bit lines BL1
1, BL12 to BLn1 and BLn2 are respectively connected to corresponding transistors T61 and T62, and load circuits 61 to 6n that operate as loads at the time of reading and writing data in the memory cell, and write circuits for switching data 41 to Tn.
4n through the first and second bit lines BL11, BL12
To BLn1 and BLn2, and a write circuit 70 for supplying to BLn1 and BLn2.

In this first example, the control signal EQ1
Is a signal for generating a one-shot pulse by detecting one of a change from a write (write) state to a read (read) state and a change in an address signal, and the transistor T20 is generated during the generation of the one-shot pulse. Is turned on to form a pair of first and second bit lines BL11 and BL1.
2 to BLn1 and BLn2 are balanced to the same potential. The control signal EQ2 is a signal for generating a one-shot pulse by sensing the change from the write state to the read state. During the generation period of the one-shot pulse, the transistors T31x and T32x are turned on and the first and first transistors are turned on. The two bit lines BL11, BL12 to BLn1, BLn2 are precharged to the power supply potential VCC level. That is, before reading the data of the memory cell, the first and second bit lines BL1
The levels of 1, BL12 to BLn1 and BLn2 are balanced to the power supply potential VCC.

A concrete circuit example of the memory cells MC11 to MCmn is shown in FIG. This circuit is a CMOS flip-flop circuit including transistors T1 to T4.

FIG. 13 is a circuit diagram of a precharge circuit and a balancer circuit portion of a second example of the conventional semiconductor memory device.

This second example is based on the control signal EQ of the first example.
1, EQ2 are integrated into one control signal EQx, and the balancer circuits 21x to 2nx and the precharge circuits 31 to 3n are controlled by the control signal EQx.

FIG. 14 is a circuit diagram showing a third example of a conventional semiconductor memory device.

In this third example, the transistors T31x and T32 of the precharge circuits 31 to 3n in the first example are used.
If x is a P-channel type, it is replaced with an N-channel type T31.
y, T32y to replace precharge circuits 31x-3
nx, the control signal thereof is EQ2 * of the level-inverted signal of EQ2, and similarly, the transistors of the load circuit are N-channel type T61x and T62x.
1x to 6nx. In this case, the gates of the transistors T61x and T62x are connected to the power supply potential VCC supply terminal in order to keep these transistors always on.

In the third example, the bit lines BL11, B
The precharge potential of L12 to BLn1 and BLn2 is an N-channel transistor T61 with respect to the power supply potential VCC.
The potential is lower by the threshold voltage of x, T62x, T31y, and T32y, and the operation speed can be increased accordingly.

FIG. 15 is a circuit diagram of a precharge circuit and a balancer circuit portion of a fourth example of the conventional semiconductor memory device.

In the fourth example, the control signals EQ1 and EQ2 * in the third example are integrated into EQy, the transistor T20 of the balancer circuits 21x to 2nx is controlled by the control signal EQy, and the level of the control signal EQy. The transistors T31y and T32y of the precharge circuits 31y to 3ny are controlled by the inversion signal. The precharge circuits 31y to 3ny are provided with an inverter IV30 for inverting the level of the control signal EQy.

FIG. 16 is a circuit diagram showing a fifth example of a conventional semiconductor memory device.

In the fifth example, instead of the control signal EQx in the second example (FIG. 13), memory cells MC11 to M are provided.
Column selection signals Y1 to Y corresponding to each of the plurality of examples of Cmn
Transistors T20, T31x, T32x of the balancer circuit and the precharge circuit depending on the level inversion signal of n.
To control the balancer circuit 21y.
Each of ~ 2ny is provided with an inverter IV20 for generating a level inversion signal of the column selection signals Y1 to Yn.

In the fifth example, since the precharge and balance operations of the first and second bit lines are performed only in the selected example, the power consumption due to the charge and discharge thereof is reduced.

FIG. 17 is a circuit diagram showing a sixth example of a conventional semiconductor memory device.

In the sixth example, instead of the control signal EQy in the fourth example (FIG. 15), memory cells MC11 to M are provided.
Column selection signals Y1 to Y corresponding to each of the plurality of examples of Cmn
Depending on the level inversion signal of n, the balancer circuits 21y-2
The balancer circuits 21y to 2ny are each provided with an inverter IV20 for generating a level inversion signal of the column selection signals Y1 to Yn.

In the sixth example, the precharge potentials of the first and second bit lines are lower than the power supply potential VCC by the threshold voltage of the N-channel transistor, which enables high-speed operation and can be selected. Since the precharge and balance operations of the first and second bit lines only in the selected column are performed, the power consumption is reduced.

[0021]

The conventional semiconductor memory device described above precharges the first and second bit lines,
At least three transistors are required for each column in order to achieve balance, and the column spacing and the bit line spacing are becoming narrower in an environment where miniaturization progresses. It is said that the space and arrangement position are limited, the size and shape of these transistors are limited, and it is difficult to improve the operating speed, and it is difficult to maintain and improve the operating speed against the increase of the parasitic capacitance and parasitic resistance of the bit line due to the increase of the capacitance. The problem is that it is difficult to arrange these transistors at optimum positions on the bit line due to their characteristics (for example, operating speed), and it is difficult to improve the characteristics, and the connection between these transistors and other layers is difficult. Therefore, it is difficult to obtain an appropriate space and arrangement position for the connection, and there is a problem that the reliability of the connection is likely to decrease.

Further, since the precharge circuit is provided corresponding to the first and second bit lines (bit line pairs) forming a plurality of pairs, measures for improving precharge characteristics, such as precharge timing and current, are provided. There is a problem that it is difficult to take measures such as adjustment and setting of driving ability (speedup, adjustment for manufacturing variations).

A first object of the present invention is to reduce the number of precharging and balancing transistors corresponding to each of a plurality of pairs of first and second bit lines (bit line pairs) to reduce the number of these transistors. A second object of the present invention is to provide a semiconductor memory device capable of improving characteristics and reliability by relaxing restrictions on size, shape, arrangement position and the like. A second object is to easily take measures to improve precharge characteristics. It is to provide a semiconductor memory device.

[0024]

SUMMARY OF THE INVENTION A semiconductor memory device of the present invention includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each corresponding to a plurality of columns of memory cells. First and second pairs that carry data
A plurality of bit line pairs, and one of the source and the drain provided corresponding to each of the plurality of bit line pairs is connected to the first and second bit lines of the corresponding bit line pair. A plurality of balancers, which are commonly connected to each other and have first and second transistors which are turned on and off when receiving a first control signal at their gates and which balance the potentials of the first and second bit lines at predetermined timings. Circuit,
One of the source and drain receives a predetermined potential, the other is commonly connected to the other of the sources and drains of the first and second transistors of each of the plurality of balancer circuits, and the gate receives the second control signal. Turn on and off third
And a precharge circuit that supplies a predetermined potential to the other of the sources and drains of the first and second transistors at a predetermined timing. Further, the precharge circuit is provided with a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a memory cell of a corresponding row provided corresponding to each of the plurality of rows of the plurality of memory cells is selected in a row unit. A plurality of word lines and a pair of first and second bit lines provided corresponding to the plurality of columns of the plurality of memory cells and transmitting data of the memory cells in the selected state of the corresponding columns. The memory cell array block including a plurality of bit line pairs is formed in a region outside the formation region.

In the precharge circuit, the source receives the power supply potential, the gate receives the second control signal, and the drain is connected to the other of the sources and drains of the first and second transistors of each of the plurality of balancer circuits. A circuit including a P-channel type third transistor for supplying the power supply potential to the other of the source and the drain of the first and second transistors during the active level period of the second control signal. An N-channel third transistor having a drain receiving a power supply potential and a gate receiving a second control signal, and a source connected to the other of the source and the drain of the first and second transistors of each of the plurality of balancer circuits. A source of the first and second transistors, and the other of the drains of the first and second transistors during the active level period of the second control signal. Potential to configured as a circuit for supplying a potential lower by the threshold voltage of said third transistor.

A plurality of precharge circuits receive power supply potentials different from each other at one of the source and the drain and receive a control signal corresponding to the gate, and commonly connect the other of the source and the drain as a drive end of the balancer circuit. It is configured as a circuit including the transistor.

In addition, the precharge circuit includes a plurality of transistors, activation of each of the plurality of transistors,
A circuit including a current drivability control means for controlling deactivation to control the current drivability of the balancer circuit. The current drivability control means is provided corresponding to each of the plurality of transistors and can be disconnected in a predetermined process. Configured as a fuse element.

A plurality of switch circuits are provided corresponding to each of the plurality of bit line pairs to control connection / disconnection between the corresponding bit line pair and the sense amplifier according to a corresponding column selection signal. Of the first and second transistors of each of the balancer circuits in place of the second control signal, the first and second transistors being generated from the corresponding column selection signal and disconnecting the switch circuit. Is configured to transmit a column-corresponding control signal for turning on the transistor.

[0029]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

The difference of the first embodiment from the conventional semiconductor memory device shown in FIG. 11 is that the balancer circuit 2 is used.
In place of 1X to 21nx, one of the source and the drain is associated with each of a plurality of bit line pairs formed by a pair of first and second bit lines (BL11, BL12 to BLn1, BLn2). The first and second bit lines of the bit line pair are connected to each other and the other is commonly connected, and the gate receives the first control signal EQ1 to turn on / off.
Channel type first and second transistors T21, T2
The first of the bit line pairs provided with 2 and corresponding at a predetermined timing
And a plurality of balancer circuits 21 to 2n for balancing the potentials of the second bit lines, and the precharge circuits 31 to 3n.
Instead of n, the source receives the power supply potential VCC and the drain is commonly connected to the other of the sources and drains of the transistors T21 and T22 of each of the plurality of balancer circuits 21 to 2n, and the gate receives the second control signal EQ2. A precharge circuit 30 that includes a third transistor T30 that turns on and off and that supplies a power supply potential VCC to the other of the sources and drains of the transistors T21 and T22 of each of the plurality of balancer circuits 21 to 2n at a predetermined timing is provided. Cells MC11 to MCmn, word lines WL1 to WLm
And paired first and second bit lines BL11, BL1
2 to BLn1 and BLn2 are formed and provided in an area outside the formation area of the memory cell array 10.

Next, the operation of the first embodiment will be described with reference to the timing charts shown in FIGS. 2 and 3.

First, after the memory cell MC11 is selected and its read operation is completed, the same bit lines BL11, B
The case of FIG. 2 in which the memory cell MCm1 on L12 is selected and the read state is connected (the write / read signal WR remains at the high level) will be described. Here, for convenience, it is assumed that the memory cell MC11 holds data of "0" level (low level) on the bit line BL11 side and the memory cell MCm1 holds data of the opposite "1" level (high level).

Column selection signal Y1 and word lines WL1 to WL
During the period when m is at the non-selection level (t1 in FIG. 2), the bit lines BL11, BL12 to BLn1 and BLn2 are at the power supply potential VCC level by the transistors T61 and T62 which are always on, and the address signal AD Due to the change of the address value, the paired first and second bit lines are balanced.

When the memory cell MC11 is selected by the word line WL1 and the column selection signal Y1 (t2 in FIG. 2), a current flows from the bit line BL11 into the memory cell MC11 and the bit line BL11 becomes low level, while The bit line BL12 remains at the power supply potential VCC (FIG. 2-t).
3). The difference potential between the bit lines BL11 and BL12 is amplified by the sense amplifier 51 and output to the outside.

Next, in order to select the memory cell MCm1,
When the address value of the address signal AD changes (t in FIG.
4) Upon detection of this, an active level (low level) one-shot pulse is generated in the control signal EQ1. During the generation of this one-shot pulse (t5 in FIG. 2), the transistors T21 and T22 are turned on and the bit line BL11,
BL12 is balanced and transistors T61, T
62, the power supply potential becomes VCC level (t in FIG. 2).
6). After balancing the bit lines BL11 and BL12,
When the word line WLm is at the selection level while the column selection signal Y1 remains at the selection level and the memory cell MCm1 is selected, the bit line BL12 is at the low level this time, and the bit line BLm.
11 remains at the power supply potential VCC (t7 in FIG. 2), and the difference potential between the bit lines BL11 and BL12 is the sense amplifier 51.
Amplified by and output to the outside.

Next, after the memory cell MC11 is selected and its write operation is completed, the memory cell MCm1 is selected to be in the read state (WR is low level when MC11 is selected, high level when MCm1 is selected). The case will be described. Here, for convenience, it is assumed that the memory cell MCm1 holds "1" level data.

Column selection signal Y1 and word lines WL1 to WL
During the period when m is at the non-selection level, the bit lines BL11 and BL12 are balanced to the power supply potential level, as in the case of FIG.

When the memory cell MC11 is selected by the column selection signal Y1 and the word line WL1 (FIG. 3-t1), the output signal from the write circuit 70 causes the bit line BL11 to the output signal from the write circuit 70 to cause the bit line BL1 to pass.
The current flows from 1 to the write circuit 70, and the bit line BL
11 is a low level of VSS level, the bit line BL12 is kept at the power supply potential VCC, and writing to the memory cell MC11 is performed (t2 in FIG. 3).

Next, when the address value of the address signal AD changes in order to select the memory cell MCm1, and the write / read signal WR changes to high level in order to read the data held in this memory cell MCm1 (see FIG. 3). At t3), the control signal EQ1 detects a change in the address value, and the control signal EQ2 detects a change from the write state to the read state, so that an active level (low level) one-shot pulse is generated. As a result, the transistor T2
1, T22, T30 are turned on, current flows from the precharge circuit 30 to the bit line BL11, the bit line BL11 rapidly becomes the power supply potential VCC level, and the bit lines BL11, 12 are balanced to the power supply potential level (FIG. 3). T5).

After precharging and balancing the bit lines BL11 and BL12, when the memory cell MCm1 is selected by the word line WLm, the bit line BL12 becomes low level this time, and MCm1 is the same as in the case of FIG.
The stored data of is output to the outside.

In the first embodiment, the pair of first and second bit lines (BL11, BL12 to BL12) is used.
n1, BLn2) corresponding to each of a plurality of bit line pairs, only the balancer circuits (21 to 2n) from the two transistors T21 and T22 need to be arranged. 1 for pair
In addition, the precharge circuit 30 includes the memory cell array 10, the word lines WL1 to WLm, and the bit line B.
Since it is formed in a region outside the formation region of the memory cell array block including L11, BL12 to BLn1 and BLn2, the number of precharge and balance transistors arranged in each of a plurality of bit line pairs can be determined by the conventional semiconductor memory. The number of devices can be reduced to ⅔, the size and shape of these transistors, the arrangement position, etc. can be relaxed accordingly, and the characteristics and the reliability can be improved.

In the first embodiment, the control signal EQ1 is changed to the change of the address value of the address signal AD,
The control signal EQ2 is used as a signal for generating an active level (low level) one-shot pulse in response to a change from the write state to the read state, and the control signal EQ2 is set to an active level (low level) in response to a change from the write state to the read state. The control signals EQ1 and E1 are used as signals for generating shot pulses.
Q2 is a write enable signal or write / read signal from the outside of this semiconductor memory device, a chip enable signal, various signals generated in synchronization with a change in address value of an address signal, and the like, and various signals generated based on these signals. The signal can be used, or it can be one signal. However, during the period of precharging the bit lines BL11, BL12 to BLn1 and BLn2 by the precharge circuit 30, the transistors T21 and T22 of the balancer circuits 21 to 2n need to be turned on.

FIG. 4 is a circuit diagram of a precharge circuit portion according to the second embodiment of the present invention. The other parts are similar to those of the circuit shown in FIG.

The precharge circuit 30a of the second embodiment is a P-channel type transistor T which receives the power supply potential VCC1 at the source and the control signal EQ2a at the gate.
31 and a source that receives a power supply potential VCC2 different from the power supply potential VCC1 and a gate that receives a control signal EQ2b, the drain is connected to the drain of the transistor T31, and these drains are connected to the transistor T2 of the balancer circuits 21 to 2n.
It has a configuration including a P-channel type transistor T32 connected to the other common connection point of the sources and drains of 1 and 22.

In the second embodiment, the control signals EQ2a and EQ2b are, for example, signals according to the operation timing of the internal circuit, so that the transistor T3 can be obtained.
1, bit lines BL11, BL12 to BLn by T32
By setting precharge of 1 and BLn2 as a signal according to the operation timing of the internal circuit, the transistor T3
1, bit lines BL11, BL12 to BLn by T32
Since 1 and BLn2 can be precharged according to the operation timing of the internal circuit and these bit lines can be precharged to different potentials, various characteristics including the operation speed can be improved. You can Here, by making the current driving capability of the transistors T31 and T32 sufficiently larger than that of the transistors T61 and T62, the precharge potential and the precharge timing of the bit line can be forcibly controlled by the precharge circuit 30a. However, during the precharge period of the bit line by the precharge circuit 30a, the transistors T21 and T22 of the balancer circuits 21 to 2n need to be turned on.

In the second embodiment,
The power supply potential is VCC1, VCC2, the control signal is EQ2a,
Although the circuit example using the transistors T31 and T32 as the EQ2b has been described, the present invention is not limited to these and supplies different potentials to the balancer circuit under the control of a plurality of signals from peripheral circuits. Any circuit can be used.

FIG. 5 is a circuit diagram of a precharge circuit portion according to the third embodiment of the present invention. The other parts are similar to those of the circuit shown in FIG.

The precharge circuit 30b of the third embodiment includes P-channel type transistors T31 and T32 having sources which receive the power supply potential VCC and gates which receive the control signal EQ2 and which have different current driving capabilities. ,
One ends of the transistors T31 and T32 are connected to the drains of the transistors T31 and T32, respectively, and the other ends of the transistors T21 and T22 of the balancer circuits 21 to 2n are connected together.
And a fuse F31, F32 which can be cut by a laser or the like and which is connected to the other common connection point of the source and the drain.

In the third embodiment, the fuses F31 and F32 are cut or uncut in the state of a wafer or the like, for example, only the fuse F31 is cut so that the driving capability of the transistor T32 and the fuse Transistor T3 by cutting off only F32
By not disconnecting the driving capability of 1 and the fuses F31 and F32, the precharge circuit 30b having the driving capability of the transistors T31 and T32 can be obtained. That is, the balancer circuit 2 based on the precharge circuit 30b
1-2n, therefore bit lines BL11, BL12-BL
Since the driving ability of 1, BLn2 can be adjusted,
Manufacturing variations and fluctuations can be suppressed, and characteristics can be improved.

Incidentally, in the third embodiment,
Fuses F31, F32 and transistors T31, T3
Although the circuit example according to 2 has been described, the present invention is not limited to this, and any precharge circuit whose current driving capability can be adjusted may be used. In addition to the fact that the number of precharge circuits is reduced, the circuits can be formed in an area outside the memory cell array block in that the characteristics can be improved by the second and third embodiments. This is because the restriction on the space is further relaxed, which means that only the balancer circuit needs to be provided in each bit line pair forming region.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention.

In the fourth embodiment, the present invention is applied to the conventional semiconductor memory device shown in FIG. 14, and instead of the balancer circuits 21x to 2nx, the first embodiment shown in FIG. The balancer circuits 21 to 2n of the embodiment are provided, and instead of the precharge circuits 31x to 3nx, the drain receives the power supply potential VCC and the gate receives the level inversion signal EQ2 * of the control signal EQ2 and the source is the balancer circuit 21.
.About.2n transistors T21 and T22 including an N-channel type transistor T30a connected to the other common connection point of the sources and drains, and the balancer circuits 21 to 2n when the control signal EQ2 * is at the active level (high level). Via the bit lines BL11, BL12 to BLn1, BLn
2 is precharged to a potential lower than the power supply potential VCC by the threshold voltage of the transistor T30a.
L1 to WLm and bit lines BL11, BL12 to BLn
It is formed and provided in a region outside the formation region of the memory cell array block including 1 and BLn2.

In the fourth embodiment, the precharge potential of the bit lines BL11, BL12 to BLn1, BLn2 is the transistor T30 with respect to the power supply potential VCC.
The operation and effect are basically the same as those of the first embodiment except that the threshold voltage of a is lower than that of the first embodiment.
Further description will be omitted.

FIG. 7 is a circuit diagram of a precharge circuit portion according to the fifth embodiment of the present invention, and the other portions are similar to the circuit shown in FIG.

In the fifth embodiment, the transistors T33 and T34 of the precharge circuit 30d are of N-channel type, and the bit lines BL11 and BL12 ...
The precharge potential of BLn1 and BLn2 is the power supply potential V
Transistors T33 and T34 for CC1 and VCC2
Since the operation and effect are basically the same as those of the second embodiment except that the threshold voltage is decreased by the threshold voltage, the further description will be omitted.

FIG. 8 is a circuit diagram of a precharge circuit portion according to the sixth embodiment of the present invention, and the other portions are similar to the circuit shown in FIG.

In the fifth embodiment, the transistors T33 and T34 of the precharge circuit 30e are N-channel type, and the bit lines BL11 and BL12.about.
The precharge potential of BLn1 and BLn2 is the power supply potential V
The operation and effect are basically the same as those of the third embodiment except that the threshold voltage of the transistors T33 and T34 is lower than that of CC, and therefore further description is omitted.

FIG. 9 is a circuit diagram showing a seventh embodiment of the present invention.

In the seventh embodiment, the present invention is applied to the conventional semiconductor memory device shown in FIG.
Transistors T21 and T of each of the plurality of balancer circuits
22 gates are driven by the level inversion signals of the corresponding column selection signals (Y1 to Yn), and the corresponding column selection signals (Y1 to Yn) are driven.
Yn) is the same as that of the first embodiment shown in FIG. 1 except that it includes an inverter IV20 that inverts the level of Yn) to form balancer circuits 21a to 2na.

The operation and effect of the seventh embodiment are basically the same as those of the first embodiment.

Further, the precharge circuits 30a and 30b of the second and third embodiments can be applied to the precharge circuit.

FIG. 10 is a circuit diagram showing an eighth embodiment of the present invention.

In the seventh embodiment, the present invention is applied to the conventional semiconductor memory device shown in FIG.
The plurality of balancer circuits 21a to 2na are the same as the circuit of FIG. 9, and the precharge circuit 30c is the same as the circuit of FIG.

The operation and effect of the eighth embodiment are basically the same as those of the first embodiment. Further, the precharge circuits 30d and 30e of the fifth and sixth embodiments can be applied to the precharge circuit.

[0066]

As described above, according to the present invention, a balancer circuit composed of two transistors is provided corresponding to each of a plurality of bit line pairs, and a plurality of balancer circuits are driven by one precharge circuit. By precharging and balancing the bit line pairs of, it is possible to reduce the number of transistors for precharging and balancing corresponding to each of the plurality of bit line pairs to about 2/3 of that of the conventional example. To that extent, restrictions on the size, shape, and arrangement position of these transistors can be relaxed,
Therefore, there is an effect that the characteristics and the reliability can be improved.

Further, one precharge circuit provided for a plurality of bit line pairs is formed in a region outside the formation region of the memory cell array block including the memory cell array, the plurality of word lines and the plurality of bit line pairs. With such a configuration, the space limitation of the precharge circuit and the balancer circuit is further relaxed, so that the above effect can be further promoted, and the circuit configuration of the precharge circuit, such as modification and adjustment function, can be further enhanced. This has the effect of making it easier to take special measures and facilitating adjustment and setting of the precharge potential, precharge timing, current drive capability, etc., and improving various characteristics.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a first timing chart of signals of respective parts for explaining the operation of the first embodiment shown in FIG.

FIG. 3 is a second timing chart of signals of respective parts for explaining the operation of the first embodiment shown in FIG.

FIG. 4 is a circuit diagram of a precharge circuit portion according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a precharge circuit portion according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a precharge circuit portion according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram of a precharge circuit portion according to a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing an eighth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a first example of a conventional semiconductor memory device.

12 is a circuit diagram showing a specific example of a memory cell of the semiconductor memory device shown in FIG.

FIG. 13 is a circuit diagram of a precharge / balancer circuit portion of a second example of the conventional semiconductor memory device.

FIG. 14 is a circuit diagram showing a third example of a conventional semiconductor memory device.

FIG. 15 is a circuit diagram of a precharge / balancer circuit portion of a fourth example of a conventional semiconductor memory device.

FIG. 16 is a circuit diagram showing a fifth example of a conventional semiconductor memory device.

FIG. 17 is a circuit diagram showing a sixth example of a conventional semiconductor memory device.

[Explanation of symbols]

10 memory cell arrays 21 to 2n, 21a to 2na, 21x to 2nx, 21y
~ 2ny balancer circuit 30, 30a to 30e, 31 to 3n, 31x to 3nx,
31y to 3ny, 31z to 3nz Precharge circuit 41 to 4n Switch circuit 51 to 5n Sense amplifier 61 to 6n, 61x to 6nx Load circuit 70 Write circuit BL11, BL12 to BLn1, BLn2 Bit line MC11 to MCmn Memory cell WL1 to WLm Word line

Claims (8)

[Claims] 1. A first pair and a second pair which are provided corresponding to a plurality of columns of a plurality of memory cells arranged in a plurality of rows and a plurality of examples and which transmit data of memory cells in a selected state of a corresponding column. A plurality of bit line pairs each including a plurality of bit lines, and one of a source line and a drain line provided corresponding to each of the plurality of bit line pairs.
And first and second transistors correspondingly connected to the second bit line and commonly connected to the other and having the gate receiving and receiving the first control signal to turn on and off the first and second bits at a predetermined timing. A plurality of balancer circuits for balancing the potentials of the lines, and one of the source and the drain for receiving a predetermined potential and the other for the other of the sources and drains of the first and second transistors of each of the plurality of balancer circuits. A third transistor, which is commonly connected and turns on and off by receiving a second control signal at its gate, is provided, and a predetermined potential is supplied to the other of the sources and drains of the first and second transistors at a predetermined timing. A semiconductor memory device having a precharge circuit. 2. A precharge circuit is provided with a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and a plurality of rows of the plurality of memory cells are provided corresponding to each memory cell of the corresponding row. And a pair of first and second bit lines which are provided in correspondence with a plurality of columns of the plurality of memory cells and which transmit data of the memory cells in a selected state of a corresponding column. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed in a region outside a formation region of a memory cell array block including a plurality of bit line pairs each formed of a line. 3. A precharge circuit, wherein a source receives a power supply potential and a gate receives a second control signal, and a drain is connected to the other of the sources and drains of the first and second transistors of each of the plurality of balancer circuits. And a P-channel type third transistor for supplying the power supply potential to the other of the source and the drain of the first and second transistors during the active level period of the second control signal. Item 2. The semiconductor memory device according to item 1. 4. A precharge circuit, wherein a drain receives a power supply potential and a gate receives a second control signal, and a source is connected to the other of the sources and drains of the first and second transistors of each of the plurality of balancer circuits. A third transistor of an N-channel type for controlling the power supply potential to the other of the source and the drain of the first and second transistors during the active level of the second control signal. 2. The semiconductor memory device according to claim 1, wherein the circuit supplies a potential lower by the threshold voltage of the transistor. 5. A plurality of precharge circuits, each of which has a source and a drain receiving a power supply potential different from each other, receives a control signal corresponding to a gate, and commonly connects the other of the source and the drain as a drive end of the balancer circuit. The semiconductor memory device according to claim 1, which is a circuit including the transistor. 6. The precharge circuit is a circuit including a plurality of transistors and a current drivability control means for controlling the current drivability of the balancer circuit by controlling activation and deactivation of each of the plurality of transistors. Item 2. The semiconductor memory device according to item 1. 7. The semiconductor memory device according to claim 6, wherein the current drivability control means is a fuse element provided corresponding to each of the plurality of transistors and capable of being cut in a predetermined process. 8. A plurality of switch circuits, each of which is provided corresponding to each of the plurality of bit line pairs and includes a plurality of switch circuits for controlling connection / disconnection between the corresponding bit line pair and a sense amplifier in accordance with a corresponding column selection signal, First of each balancer circuit
And the gates of the second transistors, instead of the second control signal, make the first and second transistors conductive during a period in which the switch circuit is disconnected from the corresponding column selection signal. The semiconductor memory device according to claim 1, wherein a column-corresponding control signal is transmitted.