JPH09307369A - Current mirror circuit and constant current driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constant current driving circuit allowing a constant current to surely flow through an electrical load through power source voltage and the resistance value of the electrical loads are fluctuated. SOLUTION: The respective gates of two FETs 1 and 2 are mutually connected and the gate and the drain of one FET 1 are connected to constitute a current mirror circuit to allow the current of a value in proportion to a reference current I ref to flow to FET 1 flow through an electrical load R through the other FET 2. In this case, third FET 3 is serially provided between the drain of FET 2 and the electrical load R, and an arithmetic amplifier 4 the noninverted input terminal of which is connected to the drain of FET 1, the inverted input terminal of which is connected to the drain of FET 2 and the output terminal of which is connected to the gate of FET 3. As the result of this, voltages between both of the source and drain of FETs 1 and 2 are always equal to each other to allow a constant current to surely flow through the electrical load R without receiving the influence of a channel length modulating effect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current drive circuit that uses a field effect transistor to flow a constant current through an electric load.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 11A, for example, a current mirror circuit 103 is composed of two field effect transistors (hereinafter also referred to as FETs) 101 and 102.
There is known a constant current drive circuit configured to flow a constant current through the electric load R. In addition, in FIG.
The case where the current mirror circuit 103 is configured by the MOS-FETs 101 and 102 of the channel is illustrated. Further, in FIG. 11 and each of the drawings described below, “D” indicates the drain terminal of the FET, “G” indicates the gate terminal of the FET, and “S” indicates the source terminal of the FET.

That is, the current mirror circuit 103 includes a first FET 10 having a gate terminal and a drain terminal connected to each other.
1 and a second FET 102 having the same polarity as that of the first FET 101 and having a gate terminal connected to the gate terminal of the first FET 101.
The two source terminals are both connected to a predetermined potential (ground potential: GND in this example).

And, such a current mirror circuit 1
In the constant current drive circuit using 03, the first FET1
A constant current source 104 having a predetermined reference power source Vref as a power source is provided between the source terminal and the drain terminal of 01.
A predetermined reference current Iref flows and a power source (second predetermined potential) different from the above predetermined potential Vx (the above Vre
The drain terminal of the second FET 102 is connected to the other end of the electric load R whose one end is connected to the electric load R.
A constant load current IL proportional to the reference current Iref flows through the drain terminal of the ET 102.

Here, the current mirror circuit 1 as described above is used.
The operation principle of No. 03 will be described. First, MOS-FE
The source-drain current IDS in the saturation region of T is
It is represented by the following formula (1).

[0006]

[Equation 1]

However, in the equation (1), μ is the carrier mobility, ε _OX is the dielectric constant of the gate oxide film, t _OX is the gate oxide film thickness, Vth is the threshold voltage, L is the channel length, and W is The channel width, VGS is the gate-source voltage, VDS is the source-drain voltage, and λ is the channel length modulation effect coefficient.

As can be seen from the equation (1), in the saturation region, the source-drain current IDS of the MOS-FET is
Is not always constant with respect to the gate-source voltage VGS, but slightly fluctuates according to the source-drain voltage VDS. This phenomenon is called a channel length modulation effect and is represented by the channel length modulation effect coefficient λ in the above equation (1).

Next, in the current mirror circuit 103, as shown in FIG. 11A, since the gate terminal and the drain terminal of the first FET 101 are connected, this first FET 101 is in the saturation region. Operate. Therefore, the first
If the FET 101 and the second FET 102 are formed on the same semiconductor chip, the characteristics of both FETs 101 and 102 are uniform, and if the second FET 102 is also operated in the saturation region, Source-drain current IDS of FET 101 (that is, reference current Iref)
And the source-drain current IDS of the second FET 102
(That is, the ratio (IL / Iref) to the load current IL) is neglected by the channel length modulation effect (that is, both FETs 10).
If the source-drain voltage VDS of 1,102 is equal), the following equation (2) is obtained from the equation (1).

[0010]

[Equation 2]

However, in the formula (2), (W / L) a is the transistor size of the first FET 101, and
/ L) b is the transistor size of the second FET 102. As can be seen from the equation (2), the first FET 101
Source-drain current IDS of the second FET 102
Ratio of source-drain current IDS to (IL / Iref)
Is equal to the ratio ((W / L) b / (W / L) a) of the transistor sizes of the FETs 101 and 102.

Therefore, the reference current Iref is applied to the electric load R.
It is possible to flow a constant load current IL which is obtained by multiplying the transistor size ratio of both FETs 101 and 102 ((W / L) b / (W / L) a). This is the principle of the current mirror circuit. As described above, in the constant current drive circuit using the current mirror circuit 103 as shown in FIG.
If the source-drain voltages VDS of T101 and T102 are equal, a desired constant current can be passed through the electric load R.

However, in reality, the voltage of the power source Vx to which one end of the electric load R is connected (hereinafter simply referred to as the power source voltage Vx
(also referred to as x) or the resistance value of the electric load R fluctuates due to temperature change or the like, the source-drain voltage VDS of the second FET 102 changes, and both FETs 101, 102
There is a problem that the source-drain voltage VDS is not equal to each other, and due to the influence of the channel length modulation effect accompanying this, a constant current cannot be surely passed through the electric load R.

For example, in the constant current drive circuit shown in FIG. 11A, the power supply voltage Vx on the electric load R side is the battery voltage of the automobile, the electric load R is 1 kΩ, and the electric load R is 2 mA. Constant current (load current IL
) Think about the case. In this case, both FET1
The transistor size ratio of 01 and 102 is 1 to 100.
(That is, (W / L) a: (W / L) b = 1: 100)
Then, the constant current source 104 causes the first FET 1
The reference current Iref flowing through 01 is set to 20 μA, and the second
A load current IL of 2 mA (= 20 μA × 100) is passed through the FET 102.

Here, the constant current drive circuit configured as described above was simulated by changing the power supply voltage Vx (battery voltage) on the electric load R side in the range from 6V to 18V and using the temperature as a parameter. The results are shown in Figure 1.
It is shown in FIG. In FIG. 12, the horizontal axis represents the power supply voltage Vx.
And the vertical axis shows the load current IL.

As is apparent from FIG. 12, FIG. 11 (A)
In the conventional constant current drive circuit shown in FIG.
The load current IL applied to the electric load R by 2 is the ratio of the reference current Iref to the transistor size ratio ((W / L) b /
It can be seen that the current does not become a constant current (2 mA) multiplied by (W / L) a, and that it fluctuates under the influence of the power supply voltage Vx and the ambient temperature.

The cause is that the source-drain voltage VDS of the first FET 101 is a voltage (about 1.5 V) determined according to the reference current Iref, whereas the source-drain voltage VDS of the first FET 101 is connected to the electric load R. The source-drain voltage VDS of the second FET 102 is 4V to 14V depending on the fluctuation of the power supply voltage Vx.
This is because it changes in a manner such as V. In other words, the two Fs that constitute the current mirror circuit 103.
This is an influence due to the channel length modulation effect accompanying a large difference in the source-drain voltage VDS of the ETs 101 and 102.

Although the load current IL fluctuates due to the fluctuation of the power supply voltage Vx on the electric load R side in the above description, the resistance value of the electric load R varies even if the power supply voltage Vx is constant. If the voltage fluctuates due to the ambient temperature, the source-drain voltage VDS of the second FET 102 changes, and the second FET is affected by the channel length modulation effect.
The source-drain current IDS of 102 changes, and as a result, a predetermined constant current cannot flow through the electric load R.

As described above, in the conventional constant current drive circuit,
Due to the influence of the channel length modulation effect in the second FET 102 connected to the electric load R, with respect to the fluctuation of the power supply voltage Vx on the electric load R side and the fluctuation of the resistance value of the electric load R,
The accuracy of constant current drive could not be ensured.

Therefore, in order to solve this problem, for example, Japanese Patent Application Laid-Open No. 2-124609 and Japanese Patent Application Laid-Open No. 4-1605.
In Japanese Patent No. 11 publication, as shown by the dotted line in FIG. 11A, the voltage of the drain terminal of the FET 102 connected to the electric load R (hereinafter referred to as the drain voltage) is monitored, and the load current flowing in the electric load R is monitored. FE so that IL becomes constant
It has been proposed to provide a control circuit 105 that changes the voltage of the gate terminal of T102 (hereinafter referred to as the gate voltage).

[0021]

However, in the technique disclosed in the above publication, as shown in FIG.
In addition to the FET 102 of, the gate terminal has a first F
Additional FET10 connected to the gate terminal of ET101
6 is provided and a configuration is adopted in which a constant current is supplied to another electric load R ′ via the drain terminal of the FET 106, that is, when one constant current source 104 is shared and a plurality of current mirror circuits are configured. Cannot supply a constant current to each of the electric loads R and R '.

That is, in this case, as shown in FIG. 11 (B), the control circuit 107 similar to the control circuit 105 is provided for the additional FET 106 as well, but with this configuration. , For example, one electric load R
Of the second FE is changed by the control circuit 105.
When the gate voltage of T102 is changed, the first FET1
The reference current Iref flowing through 01 also changes, and the gate voltage of the additional FET 106 connected to the other electric load R ′ also changes, and as a result, the value of the current flowing through the other electric load R ′ is unnecessary. Will be adjusted to.

Therefore, in the technique disclosed in the above publication, when a constant current is applied to each of the plurality of electric loads R and R ', one constant current source 104 as shown in FIG.
It is not possible to adopt a configuration in which each electric load R,
It is necessary to adopt the configuration shown in FIG. 11A for each R '.
As a result, the circuit scale becomes large, and moreover, the current consumption of the entire circuit becomes large due to the provision of a plurality of constant current sources 104.

On the other hand, not only the current mirror circuit 103 shown in FIG. 11A, but also the source terminal is connected to a predetermined potential (ground potential: GND in this example) as shown in FIG. 13A, for example. The drain terminal of the FET 108 is connected to the other end of the electric load R, one end of which is connected to the power supply voltage Vx different from the predetermined potential, and
By applying a predetermined gate voltage (gate-source voltage VGS) to the gate terminal of 08, the FET 108 is operated in the saturation region, whereby the electric load R
It is also conceivable to flow a constant current according to the gate-source voltage VGS of 108. In this example, F
An N-channel MOS-FET is used as the ET 108, and a predetermined reference voltage Vref is divided by the two resistors 109 and 110 at the gate terminal of the FET 108 to apply a predetermined gate voltage. .

Also in the case of the structure shown in FIG. 13A, the source-drain voltage V of the FET 108 is changed by the fluctuation of the power supply voltage Vx and the fluctuation of the resistance value of the electric load R.
When DS changes, due to the effect of channel length modulation effect,
The load current IL flowing through the electric load R fluctuates, and constant current drive becomes impossible.

Therefore, even in the case of this configuration, the technique disclosed in the above publication is applied, and as shown by the dotted line in FIG. 13 (A), between the drain terminal and the gate terminal of the FET 108, as shown in FIG. Control circuit 1 similar to the control circuit 105 shown
It is possible to provide 11.

However, in the technique disclosed in the above publication, as shown in FIG. 13B, in addition to the FET 108, an additional FET 112 whose gate terminal is connected to the connection point of the resistors 109 and 110 is provided, and When a configuration is adopted in which a constant current is passed to another electric load R ′ via the drain terminal of the FET 112, that is, a plurality of FETs 108, 11
When the bias circuit for the gate voltage composed of the resistors 109 and 110 is shared by 2, the constant current cannot flow through each of the electric loads R and R '.

That is, also in this case, as shown in FIG. 13B, the control circuit 113 similar to the control circuit 111 is provided for the additional FET 112.
With this configuration, for example, when the resistance value of one electric load R changes and the gate voltage of the FET 108 is changed by the control circuit 111, the gate voltage of the other FET 112 also changes. As a result, The FET 112
The electric current value flowing through the electric load R ′ connected to the drain terminal of the device changes.

Therefore, in the technique disclosed in the above publication, when a constant current is intended to flow through each of the plurality of electric loads R and R ', one bias circuit (resistor as shown in FIG. 13B) is used. 109, 110) cannot be adopted in common, and it is necessary to adopt the configuration shown in FIG. 13A for each electric load R, R ', which increases the circuit scale and current consumption. is there.

The present invention has been made in view of these various problems, and ensures that a predetermined constant current flows through the electric load even if the power supply voltage of the electric load or the resistance value of the electric load itself fluctuates. It is an object of the present invention to provide a constant current drive circuit capable of providing a constant current to a plurality of electric loads with a simple configuration and a current mirror circuit suitable for configuring the constant current drive circuit. I am trying.

[0031]

Means for Solving the Problems and Effects of the Invention A current mirror circuit according to claim 1 made to achieve the above object is the same as the conventional current mirror circuit 103 shown in FIG. A first field effect transistor having a gate terminal and a drain terminal connected to each other;
And a second field effect transistor having the same polarity as that of the field effect transistor and having a gate terminal connected to the gate terminal of the first field effect transistor.
Both source terminals of the second field effect transistor and the second field effect transistor are connected to a predetermined potential, and a third field effect transistor having the same polarity as the first and second field effect transistors and an operational amplifier are further provided. I have it.

The source terminal of the third field effect transistor is connected to the drain terminal of the second field effect transistor, and the non-inverting input terminal, the inverting input terminal, and the output terminal of the operational amplifier are respectively The non-inverting input terminal is connected to the drain terminal of the first field effect transistor,
The inverting input terminal is connected to the drain terminal of the second field effect transistor, and the output terminal is connected to the gate terminal of the third field effect transistor.

In the current mirror circuit according to the first aspect of the present invention configured as described above, a predetermined reference current is caused to flow between the source terminal and the drain terminal of the first field effect transistor, and the first and second fields are formed. If a potential difference is applied between the source terminal of the field effect transistor and the drain terminal of the third field effect transistor, the operation is as follows.

First, since the gate terminal and the drain terminal of the first field effect transistor are connected, the first field effect transistor operates in the saturation region, and the gate voltage and the drain voltage of the first field effect transistor are the reference current (that is, the first voltage). It has a value corresponding to the source-drain current IDS of the field effect transistor. Since the gate terminal of the first field effect transistor and the gate terminal of the second field effect transistor are connected to each other, the gate voltage of the second field effect transistor is equal to the gate voltage of the first field effect transistor. Is equal to

On the other hand, the gate voltage of the third field effect transistor is controlled by an operational amplifier so that the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor become equal. Will be applied. That is, the drain terminal of the first field effect transistor and the drain terminal of the second field effect transistor are virtually grounded by the operational amplifier.

Therefore, according to the current mirror circuit of the first aspect, even if the potential difference between the source terminals of the first and second field effect transistors and the drain terminal of the third field effect transistor changes. , The source-drain voltage of the third field effect transistor is adjusted so that the drain voltage of the second field effect transistor becomes equal to the drain voltage of the first field effect transistor. The source-drain voltage of the field effect transistor is always the same.

As a result, the first field effect transistor and the second field effect transistor are always equal in not only the gate-source voltage but also the source-drain voltage, whereby the second field effect transistor is the same. The current that can flow through the effect transistor (that is, the current that can flow between the source terminal of the second field effect transistor and the drain terminal of the third field effect transistor) is equal to the reference current value It is a constant value obtained by multiplying the ratio of the transistor sizes of the first field effect transistor and the second field effect transistor.

Therefore, by using the current mirror circuit according to claim 1, as described in claim 2, between the source terminal and the drain terminal of the first field effect transistor,
A predetermined reference current is caused to flow by a constant current source, and one end of the electric load is connected to a second predetermined potential different from the predetermined potential to which the source terminals of the first and second field effect transistors are connected. , If the drain terminal of the third field-effect transistor is connected and a current is caused to flow through the electric load through the drain terminal of the third field-effect transistor, the electric load is supplied with the reference current. It becomes possible to reliably flow a proportional constant current.

That is, according to the current mirror circuit of the first aspect, as described above, the potential difference between the source terminals of the first and second field effect transistors and the drain terminal of the third field effect transistor is reduced. Even if it changes, the source-drain voltages of the first and second field effect transistors are always the same, and the current flowing through the second field effect transistor has a constant value. When the current drive circuit is configured, even if the second predetermined potential to which one end of the electric load is connected changes or the resistance value of the electric load changes due to temperature change or the like, Third
The constant current can be passed through the drain terminal of the field effect transistor.

As described above, according to the constant current drive circuit of claim 2 using the current mirror circuit of claim 1, even if the power supply voltage of the electric load or the resistance value of the electric load itself fluctuates. Therefore, it becomes possible to reliably flow a predetermined constant current through the electric load. Moreover, according to the current mirror circuit of the first aspect, the above effect can be obtained without changing the gate voltages of the first and second field effect transistors at all.

Therefore, according to the constant current drive circuit of the second aspect, which uses the current mirror circuit of the first aspect,
Even if it is configured such that a portion including the first field effect transistor and the constant current source is shared and a plurality of driving portions including the second field effect transistor, the third field effect transistor, and the operational amplifier are provided, The gate voltage of the field effect transistor No. 1 is constant, and the respective drive parts operate independently. Therefore, a constant current can be surely flowed to each of the plurality of electric loads by the plurality of driving portions that share the portion including the first field effect transistor and the constant current source, which complicates the circuit configuration. It is possible to reduce the current consumption as well.

Next, in a constant current drive circuit according to a third aspect of the present invention, a first field effect transistor having a gate terminal and a drain terminal connected to each other, and the same field effect transistor as the first field effect transistor, and A current mirror circuit in which a gate terminal is formed of a second field effect transistor connected to the gate terminal of the first field effect transistor, and both source terminals of the first and second field effect transistors are both connected to a predetermined potential; A constant current source for supplying a predetermined reference current is provided between the source terminal and the drain terminal of the first field effect transistor.

In the constant current drive circuit according to a third aspect of the present invention, an electric load whose one end is connected to a second predetermined potential different from the predetermined potential is connected via a drain terminal of the second field effect transistor. Although a constant current is made to flow, a resistor having a predetermined resistance value is provided between the terminal of the electric load opposite to the second predetermined potential and the drain terminal of the second field effect transistor. The resistance value of the resistor provided in series is set to the source-drain voltage of the first field-effect transistor and the source-drain voltage of the second field-effect transistor when the constant current flows in the electric load. Are set to match.

That is, in the constant current drive circuit according to claim 3, in comparison with the constant current drive circuit according to claim 2,
In place of the field effect transistor and the operational amplifier of, a resistor is provided in series between the electric load and the drain terminal of the second field effect transistor, and a desired constant current flows in the electric load. In this case, the resistance value of the resistor is set so that the source-drain voltages of the first and second field-effect transistors substantially match.

Specifically, the predetermined potential to which the source terminals of both field effect transistors are connected is VS, the second predetermined potential to which the electric resistance is connected is Vx, and the source-drain voltage of the first field effect transistor. Is VDSa, IL is a constant current that should flow through the electric load, and RL is the resistance value of the electric load, the resistance value r of the above resistor is calculated by the following formula (3).
Is determined as follows.

[0046]

## EQU00003 ## r = (. Vertline.Vx-VS.vertline.-VDSa-RL.times.IL) / IL [.OMEGA.] (3) According to the constant current drive circuit of the third aspect,
Both the source and drain voltages of the first and second field effect transistors can be set to be equal regardless of the resistance value RL of the electric load, and as a result, the first field effect transistor and the second field effect transistor can be set to the same value as the reference current value. A constant current having a value obtained by multiplying the transistor size ratio with the field effect transistor can be surely passed through the electric load.

Further, according to the constant current drive circuit of the third aspect, even if the resistance value of the electric load fluctuates, the fluctuation amount is the second predetermined potential and the drain terminal of the second field effect transistor. Since the ratio becomes small with respect to the total resistance value between (and the sum of the resistance value of the electric load and the resistance value of the above resistor), a predetermined constant current is stabilized to the electric load. Can be washed away.

As described above, the constant current drive circuit according to the third aspect is effective when the second predetermined potential to which the electric load is connected is stable and only the fluctuation of the resistance value of the electric load matters. Therefore, despite the extremely simple structure, a constant current can be surely passed through the electric load.

Further, according to the constant current drive circuit of the third aspect, the above effect can be obtained without changing the gate voltages of the first and second field effect transistors. Therefore, as in the constant current drive circuit according to claim 2, a plurality of sets of the second field effect transistor and the resistor are provided while sharing the part of the first field effect transistor and the constant current source. Even with such a configuration, a plurality of sets of the second field effect transistor and the resistor can reliably flow a constant current to each of the plurality of electric loads, and the circuit configuration is not complicated. Low current consumption can be achieved.

Next, in a constant current drive circuit according to a fourth aspect of the present invention, a current determining field effect transistor having a source terminal connected to a predetermined potential, the current determining field effect transistor having the same polarity and the source. The voltage controlling field effect transistor whose terminal is connected to the drain terminal of the current determining field effect transistor, the inverting input terminal being connected to the drain terminal of the current determining field effect transistor, and the output terminal being the voltage controlling field effect transistor. An operational amplifier connected to the gate terminal of the transistor, and the drain terminal of the voltage control field effect transistor is connected to the other end of the electric load whose one end is connected to a second predetermined potential different from the predetermined potential. It is connected.

Then, the first bias means applies the first set voltage between the gate terminal and the source terminal of the current determining field effect transistor, and the second bias means applies the non-inversion of the operational amplifier. A second set voltage is applied between the input terminal and the source terminal of the current determining field effect transistor.

In the constant current drive circuit according to the fourth aspect of the present invention thus configured, a current flows through the electric load through the current determining field effect transistor and the voltage controlling field effect transistor. The current value is generally determined by the first set voltage (that is, the gate-source voltage) applied between the gate terminal and the source terminal of the current determining field effect transistor by the first bias means. That is, if the first set voltage applied by the first biasing means is set so that the current determining field effect transistor operates in the saturation region, as can be seen from the above-mentioned formula (1), the current determining This is because the load current that the field effect transistor can flow as the source-drain current is substantially determined according to the first set voltage as the gate-source voltage.

At this time, at the gate terminal of the voltage controlling field effect transistor, the voltage at the non-inverting input terminal of the operational amplifier is made equal to the drain voltage of the current determining field effect transistor by the operational amplifier. ,
A gate voltage is applied. That is, the non-inverting input terminal of the operational amplifier and the drain terminal of the field effect transistor for current determination are virtually grounded by the operational amplifier, and the second predetermined potential to which the electric load is connected fluctuates or the resistance value of the electric load is changed. So that the voltage at the non-inverting input terminal of the operational amplifier is equal to the drain voltage of the current-determining field-effect transistor, the source-drain voltage of the voltage-controlling field-effect transistor Is adjusted. As a result, the source-drain voltage of the current determining field effect transistor is applied between the non-inverting input terminal of the operational amplifier and the source terminal of the current determining field effect transistor by the second bias means. It is always equal to the set voltage.

Therefore, according to the constant current drive circuit of the fourth aspect, the current determining field effect transistor is:
The gate-source voltage VGS and the source-drain voltage VDS are calculated such that the source-drain current in the saturation region matches the constant current that should flow through the electric load, and the first set voltage is the gate obtained above. By setting the second set voltage so as to match the source-drain voltage VDS, which is the same as the source-to-source voltage VGS,
The channel length modulation effect of the current determining field effect transistor does not appear, and the constant current can always be passed through the electric load.

Further, according to the constant current drive circuit of the fourth aspect, the above effect can be obtained without changing the gate voltage of the current determining field effect transistor at all. Therefore, according to the constant current drive circuit of claim 4, the first and second bias means are commonly used, and the drive part is composed of the current determination field effect transistor, the voltage control field effect transistor, and the operational amplifier. Even if a plurality of transistors are provided, the gate voltage of each current determining field effect transistor is constant, and each driving portion operates independently. Therefore, a constant current can be surely flowed to each of the plurality of electric loads by the plurality of driving portions sharing the first and second bias means, and the circuit configuration is not complicated.

[0056]

Embodiments of the present invention will be described below with reference to the drawings. It is needless to say that the embodiments of the present invention are not limited to the following examples, and can take various forms as long as they belong to the technical scope of the present invention.

[First Embodiment] FIG. 1A is a circuit diagram showing a constant current drive circuit of the first embodiment. The constant current drive circuit according to the first embodiment is for supplying a constant current (load current IL) to an electric resistance R whose one end is connected to a predetermined power supply voltage (for example, the positive side of an automobile battery) Vx. And an N-channel MOS-FET (hereinafter simply referred to as FET) 1 as a first field effect transistor in which a gate terminal and a drain terminal are connected to each other and a source terminal is connected to a ground potential, and a gate terminal FET above
An N-channel MOS-FET (hereinafter simply referred to as FET) 2 as a second field effect transistor, which is connected to the gate terminal of 1 and the source terminal of which is connected to the ground potential;
The source terminal is connected to the drain terminal of the FET 2 and the drain terminal is connected to the terminal of the electric load R on the side opposite to the power supply voltage Vx. Called FET)
3, an operational amplifier 4 having a non-inverting input terminal connected to the drain terminal of the FET1, an inverting input terminal connected to the drain terminal of the FET2, and an output terminal connected to the gate terminal of the FET3. , And a current mirror circuit 5 including.

Further, in the constant current drive circuit of the first embodiment, a predetermined reference current Vre is used as a power source from the drain terminal to the source terminal of the FET1 to obtain a predetermined reference current Ire.
A constant current source 6 for flowing f is provided. At least the FET1 and the FET2 are formed on the same semiconductor chip, and the carrier mobility μ, the dielectric constant ε _{OX of} the gate oxide film, the gate oxide film thickness t _OX , and the threshold of the FETs 1 and 2 are both formed. The characteristics such as the value voltage Vth are the same. Also,
In the constant current drive circuit of the first embodiment, the electric load R is 1 kΩ and a constant current of 2 mA (load current IL ). And for this,
The reference current Iref flowing through the FET 1 by the constant current source 6 is set to 2
The transistor size ratio of FET1 and FET2 is set to 1: 100 while being set to 0 μA.

In the constant current drive circuit configured as described above, the load current IL is passed through the electric load R via the FET 2 and the FET 3, and at that time, it operates as follows. First, in the FET 1, since the gate terminal and the drain terminal are connected, the constant current source 6 causes the reference current I to flow.
When the ref flows, it operates in the saturation region and its gate voltage and drain voltage are changed to the reference current Ire.
It has a value corresponding to f (that is, the source-drain current of FET1). And the gate terminal of FET1 and FET
Since the gate terminal of 2 is connected to each other,
The gate voltage of 2 becomes equal to the gate voltage of FET1.

On the other hand, the gate voltage of the FET 3 is applied by the operational amplifier 4 so that the drain voltage of the FET 1 and the drain voltage of the FET 2 become equal. That is, the drain terminal of the FET1 and the drain terminal of the FET2 are virtually grounded by the operational amplifier 4, and the source-drain voltage of the FET3 is adjusted so that the drain voltage of the FET2 becomes equal to the drain voltage of the FET1. , Both sources of FET1 and FET2
The drain-to-drain voltage is always the same.

As a result, the FET1 and the FET2 are always equal in not only the gate-source voltage but also the source-drain voltage. Therefore, the source-drain current IDS1 (that is, the reference current Iref) of the FET1 and F
The ratio (IDS2 / IDS1 = IL / Iref) of the source-drain current IDS2 (that is, the load current IL) of ET2 is given by the following expression (4) from the above expression (1).

[0062]

(Equation 4)

However, in the equation (4), VDS1 is FET
1 is the source-drain voltage, VDS2 is the source-drain voltage of FET2, (W / L) 1 is the transistor size of FET1, and (W / L) 2 is the transistor size of FET2. Then, as described above, VDS1 = VDS2
It is.

As is clear from the equation (4), the load current IL that the FET2 can flow as the source-drain current IDS2 is the source-drain current I1 of the FET1.
FE is set to the value of the reference current Iref (= 20 μA) which is DS1.
Ratio of transistor sizes of T1 and FET2 ((W /
L) 2 / (W / L) 1 = 100).

Therefore, according to the constant current drive circuit of the first embodiment, even if the power supply voltage Vx on the electric load R side fluctuates or the resistance value of the electric load R fluctuates due to temperature change or the like, A constant load current IL (2 mA = 20 μA × 100) can be passed through the electric load R via FET2 and FET3.

Here, in order to further clarify the effect of the constant current drive circuit of the first embodiment, when the power supply voltage Vx (battery voltage) on the electric load R side is changed in the range of 6V to 18V. The simulation result is shown in FIG.
Note that FIG. 2 compares the circuit of the first embodiment with the conventional circuit shown in FIG. 11A under the same conditions.

As is apparent from FIG. 2, in the conventional circuit,
The load current IL is not constant depending on the resistance value variation of the electric load R caused by the variation of the power supply voltage Vx and the ambient temperature variation, whereas the constant current drive circuit of the first embodiment of the present invention provides a power source. The load current IL can be kept constant without being affected by the fluctuation of the voltage Vx and the ambient temperature. this is,
With FET3 and operational amplifier 4, FET1 and FET
This is because both the source-drain voltages VDS1 and VDS2 of 2 can be maintained at the same value.

Further, according to the constant current drive circuit of the first embodiment, the above effect can be obtained without changing the gate voltages of the FET1 and FET2 at all. Therefore, according to the constant current drive circuit of the first embodiment,
As illustrated in (B), the FET 1 and the constant current source 6 are shared, and a drive portion including the FETs 7 and 8 and the operational amplifier 9 similar to the drive portion including the FETs 2 and 3 and the operational amplifier 4 is additionally provided. Even if it is configured as described above, the gate voltage of the FET1 is constant, and the driving portions (FET
The FETs 2 and 3 and the operational amplifier 4, and the FETs 7 and 8 and the operational amplifier 9) operate independently. Therefore, a constant current can be surely flowed to each of the plurality of electric loads R and R ′ by the plurality of driving portions that share the FET 1 and the constant current source 6, and the circuit configuration is not complicated.

In the first embodiment, the ground potential corresponds to the predetermined potential and the power supply voltage Vx corresponds to the second predetermined potential. On the other hand, in the first embodiment, the N-channel MOS is
Although the current mirror circuit 5 is configured by using -FETs 1, 2 and 3, as shown in FIG.
You may make it comprise a current mirror circuit using ET1 ', 2', 3 '. In this case, the FET
The source terminals of 1'and 2'are connected to a predetermined potential VDD higher than the ground potential, and the constant current source 6 allows FE
Reference current Iref from the source terminal to the drain terminal of T1
Will be washed away. And one end of the electric load R is
While being connected to the ground potential as the second predetermined potential,
The load current IL is supplied to the electric load R from the drain terminal of the FET3.

Then, as shown in FIG.
Even when the -FETs 1'to 3'are used, a constant load current IL can be surely supplied to the electric load R, just like the constant current drive circuit of the first embodiment described above. Second Embodiment Next, FIG. 4A is a circuit diagram showing a constant current drive circuit of the second embodiment.

The constant current drive circuit of the second embodiment is also for flowing a constant load current IL through an electric resistance R whose one end is connected to a predetermined power supply voltage Vx, and has a gate terminal and a drain terminal. Connected to each other and their source terminals connected to the ground potential, serving as a first field effect transistor N
Channel MOS-FET (hereinafter simply referred to as FET) 1
1, a gate terminal of which is connected to the gate terminal of the FET 11 and a source terminal of which is connected to the ground potential, which is an N-channel MOS-FET as a second field effect transistor.
(Hereinafter, simply referred to as FET) 12 and the above-mentioned FET at one end
A resistor 13 connected to the drain terminal of 12 and the other end of which is connected to a terminal opposite to the power supply voltage Vx of the electric load R;
Is provided with a current mirror circuit 15.

Also, in the constant current drive circuit of the second embodiment, from the drain terminal of the FET 11 to the source terminal,
Using a predetermined reference power source Vref as a power source, a predetermined reference current I
A constant current source 16 for flowing ref is provided. That is,
In the constant current drive circuit of the second embodiment, the FET 1 which is exactly the same as the FETs 1 and 2 in the constant current drive circuit of the first embodiment is used.
In addition to the FETs 1 and 12, the resistor 13 is provided in series between the electric load R and the drain terminal of the FET 12 instead of the FET 3 and the operational amplifier 4.

The FET 11 and the FET 12 are also formed on the same semiconductor chip as in the case of the first embodiment, and the characteristics of both are the same. Also in the constant current drive circuit of the second embodiment, the electric load R is 1 kΩ and the electric load R is 2 m, as in the first embodiment.
A constant current of A (load current IL) is made to flow,
Reference current Iref flowing through the FET 11 by the constant current source 16
Is set to 20 μA, and FET11 and FET12
And the ratio of the transistor size to 1 is set to 1: 100. Since the basic operation of the FET 11 and the FET 12 is the same as that of the FET 1 and the FET 2 of the first embodiment, detailed description will be given.

In the constant current drive circuit of the second embodiment, the resistance value of the resistor 13 is set to the source of the FET 11 when the constant current (2 mA) flows through the electric load R.
The voltage between the drain and the voltage between the source and drain of the FET 12 are set to match.

Specifically, when the reference current Iref of 20 μA is applied to the FET 11, the source-drain voltage VDS11 of the FET 11 is 1.5 V, and the power supply voltage Vx to which the electric load R is connected is 12 V. Then, resistor 1
The resistance value r of 3 is expressed by the following equation (5) based on the above equation (3).

[0076]

## EQU00005 ## r = (12V-0V-1.5V-1k.OMEGA..times.2mA) / 2mA (5) According to the constant current drive circuit of the second embodiment, regardless of the resistance value of the electric load R, , FET11 and FET1
Both source and drain voltages of 2 can be set equal. Therefore, the value of the reference current Iref (= 20 μA) is F
Ratio of transistor size between ET11 and FET12 (=
A constant current (= 2 mA) multiplied by 100) can be surely passed through the electric load R.

Moreover, according to the constant current drive circuit of the second embodiment, even if the resistance value of the electric load R fluctuates, the fluctuation amount is the total resistance value between the power supply voltage Vx and the drain terminal of the FET 12. Since the ratio becomes small with respect to (that is, the sum of the resistance value of the electric load R and the resistance value of the resistor 13),
A predetermined constant current can be stably applied to the electric load R.

In order to further clarify the effect of the constant current drive circuit of the second embodiment, the ambient temperature is changed from -40 ° C to 80 ° C under the condition that the power supply voltage Vx on the electric load R side is constant at 12V. FIG. 5 shows the simulation result when the range is changed. Note that FIG. 5 compares the circuit of the second embodiment with the conventional circuit shown in FIG. 11A under the same conditions.

As is apparent from FIG. 2, in the conventional circuit,
The load current IL cannot be accurately set to 2 mA according to the transistor size ratio, and the load current IL depends on the resistance value variation of the electric load R due to the change in ambient temperature.
L changes. On the other hand, according to the constant current drive circuit of the second embodiment, it can be seen that the load current IL can be set to about 2 mA, which is the ratio of the transistor size, and the temperature characteristics are good.

As described above, the constant current drive circuit of the second embodiment is effective when the power supply voltage Vx on the electric load R side is stable and only the fluctuation of the resistance value of the electric load R poses a problem. Despite the extremely simple structure, a constant current can be surely passed through the electric load R.

Furthermore, according to the constant current drive circuit of the second embodiment, the above effect can be obtained without changing the gate voltages of the FET 11 and the FET 12. Therefore, as illustrated in FIG. 4B, the FET 11 and the constant current source 16 are shared, and the FET 12 and the resistor 13 are shared.
FET 17 and resistor 18, similar to the drive part consisting of
Even if it is configured to add a drive part consisting of
The gate voltage of the FET 11 is constant, and the drive parts (FET 12 and resistor 13, and FET 17 and resistor 18) operate independently of each other. Therefore, a constant current can be surely flowed to each of the plurality of electric loads R and R ′ by the plurality of driving portions that share the FET 11 and the constant current source 16, and the circuit configuration is not complicated.

Also in the second embodiment, the ground potential corresponds to the predetermined potential and the power supply voltage Vx corresponds to the second predetermined potential. On the other hand, in the second embodiment, the N-channel MOS is
-The current mirror circuit 15 was constructed using the FETs 11 and 12, but as shown in FIG.
You may make it comprise a current mirror circuit using FET11 ', 12'. In this case, FET1
The source terminals of 1'and 12 'are connected to a predetermined potential VDD higher than the ground potential, and the constant current source 16
The reference current Iref will flow from the source terminal to the drain terminal of the FET 11. Then, one end of the electric load R is connected to the ground potential as the second predetermined potential, and a load current IL is supplied to the electric load R from the drain terminal of the FET 12 'via the resistor 13. Becomes

Then, as shown in FIG. 6, a P channel MOS
Even when the -FETs 11 'and 12' are used, a constant load current IL can be supplied to the electric load R just as in the constant current drive circuit of the second embodiment described above. [Third Embodiment] FIG. 7A is a circuit diagram showing a constant current drive circuit according to the third embodiment. The constant current drive circuit of the third embodiment is also for flowing a constant load current IL through the electric resistance R whose one end is connected to the predetermined power supply voltage Vx.

As shown in FIG. 7A, in the constant current drive circuit of the third embodiment, the source terminal is connected to the ground potential,
N-channel M as field effect transistor for current determination
An OS-FET (hereinafter, simply referred to as FET) 21 and a voltage control electric field in which a source terminal is connected to a drain terminal of the FET 21 and a drain terminal is connected to a terminal opposite to the power supply voltage Vx of the electric load R. An N-channel MOS-FET (hereinafter simply referred to as FET) 22 as an effect transistor, and an operational amplifier 23 having an inverting input terminal connected to the drain terminal of the FET 21 and an output terminal connected to the gate terminal of the FET 22. ing.

Further, in the constant current drive circuit of the third embodiment, the FET 21 is divided by dividing the predetermined reference voltage Vref.
Between the gate terminal and the source terminal of the first set voltage V
G is applied, and the second set voltage V is applied between the non-inverting input terminal of the operational amplifier 23 and the source terminal of the FET 21.
It is provided with three voltage dividing resistors 24, 25 and 26 for applying R.

That is, assuming that the resistance values of the voltage dividing resistors 24, 25, 26 are R24, R25, R26, respectively, the gate terminal of the FET 21 has a first setting voltage VG, VG = V
A voltage of ref × R24 / (R24 + R25 + R26) is applied as the gate-source voltage. Then, at the non-inverting input terminal of the operational amplifier 23, VR = Vref × (R24 + R25) / (R24 + R25 + R) is set as the second setting voltage VR.
26) is applied.

In the constant current drive circuit of the third embodiment having such a configuration, the FET 21 and F are connected to the electric load R.
The load current IL will flow through ET22,
At this time, the operational amplifier 2 is connected to the gate terminal of the FET 22.
By 3, the gate voltage is applied so that the voltage of the non-inverting input terminal of the operational amplifier 23 and the drain voltage of the FET 21 become equal.

That is, the non-inverting input terminal of the operational amplifier 23 and the drain terminal of the FET 21 are virtually grounded by the operational amplifier 23, the power supply voltage Vx on the electric load R side fluctuates, and the resistance value of the electric load R changes with temperature. Even if it fluctuates due to changes, etc., the voltage at the non-inverting input terminal of the operational amplifier 23 and the FET
So that the drain voltage of 21 becomes equal.
The source-drain voltage of is adjusted.

As a result, the drain voltage of the FET 21 is
It is always equal to the second set voltage VR applied to the non-inverting input terminal of the operational amplifier 23 by the voltage dividing resistors 24 to 26. In other words, the source-drain voltage of the FET 21 is always equal to the second setting voltage VR,
The channel length modulation effect of is ignored.

Therefore, according to the constant current drive circuit of the third embodiment, the first set voltage VG and the second set voltage V are set.
By setting R appropriately, the load current IL flowing through the electric load R can be made constant at all times. Therefore, a method of determining the first set voltage VG and the second set voltage VR will be described below.

First, in a MOS-FET, in general, as shown in FIG. 8, if the source-drain voltage VDS is constant, the source-drain voltage with respect to the gate-source voltage VGS is reduced.
Point P where drain drain voltage IDS is almost constant regardless of temperature P
Exists. In addition, FIG. 8 shows an N-channel MOS-FET.
As for the source-drain voltage VDS is constant,
Source when changing the gate-source voltage VGS
The results of simulating the drain current IDS with temperature as a parameter are shown.

Therefore, for the FET 21, the gate-source voltage VGS and the source-drain voltage VDS are set so that the source-drain current IDS matches the constant current to be passed through the electric load R and reaches the point P. Each of the voltage dividing resistors 2 is determined so that the first set voltage VG coincides with the above-obtained gate-source voltage VGS and the second set voltage VR coincides with the above-obtained source-drain voltage VDS.
The resistance value of 4 to 26 and the reference voltage Vref may be set.

Then, the gate-source voltage and the source-drain voltage of the FET 21 are held at the first set voltage VG and the second set voltage VR, respectively, and as a result, the power supply voltage Vx. Even if the resistance value of the electric load R fluctuates, the FET 21 and the FET 22 are connected to the electric load R.
A constant load current IL can always be supplied via this.

Here, in order to further clarify the effect of the constant current drive circuit of the third embodiment, the power supply voltage Vx on the electric load R side is changed in the range of 6V to 18V, and the temperature is used as a parameter for the simulation. Figure 9 shows the result of
Shown in Incidentally, FIG. 9 shows the circuit of the third embodiment and FIG.
This is a comparison between the conventional circuit shown in (A) and the same conditions.

As is clear from FIG. 9, in the conventional circuit,
The load current I depends on the fluctuation of the power supply voltage Vx and the ambient temperature.
While L changes, according to the constant current drive circuit of the third embodiment, the load current IL can be kept substantially constant without being affected by fluctuations in the power supply voltage Vx and the ambient temperature. . This is because the source-drain voltage of the FET 21 can be kept constant by the FET 22 and the operational amplifier 23.

Further, according to the constant current drive circuit of the third embodiment, the above effect can be obtained without changing the gate voltage of the FET 21 at all. Therefore, FIG.
As illustrated in (B), a drive portion including FETs 27 and 28 and an operational amplifier 29, which is similar to the drive portion including the FETs 21 and 22 and the operational amplifier 23, sharing the reference power supply Vref and the voltage dividing resistors 24 to 26. Even if it is configured to additionally provide, the gate voltages of the FETs 21 and 27 are constant, and the drive portions (FETs 21 and 22 and operational amplifier 23, and FETs 27 and 28 and operational amplifier 29) described above are provided.
Operate independently. Therefore, a constant current can be surely applied to each of the plurality of electric loads R and R ′ by the plurality of driving portions sharing the reference power source Vref and the voltage dividing resistors 24 to 26, and the circuit configuration becomes complicated. There is nothing to do.

In the third embodiment, the ground potential corresponds to the predetermined potential and the power supply voltage Vx corresponds to the second predetermined potential. Further, the reference power source Vref and the voltage dividing resistors 24 to 26
Corresponds to the first bias means and the second bias means. On the other hand, in the constant current drive circuit of the third embodiment,
Although N-channel MOS-FETs 21 and 22 are used, as shown in FIG.
You may make it comprise using 1 ', 22'. still,
In this case, the source terminal of the FET 21 'is connected to the predetermined potential VDD higher than the ground potential, and one end of the electric load R is connected to the ground potential as the second predetermined potential. Then, the load current IL is supplied to the electric load R from the drain terminal of the FET 22 '.

Then, as shown in FIG.
Even when the S-FETs 21 'and 22' are used, the electric load R is exactly the same as the constant current drive circuit of the third embodiment described above.
A constant load current IL can be passed to.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a constant current drive circuit according to a first embodiment.

FIG. 2 is a graph illustrating the effect of the constant current drive circuit of the first embodiment.

FIG. 3 is a circuit diagram showing a modification of the constant current drive circuit of the first embodiment.

FIG. 4 is a circuit diagram illustrating a constant current drive circuit of a second embodiment.

FIG. 5 is a graph illustrating the effect of the constant current drive circuit of the second embodiment.

FIG. 6 is a circuit diagram showing a modification of the constant current drive circuit of the second embodiment.

FIG. 7 is a circuit diagram illustrating a constant current drive circuit according to a third embodiment.

FIG. 8 is a graph showing operating characteristics of an N-channel MOS-FET.

FIG. 9 is a graph illustrating the effect of the constant current drive circuit of the third embodiment.

FIG. 10 is a circuit diagram showing a modification of the constant current drive circuit of the third embodiment.

FIG. 11 is a circuit diagram showing a constant current drive circuit using a conventional current mirror circuit.

FIG. 12 is a graph illustrating a problem of the constant current drive circuit of FIG.

FIG. 13 is a circuit diagram showing another conventional constant current drive circuit.

[Explanation of symbols]

1,2,3,7,8,11,12,17,21,22,22
27, 28 ... FETs 4, 9, 23, 29 ... Operational amplifier 5, 15 ... Current mirror circuit 6, 16 ... Constant current source R ... Electric load 13, 18 ...
Resistors 24, 25, 26 ... Dividing resistors

Claims (4)

[Claims] 1. A first field effect transistor having a gate terminal and a drain terminal connected to each other, and a gate terminal of the first field effect transistor having the same polarity as that of the first field effect transistor. A second field effect transistor connected to the second field effect transistor, and a source terminal of the first field effect transistor and a source terminal of the second field effect transistor,
In a current mirror circuit, both of which are connected to a predetermined potential, having the same polarity as the first and second field effect transistors,
And a third field effect transistor having a source terminal connected to the drain terminal of the second field effect transistor, a non-inverting input terminal connected to the drain terminal of the first field effect transistor, and an inverting input. A terminal connected to the drain terminal of the second field effect transistor,
Further, an operational amplifier having an output terminal connected to the gate terminal of the third field effect transistor, and a current mirror circuit. 2. The current mirror circuit according to claim 1, and a constant current source for flowing a predetermined reference current between the source terminal and the drain terminal of the first field effect transistor, The third end is connected to the other end of the electric load whose one end is connected to a second predetermined potential different from the predetermined potential to which the source terminals of the first and second field effect transistors are connected.
A constant current drive circuit, wherein the drain terminal of the field effect transistor is connected to the electric load, and a constant current is supplied to the electric load via the drain terminal of the third field effect transistor. 3. A first field effect transistor having a gate terminal and a drain terminal connected to each other, and a gate terminal of the first field effect transistor having the same polarity as that of the first field effect transistor. And a second field effect transistor connected to the first field effect transistor, wherein the source terminal of the first field effect transistor and the source terminal of the second field effect transistor are both connected to a predetermined potential, A constant current source for flowing a predetermined reference current between a source terminal and a drain terminal of the first field effect transistor, and one end of which is connected to a second predetermined potential different from the predetermined potential. A constant current drive circuit configured to allow a constant current to flow through a load via a drain terminal of the second field effect transistor, wherein: A resistor having a predetermined resistance value is provided in series between the terminal on the side opposite to the second predetermined potential and the drain terminal of the second field effect transistor, and the resistance value of the resistor is The source-drain voltage of the first field-effect transistor and the source-drain voltage of the second field-effect transistor are set to substantially match when the constant current flows in the electric load. A constant current drive circuit characterized by: 4. A current determining field effect transistor having a source terminal connected to a predetermined potential, the current determining field effect transistor having the same polarity, and
A voltage controlling field effect transistor having a source terminal connected to the drain terminal of the current determining field effect transistor, an inverting input terminal connected to the drain terminal of the current determining field effect transistor, and an output terminal having the voltage An operational amplifier connected to the gate terminal of the controlling field effect transistor; first biasing means for applying a first set voltage between the gate terminal and the source terminal of the current determining field effect transistor; A second bias means for applying a second set voltage between a non-inverting input terminal of the operational amplifier and a source terminal of the current determining field effect transistor; and a second bias means different from the predetermined potential. The drain terminal of the voltage control field effect transistor is connected to the other end of the electric load whose one end is connected to a predetermined potential, A constant current drive circuit, wherein a constant current is made to flow through the load via the drain terminal of the voltage controlling field effect transistor.