JPH09298300A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fine, high-speed semiconductor device which can prevent short-circuiting between semiconductor regions even when a compound layer having a low resistance is formed on the semiconductor regions and which can be manufactured with a high yield. SOLUTION: A Si film 14 and a diffusion layer 21, which are already subjected to removal of their spontaneously-oxidized films, are subjected to an ion implanting process to form amorphous layers 14a and 21a on the film 14 and layer 21, and are then subjected to an annealing process of 2 stages to thereby form a TiSi2 film 24. Suppression of a silicide formation reaction by knocked-on oxygen atoms can be prevented so that the amorphous layers 14a and 21a can have a sufficient thickness and the silicide formation reaction can be promoted. Thus, the need for an additional annealing process can be eliminated and excessive growth of the TiSi2 films 23 and 24 can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a compound layer of a semiconductor and a metal is formed on the surface of a semiconductor region in a self-aligned manner.

[0002]

2. Description of the Related Art In order to miniaturize and speed up a semiconductor device such as a MOS transistor, it is necessary to reduce the resistance of a diffusion layer formed on a semiconductor substrate and wiring formed of a semiconductor. A structure in which a compound layer of a semiconductor and a metal is formed on the surface of a semiconductor region in a self-aligned manner is considered.

8 and 9 show a conventional example of a method for manufacturing a MOS transistor having such a compound layer and having an LDD structure. In this conventional example, as shown in FIG. 8A, a SiO ₂ film 12 is selectively formed on the surface of a Si substrate 11 to determine an element isolation region, and an element surrounded by the SiO ₂ film 12 is defined. A SiO ₂ film 13 as a gate oxide film is formed on the surface of the active region.

After that, a gate electrode is formed of the Si film 14 made of polycrystalline Si, a low-concentration diffusion layer 15 is formed, and a side wall made of a SiO ₂ film 16 and the like is formed on the Si film 14. Then, a SiO ₂ film 17 as a sacrificial oxide film is formed on the entire surface, and a high-concentration diffusion layer 21 is formed by ion implantation of impurities through the SiO ₂ film 17.

Next, as shown in FIG. 8B, ion implantation is performed to form amorphous layers 14a and 21a on the surfaces of the Si film 14 and the diffusion layer 21. Then, after removing the SiO ₂ film 17, a Ti film 22 is formed on the entire surface, and the amorphous layer 14 is formed.
By reacting a and 21a with the Ti film 22 by heat treatment in a nitrogen atmosphere, a C49 phase TiSi ₂ film 23 is formed on the surfaces of the Si film 14 and the diffusion layer 21, as shown in FIG. 8C.

Next, as shown in FIG. 9A, as shown in FIG.
After performing heat treatment at a higher temperature than the heat treatment in the process of
As shown in FIG. 9B, the Ti film 22 left unreacted and the Ti film formed on the SiO ₂ films 12 and 16
The N film is removed. Then, as shown in FIG.
A heat treatment at a higher temperature than the heat treatment in the step (a) is performed to cause a phase transition from the C49 phase TiSi ₂ film 23 to the low resistance C54 phase TiSi ₂ film 24.

By the way, from the Ti film 22 to the TiSi ₂ film 2
3 for forming the TiSi ₂ film 2 by only a two-step heat treatment, that is, a first-step heat treatment for forming No. 3 and a second-step heat treatment for causing a phase transition from the TiSi ₂ film 23 to the TiSi ₂ film 24.
4 is formed, as shown by the curve in the graph of FIG.
A so-called thin line effect occurs in which the sheet resistance of the diffusion phase 21 including the TiSi ₂ film 24 does not drop to a desired level of about 5Ω / □ in the thin line region.

Therefore, as in the above-described embodiment, by forming the amorphous layers 14a and 21a on the surfaces of the Si film 14 and the diffusion layer 21, the silicidation reaction is promoted, and the two steps described above are performed. It has been considered to add the heat treatment shown in FIG. 9A to the middle of the heat treatment (see, for example, Japanese Patent Laid-Open No. Hei 5
No. 291180). In such a conventional example, as shown in FIG.
As shown by the curve in the graph, the thin line effect hardly occurs.

[0009]

However, the temperature of the heat treatment added in the middle of the two-stage heat treatment is 800 ° C., which is about the same as the temperature of the second-stage heat treatment of 800 ° C. It is considerably higher than the temperature of 650 degrees for the heat treatment of the stage. When such a high temperature heat treatment is performed, the Si film 1
4 and the diffusion layer 21 from the Ti on the SiO ₂ films 12 and 16
Si atoms diffuse into the film 22.

[0010] Therefore, as shown in FIG. 9 (a), protruding from the top TiSi ₂ film 23 by the additional heat treatment is Si film 14 and the diffusion layer 21 onto the SiO ₂ film 12 and 16 is grown, the TiSi ₂ TiSi ₂ phase-transformed from the film 23
The Si film 14 and the diffusion layer 21 may be short-circuited via the film 24. Therefore, in the above-mentioned conventional example, this MO
It has been difficult to manufacture S transistors with high yield.

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a semiconductor oxide film is removed from a surface of a semiconductor region, ions are implanted into the semiconductor region, and the surface of the semiconductor region is amorphous. Forming a crystalline layer, a step of reacting the amorphous layer with a metal in a first heat treatment to form a reactant layer on the surface, and a second heat treatment of the reactant layer to form a compound. And a step of forming a layer.

A method for manufacturing a semiconductor device according to a second aspect is the method for manufacturing a semiconductor device according to the first aspect, further comprising a step of forming a semiconductor nitride film over the entire surface after the step of forming the compound layer. I am trying.

A method of manufacturing a semiconductor device according to claim 3 is the method of manufacturing a semiconductor device according to claim 2, wherein an interlayer insulating film having etching characteristics different from those of the semiconductor nitride film is formed on the semiconductor nitride film. A step of etching the interlayer insulating film using the semiconductor nitride film as a stopper in a pattern of connection holes for the compound layer; and, after the etching, etching only the semiconductor nitride film in the pattern to form the connection holes. And a step of opening.

In the method of manufacturing a semiconductor device according to the first aspect, ion implantation is performed with the semiconductor oxide film removed from the surface of the semiconductor region where the compound layer is to be formed, and an amorphous layer is formed on the surface of this semiconductor region. Therefore, it is possible to prevent the chemical reaction between the semiconductor and the metal from being suppressed by the oxygen atoms knocked on the semiconductor region by the ion implantation, and to form an amorphous layer with a sufficient thickness. Therefore, the compounding reaction between the semiconductor and the metal can be promoted.

Therefore, the low resistance compound layer can be formed on the surface of the semiconductor region only by the formation of the amorphous layer and the first and second heat treatments, and the first heat treatment and the second heat treatment are combined. Since it is not necessary to perform additional heat treatment in the middle, it is possible to prevent the reactive substance or the compound layer from bulging out from the semiconductor region to the outside of the semiconductor region and form the compound layer in a self-aligned manner only on the surface of the semiconductor region. it can.

In the method of manufacturing a semiconductor device according to the second aspect, since the semiconductor nitride film is formed as a step subsequent to the step of forming the compound layer, the semiconductor oxide film is formed as a step subsequent to the step of forming the compound layer. Compared to the case of forming the layer, oxygen is less mixed into the compound layer, and the increase in sheet resistance due to aggregation of the compound layer can be suppressed.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, since the interlayer insulating film and the semiconductor nitride film are selectively etched to open the connection hole, the insulating film surrounding the semiconductor region and the interlayer insulating film are formed. Even if the etching characteristics are substantially equal to each other and the connection hole is displaced from the compound layer, the insulating film surrounding the semiconductor region is not etched like the opening of the connection hole and is formed in the connection hole. It is possible to prevent a short circuit between the wiring under the insulating film surrounding the semiconductor region and the wiring under the insulating film.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A CMOS having an LDD structure will be described below.
First to Third Inventions of the Present Invention Applied to Manufacturing of Transistor
An embodiment will be described with reference to FIGS. Figure 1
3 shows 1st Embodiment. In the first embodiment, as shown in FIG. 1A, the SiO ₂ film 12 is selectively formed on the surface of the Si substrate 11 by the LOCOS method of performing wet oxidation at a temperature of 950 ° C. To decide. Instead of LOCOS element isolation, trench element isolation or the like may be adopted.

After that, an appropriate well (not shown) is formed, a buried layer (not shown) for suppressing punch-through between the source and the drain is formed in the well, and a threshold voltage is set. Ion implantation of impurities for adjustment is performed. Then, a SiO ₂ film 13 having a film thickness of about 8 nm is formed as a gate oxide film on the surface of the element active region surrounded by the SiO ₂ film 12 by pyrogenic oxidation at a temperature of 850 ° C.

Thereafter, the Si film 14 made of polycrystalline Si is deposited by the low pressure CVD method in which the source gas is SiH ₄ and the deposition temperature is 620 ° C., and the Si film 14 is processed into a gate electrode pattern by photolithography and dry etching. To do. The Si substrate 11 and the Si film 14 serve as a semiconductor (semiconductor region) in the present invention.

Next, using the Si film 14 and the SiO ₂ film 12 and a suitable photoresist (not shown) as a mask, N
As ⁺ is ion-implanted into the formation region of the MOS transistor at an acceleration energy of 20 keV and a dose amount of 6 × 10 ¹² cm ^−2.
BF ₂ ⁺ is ion-implanted at an acceleration energy of keV and a dose amount of 2 × 10 ¹³ cm ⁻² to form a low-concentration diffusion layer 15 as shown in FIG.

Next, as shown in FIG. 1C, the film thickness is 1
A SiO ₂ film 16 having a thickness of about 50 nm is deposited by the atmospheric pressure CVD method, and the SiO ₂ film 16 is etched back by anisotropic dry etching to form a side wall of the SiO ₂ film 16 on the Si film 14. A SiO ₂ film deposited by a low pressure CVD method using TEOS as a raw material or an atmospheric pressure CVD method using O ₃ + TEOS as a raw material, a SiN film deposited by a low pressure CVD method, or the like may be used instead of the SiO ₂ film 16. good.

Next, the Si film 14 and the SiO ₂ films 12, 1
6 and an appropriate photoresist (not shown) as a mask, and in the formation region of the NMOS transistor, the acceleration energy of 60 keV and the dose amount of 3 × 10 ¹⁵ cm ⁻² are used.
⁺ Is ion-implanted, BF ₂ ⁺ is ion-implanted into the formation region of the PMOS transistor at an acceleration energy of 40 keV and a dose amount of 3 × 10 ¹⁵ cm ⁻² , and as shown in FIG. The diffusion layer 21 is formed.

These ion implantations may be performed with a sacrificial oxide film having a film thickness of about 10 nm formed on the entire surface.
You may perform directly with respect to Si substrate 11 grade. afterwards,
Impurities in the diffusion layers 15 and 21 are activated by performing short-time annealing at a temperature of 1000 to 1100 ° C. for 10 seconds and furnace annealing at a temperature of 850 to 950 ° C. for about 10 minutes.

As described above, if the sacrificial oxide film is used during the ion implantation for forming the diffusion layer 21, the sacrificial oxide film remains on the entire surface at this point. Further, even if the sacrificial oxide film is not used, the Si substrate 11 is formed while performing ion implantation for forming the diffusion layer 21 and heat treatment for activating the impurities in the diffusion layers 15 and 21. And Si
A natural oxide film 25 having a thickness of about 3 nm is formed on the surface of the film 14.
Are formed.

Then, using a mixed solution of hydrofluoric acid and ammonium fluoride, such as buffered hydrofluoric acid or hydrofluoric acid, the etching rate is set to 3
Wet etching of about nm / min is performed, and FIG.
As shown in (e), the natural oxide film 25 (the sacrificial oxide film when the sacrificial oxide film is used) is removed. This natural oxide film 2
5 (or sacrificial oxide film) becomes the semiconductor oxide film in the present invention. Here, gas: CHF ₃ / CO = 60/24
Magnetron type anisotropic dry etching of 0 sccm, pressure = 5.3 Pa, output = 1200 W, temperature = 30 ° C. may be used instead of wet etching.

Next, as shown in FIG. 2A, 40 keV
A at acceleration energy of 3 × 10 ¹⁴ cm ^-2
Amorphous layers 14a and 21a are formed on the surfaces of the Si film 14 and the diffusion layer 21 by ion implantation of s ⁺ . At this time, since the ion implantation is performed with the natural oxide film 25 removed, not only oxygen atom knock-on does not occur, but also the amorphous layers 14a and 21a having a sufficient thickness are formed. As
Instead of ⁺ may be used Sb ⁺ or Si ⁺ or the like.

Next, as shown in FIG. 2B, a Ti film (metal film in the present invention) 22 is formed on the entire surface by a CVD method or a vapor deposition method. Instead of Ti, another refractory metal such as Co, Ni or Pt may be used. After that, annealing is performed in a nitrogen atmosphere at a temperature of 650 ° C. for a short time of 30 seconds to cause the amorphous layers 14a and 21a and the Ti film 22 to react with each other, and as shown in FIG. A C49 phase TiSi ₂ film (reactant layer in the present invention) 23 is formed on the surfaces of the film 14 and the diffusion layer 21.

Since the SiO ₂ films 12 and 16 and the Ti film 22 do not cause a silicidation reaction, the SiO ₂ films 12 and 16
The Ti film 22 remains unreacted on top. TiSi ₂ film 2
The heat treatment for causing the silicidation reaction to form 3 may be performed in an argon atmosphere.

Next, ammonia hydrogen peroxide (NH ₃ : H
₂ O ₂ : H ₂ O = 1: 2: 6) and the temperature is room temperature and the time is 10 minutes.
As shown in, the Ti film 22 which remains unreacted is selectively removed. Instead of ammonia hydrogen peroxide, hydrochloric acid hydrogen peroxide or sulfuric acid hydrogen peroxide may be used.

Next, in a nitrogen atmosphere or an argon atmosphere
The temperature is 800 ℃ and the time is 30 seconds.
As shown in FIG. 2 (e), Ti of C49 phase
Si _TwoFrom the film 23, sheet resistance is as low as 5Ω / □
C54 phase TiSi which is_TwoMembrane (compound in the present invention
Layer) 24. After that, as shown in Fig. 3 (a)
Then, the interlayer insulating film 26 is formed.

Next, as shown in FIG. 3B, TiSi ₂
A contact hole 27 reaching the film 24 is opened in the interlayer insulating film 26,
The connection hole 27 is filled with a tungsten plug 31 or the like. Then, the wiring is formed by the first-layer Al film 32, and the Al film 32 and the like are covered by the SiO ₂ film 33 having a flat surface.
A wiring or the like made of an I film (not shown) is formed on the SiO ₂ film 33 to complete this CMOS transistor.

The curve in the graph of FIG. 6 shows the sheet resistance of the diffusion layer 21 including the TiSi ₂ film 24 formed in the first embodiment as described above. In the first embodiment, the first stage heat treatment for forming the TiSi ₂ film 23 from the Ti film 22 and the TiSi ₂ film 23 to the TiSi ₂ film are performed.
Although no additional heat treatment was performed in the middle of the second-stage heat treatment for causing the phase transition to the film 24, the same sheet resistance as that of the conventional example shown by the curve was obtained. There is.

In the first embodiment, amorphous Si may be used as the Si film 14. In this case, in the step shown in FIG. 1A, the Si film 14 made of amorphous Si is formed to a thickness of about 100 to 300 nm by the low pressure CVD method. The Si film 14 may be amorphous Si doped with impurities (for example, phosphorus) or amorphous Si not doped with impurities (non-doped). However, when the Si film 14 made of non-doped amorphous Si is formed, a step of introducing impurities into the Si film 14 will be performed in a later step. Below, each Si film 1
An example of the film forming conditions of No. 4 will be described.

A. Si composed of phosphorus-doped amorphous Si
Film forming conditions of film 14 Film forming pressure: 50 to 400 Pa Film forming temperature: 500 to 600 ° C. Film forming gas and flow rate: SiH ₄ = 50 to 2000 sccm PH ₃ = 10 to 500 sccm

B. Si made of non-doped amorphous Si
Film forming conditions of film 14 Film forming pressure: 50 to 400 Pa Film forming temperature: 500 to 600 ° C. Film forming gas and flow rate: SiH ₄ = 50 to 2000 sccm

As described above, S made of amorphous Si is used.
After forming the i film 14, the Si film 14 is processed into a pattern of the gate electrode, and then the steps described with reference to FIGS. 1B to 1E are performed in the same manner as described above. After that, Figure 2
In the step shown in (a), ion implantation is performed as described above. As a result, the surface layer of the Si film 14 slightly polycrystallized by the heat treatment for activating the impurities in the diffusion layers 15 and 21 described with reference to FIG.
4a is formed. Further, the amorphous layer 21a is formed on the surface layer of the diffusion layer 21.

At this time, similar to the above, the natural oxide film 25 is formed.
Since the ion implantation is performed in a state where (the sacrificial oxide film when the sacrificial oxide film is formed) is removed, not only the knock-on of oxygen atoms due to the ion implantation does not occur,
The amorphous layers 14a and 21a having a sufficient thickness are formed. Moreover, since the Si film 14 is originally formed as amorphous Si, the Si film 1 is formed by ion implantation as compared with the case where the Si film 14 made of polycrystalline Si is formed.
4 The amorphousness of the amorphous layer 21a formed on the surface is increased, and the amorphous layer 21a having better reactivity can be obtained.

After performing the above steps, the process shown in FIG.
The steps described with reference to FIG. 3B are performed in the same manner as above,
This completes the CMOS transistor.

In the graph of FIG. 7, a curved line represents Si made of N-type polycrystalline Si in the first embodiment as described above.
The sheet resistance of the gate electrode when the film 14 is formed is shown. The curve shows the sheet resistance of the gate electrode when the Si film 14 made of the same P-type polycrystalline Si is formed. Further, the curve shows the sheet resistance of the gate electrode when the Si film 14 made of the same N-type amorphous Si is formed. The curve shows the sheet resistance of the gate electrode when the Si film 14 made of the same P-type amorphous Si is formed. It should be noted that the surface of these Si films 14 is subjected to ion implantation under the same conditions by the amorphous layer 14a.
Was formed.

As shown in each of these curves, by forming the Si film 14 made of amorphous Si, the polycrystalline S
It can be seen that the increase of the sheet resistance is suppressed in the thinner line region as compared with the case where the Si film 14 made of i is formed.

FIG. 4 shows a second embodiment. In the second embodiment, the polycide layer 36 including the Si film 34 and the WSi ₂ film 35 and the SiO 2 on the polycide layer 36 are formed.
Substantially the same steps as those in the first embodiment described above are performed except that the ₂ film 37 and the gate electrode pattern are processed and the TiSi ₂ film 24 is not formed on the surface of the gate electrode. In the second embodiment as described above, the same operational effect as that of the first embodiment can be obtained.

FIG. 5 shows a third embodiment. The third embodiment executes substantially the same steps as the above-described second embodiment except that the SiN film 38 is formed on the entire surface as a step after the TiSi ₂ film 24 is formed. In the third embodiment like this, when the connection hole 27 is opened,
The interlayer insulating film 26 can be etched using the SiN film 38 as a stopper, and only the SiN film 38 can be etched using the SiO ₂ films 16, 37 and 12 as stoppers.

Therefore, misalignment occurs in the photolithography process before opening the connection hole 27, and the connection hole 27 is misaligned.
Is displaced from the top of the TiSi ₂ film 24, the connection hole 27
It is possible to prevent a short circuit between the tungsten plug 31 and the polycide layer 36 without etching the SiO ₂ films 16, 37 and 12 at the same time as the opening.

The first to third embodiments described above are LDs.
Although the invention of the present application is applied to the manufacture of a CMOS transistor having a D structure, the invention of the present application is also applied to the structure of a non-LDD structure CMOS transistor, a non-complementary MOS transistor, or a semiconductor device other than a MOS transistor. Can be applied.

[0046]

According to the method of manufacturing a semiconductor device of the first aspect,
Since the low resistance compound phase can be formed only on the surface of the semiconductor region in a self-aligned manner, it is possible to prevent a short circuit between the semiconductor regions even if the low resistance compound phase is formed on the surface of the semiconductor region. Therefore, a fine and high-speed semiconductor device can be manufactured with a high yield.

In the method of manufacturing a semiconductor device according to the second aspect, since the upper layer of the sheet resistance due to the aggregation of the compound layer can be suppressed because oxygen is less mixed into the compound layer, the semiconductor device can be manufactured at a higher speed. You can

In the method of manufacturing the semiconductor device according to the third aspect, since it is possible to prevent a short circuit between the wiring formed in the connection clause and the wiring under the insulating film surrounding the semiconductor region, it is fine and high speed. Semiconductor devices can be manufactured with a higher yield.

[Brief description of drawings]

FIG. 1 is a side sectional view sequentially showing an initial step of a first embodiment of the invention of the present application.

FIG. 2 is a side sectional view sequentially showing a middle stage process of the first embodiment.

FIG. 3 is a side sectional view sequentially showing a final step of the first embodiment.

FIG. 4 is a side sectional view showing a step in the middle of the second embodiment of the present invention.

FIG. 5 is a side sectional view showing a step in the middle of the third embodiment of the present invention.

FIG. 6 is a graph showing the relationship between the sheet resistance and the width of the diffusion layer formed in each of the two methods shown in the related art and the first to third embodiments of the present invention.

FIG. 7 is a schematic view of the polycrystalline S according to the first to third embodiments of the invention of the present application.
5 is a graph showing the relationship between the width of the gate electrode and the sheet resistance when a Si film made of i is formed and when a Si film made of amorphous Si is formed.

FIG. 8 is a side sectional view sequentially showing the first half steps of a conventional example of the present invention.

FIG. 9 is a side sectional view sequentially showing the latter half of the steps of a conventional example.

[Explanation of symbols]

14 Si film 14a Amorphous layer 21 Diffusion layer
21a amorphous layer 22 Ti film 23 TiSi ₂ film 24 TiS
i ₂ film 25 natural oxide film 26 interlayer insulating film 27 connection hole 38 SiN film

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a compound layer of a semiconductor and a metal is formed on a surface of a semiconductor region, wherein ion implantation is performed on the semiconductor region in a state where a semiconductor oxide film is removed from the surface of the semiconductor region. Forming an amorphous layer on the surface of the semiconductor region; reacting the amorphous layer with the metal in a first heat treatment to form a reactant layer on the surface; And a step of forming a compound layer by performing a second heat treatment, the method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a semiconductor nitride film on the entire surface after the step of forming the compound layer. 3. A step of forming an interlayer insulating film having an etching characteristic different from that of the semiconductor nitride film on the semiconductor nitride film, and a pattern of connection holes for the compound layer, wherein the semiconductor nitride film is used as a stopper to form the interlayer insulating film. 3. The semiconductor device according to claim 2, further comprising: a step of etching an insulating film; and a step of etching only the semiconductor nitride film with the pattern to open the connection hole after the etching. Production method.