JPH09283636A - Manufacture of semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To substantially synchronize etching end points of an N-type silicon film portion and a P-type silicon film portion so as to prevent excavation and generation of residue on a substrate, by etching back a silicon film portion of a PMOS region by a predetermined thickness and then introducing P-type impurity into the silicon film portion. SOLUTION: A silicon film 15 is formed on a substrate 11 having an N-type pattern forming region 11a and a P-type pattern forming region 11b. The P-type pattern forming region 11b of the silicon film 15 is etched back by a predetermined thickness determined by the etching rate ratio between P-type silicon and N-type silicon. N-type impurity 16 is introduced into the N-type pattern forming region 11a and P-type impurity 18 is introduced into the P-type pattern forming region 11b. The impurity is diffused in each region. A metallic conductive film 19 is formed on the silicon film 15. Then, the silicon film 15 and the conductive film 19 are patterned by etching, and thus an N-type pattern 21 and a P-type pattern 22 are simultaneously formed on the substrate 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS in which a surface channel type N channel MOS transistor and a P channel MOS transistor are provided on the same substrate.
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device that are preferably used for a transistor.

[0002]

2. Description of the Related Art C (Complementary) -MOS transistor composed of an N-channel type MOS field effect transistor (hereinafter referred to as NMOS) and a P-channel type MOS field effect transistor (hereinafter referred to as PMOS) Since (hereinafter, referred to as CMOS) has low power consumption and can operate at high speed, it is widely used as many LSI constituent devices such as memories and logics. In the CMOS described above, the N ⁺ type gate electrode is used for both the NMOS and the PMOS, so that the process is simplified and the buried channel type PMOS is operated at high speed.

On the other hand, with the high integration of semiconductor devices,
Currently, M has been miniaturized to a gate length of 0.1 μm or less
Room temperature operation of OS type transistors has also been confirmed. When the miniaturization of the MOS type transistor progresses even after the deep submicron generation, in the above CMOS,
To prevent the short channel effect, a so-called Dual Gate structure in which an NMOS is an N ⁺ type gate electrode and a PMOS is a P ⁺ type gate electrode is adopted to form a CMOS with a surface channel type NMOS and a PMOS. The need has arisen.

When manufacturing the CMOS having the dual gate structure, As (arsenic) is formed in the NMOS region of the polysilicon film (or amorphous silicon film) forming the gate electrode.
N-type impurities such as or P (phosphorus) are implanted, and P-type impurities such as B (boron) or BF ₂ (boron difluoride) are implanted into the PMOS region. Next, after forming a conductive film made of a metal silicide film or a metal film on the polysilicon film, diffusion and activation heat treatment of the impurities implanted in the polysilicon film are performed, and the polysilicon film in the NMOS region is N-doped.
^The polysilicon film in the PMOS region is changed to the ⁺ type by the P ⁺ type.
Then, the polysilicon film and the conductive film are patterned by etching to form a P ⁺ type gate electrode and an N ⁺ type gate electrode at the same time.

In the above method, however, the impurities in the polysilicon film are interdiffused through the conductive film made of a metal silicide film or a metal film during the heat treatment, and the impurities in the NMOS region and the PMOS region in the polysilicon film are diffused. There was a problem that they would be compensated for each other. Therefore, a method of increasing the grain size of the polysilicon film forming the gate electrode to make it difficult for impurities to diffuse into the metal-based conductive film, or forming a silicide film or a metal film after diffusing impurities into the polysilicon film A method has been proposed in which the amount of impurities diffused from the polysilicon film into the silicide film or the metal film is reduced.

[0006]

However, as shown in FIG. 5, the N ⁺ type polysilicon and the P ⁺ type polysilicon forming the Dual Gate structure have different etching rates depending on the sheet resistance. Show. In particular, the lower the resistivity region, the N ⁺ -type etching rate of the polysilicon is accelerated and since the etching rate of the P-type polysilicon is slow, the N ⁺ -type polysilicon and P ⁺ -type polysilicon The difference in etching rate becomes large. Therefore, as shown in FIG. 6 in the above-described CMOS manufacturing process, one wiring material layer having a laminated structure of the polysilicon film 61 and the conductive film 62 in which the N ⁺ type part and the P ⁺ type part are mixed is formed. When patterning at the same time using the mask of
A portion of the substrate 60 under the N ⁺ -type polysilicon film 61a having a high etching rate is excessively overetched and dug, or a residue of the P ⁺ -type polysilicon film 61b having a slow etching rate remains on the step.

[0007]

Therefore, a method of manufacturing a semiconductor device according to the present invention for solving the above-mentioned problems is characterized by performing the following steps. That is, in the first method, a silicon film is formed on the substrate in the first step, N-type impurities are introduced into the N-type pattern forming region of the silicon film in the second step, and P After introducing a type impurity, diffusing the N-type impurity and the P-type impurity into respective regions in the silicon film in the third step, and forming a metal-based conductive film on the silicon film in the fourth step. When the N-type pattern and the P-type pattern are simultaneously formed on the substrate by patterning the silicon film and the conductive film in the fifth step, the silicon is formed after the first step and in the second step. Before introducing P-type impurities into the P-type pattern forming region of the film, a step of etching back the P-type pattern forming region of the silicon film by a predetermined thickness is performed.

In the second method, when performing the first to fifth steps, the P-type pattern forming region of the silicon film is formed into a predetermined film after the third step and before the fourth step. It is characterized by performing a step of etching back by the thickness.

In the first method or the second method described above, the P-type pattern forming region is predetermined before the P-type impurity is introduced into the P-type pattern forming region of the silicon film or after the P-type impurity is diffused. Since the film thickness is etched back, the P-type pattern formation region of the silicon film is thinned with almost no change in the diffusion state of impurities in the silicon film. Therefore, in the fifth step, the N-type pattern forming region of the silicon film whose etching rate is increased by diffusing the N-type impurities and the etching rate is decreased by diffusing the P-type impurities. Patterning is performed at the same time as the P-type pattern forming region of the silicon film which is thinner than the mold pattern forming region. Therefore, in the P-type pattern forming region, the etching rate of the silicon film slower than that in the N-type pattern forming region is covered by the thinning of the silicon film portion, and the etching of the N-type pattern forming region and the P-type pattern forming region is performed. The end points of are almost at the same time.

In the third method, a predetermined film is formed on the upper surface or the lower surface of the silicon film in the N-type pattern forming region in the steps before the fourth step when performing the first step to the fifth step. It is characterized in that a step of forming a thick silicon layer is performed.

In the third method, the silicon layer is formed on or below the silicon film in the N-type pattern forming region before the conductive film is formed on the silicon film. The N-type pattern formation region of the silicon film is thickened with almost no change in the diffusion state of the impurities. Therefore, in the fifth step, the P-type pattern forming region of the silicon film, which has a slower etching rate due to the diffusion of the P-type impurities, and the diffusion of the N-type impurities, results in a higher etching rate. Patterning of the silicon film thicker than the P-type pattern forming region and the N-type pattern forming region is simultaneously performed. Therefore, in the N-type pattern formation region, the portion of the silicon film having a higher etching rate than the P-type pattern formation region is covered by the thickening of the silicon film portion, and the N-type pattern formation region and the P-type pattern formation region are separated from each other. The etching end points are almost at the same time.

Further, the semiconductor device of the present invention has
An N-type pattern having a laminated structure of a silicon film in which N-type impurities are diffused and a metal-based conductive film, and a P-type pattern having a laminated structure of a silicon film in which P-type impurities are diffused and a metal-based conductive film A semiconductor device having
The silicon film forming the mold pattern is characterized by being thicker than the silicon film forming the P-type pattern by a predetermined thickness. In the above semiconductor device, the P-type pattern is formed by the silicon film whose etching rate is slowed down by diffusing the P-type impurity and the conductive film on the upper surface, and the etching rate is fast by diffusing the N-type impurity. And a silicon film having a thickness larger than that of the P-type pattern, the conductive film on the upper surface of the silicon film, and the N-type pattern are formed. Therefore, the N-type pattern is covered by thickening the portion corresponding to the high etching rate.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION A method of manufacturing a semiconductor device and a method of manufacturing a semiconductor device of a CMOS according to the present invention will be described below.
Will be described in detail based on the embodiment applied to. In each embodiment, common components are designated by the same reference numerals, and redundant description of the same steps will be omitted.

First, a first embodiment of the present invention will be described with reference to FIGS. 1 (1) to 1 (5). As shown in FIG.
For example, by the LOCOS (Local Oxidation of Silicon) method, the field oxide film 12 is formed on the front surface side of the substrate 11 made of silicon, and the front surface side of the substrate 11 is formed with the NMOS region 11a for forming the NMOS and the PMOS. Separated into the PMOS region 11b. This NMO
The S region 11a becomes the N-type pattern forming region, and the PMOS
The region 11b becomes the P-type pattern forming region.

Next, P is formed in the NMOS region 11a of the substrate 11.
Ion implantation is performed to form a well region 13a and to form a buried diffusion layer for preventing punch through of a transistor (not shown here).
Further, ion implantation is performed to adjust the threshold voltage of the transistor. Similarly, the PMOS region 11 of the substrate 11
An N well region 13b and a buried diffusion layer (not shown) are formed in the region b, and ion implantation for adjusting the threshold voltage is further performed.

Next, a gate oxide film 14 having a film thickness of 8 nm is formed on the surface of the substrate 11 by the thermal oxidation method. here,
For example, pyrogenic oxidation is performed in an atmosphere consisting of hydrogen and oxygen at 850 ° C. Next, low pressure CVD (Chem
ical Vapor Deposition)
A silicon film 15 made of amorphous silicon is deposited to a film thickness of 100 nm. As an example of a specific film forming condition for the silicon film 15, a material gas: SiH ₄ (monosilane) film forming temperature: 550 ° C. is set. In the step of forming the silicon film 15,
Polysilicon may be deposited and formed by a CVD method.

Next, a resist pattern (not shown) which covers at least the PMOS region 11b and opens on the NMOS region 11a is formed on the silicon film 15 by lithography. Then, the NMOS region 1 is formed by ion implantation using this resist pattern as a mask.
An N-type impurity 16 is introduced into the silicon film 15 of 1a. As an example of a specific introduction condition of the N-type impurity 16, N-type impurity: phosphorus ion (P ⁺ ) implantation energy: 10 keV implantation dose amount: 5 × 10 ¹⁵ / cm ² .

After removing the resist pattern, a resist pattern 17 having a shape covering at least the NMOS region 11a and opening on the PMOS region 11b is newly formed on the silicon film 15. Then, by etching using the resist pattern 17 as a mask,
The silicon film 15 in the PMOS region 11b is etched back by about 30 nm. This step is the point of the first embodiment. This etching amount is determined from the etching rate ratio between the silicon film 15 portion of the NMOS region 11a in which the N-type impurity is diffused and the silicon film 15 portion of the PMOS region 11b in which the P-type impurity is diffused in the subsequent step. It is set to a value such that the end points of the etching of the silicon film portion are the same. That is, the etching rate of the silicon film 15 portion in the NMOS region 11a is vn and the film thickness is tn.
When the etching rate of the silicon film 15 portion in the PMOS region 11b is vp and the film thickness is tp, tn
The etching amount is set so that tp satisfies / vn = tp / vp.

After the silicon film 15 is etched back as described above, as shown in FIG. 1B, the PMO is formed by ion implantation using the resist pattern 17 as a mask.
A P-type impurity 18 is introduced into the silicon film 15 in the S region 11b. As an example of specific introduction conditions of P-type impurities, P-type impurities: boron ions (B ⁺ ) implantation energy: 5 keV implantation dose amount: 5 × 10 ¹⁵ / cm ² .

Next, in the third step, as shown in FIG. 1C, after removing the resist pattern (17), 650
Heat treatment is performed at a temperature of about 10 hours. By this heat treatment, the amorphous silicon forming the silicon film 15 is crystallized to become polysilicon. This polysilicon is CVD
The crystal grain size is larger than that of polysilicon formed by the method. Subsequently, rapid thermal annealing at 1000 ° C. for about 10 seconds (Rapid Thermal Anneal: hereinafter referred to as RTA)
The N-type impurity 16 implanted into the surface layer of the silicon film 15 is diffused into the silicon film 15 of the NMOS region 11a and activated, and the P-type impurity 18 is diffused into the silicon film 15 of the PMOS region 11b. Activate with.

Next, in the fourth step, as shown in FIG. 1D, a conductive film 19 made of tungsten silicide (WSix) is deposited to a film thickness of 70 nm on the silicon film 15 by a low pressure CVD method. To do. As an example of specific film forming conditions of the conductive film 19, the material gas: tungsten hexafluoride (WF ₆ ) and monosilane (SiH ₄ ) film forming temperature: 380 ° C. As described above, a wiring layer having a polycide structure is formed by stacking the conductive film 19 made of WSix on the silicon film 15 made of polysilicon containing impurities. In addition to the above WSix, the conductive film 19 may be a silicide of a refractory metal such as titanium silicide (TiSix) or molybdenum silicide (MoSix) or a refractory material such as tungsten (W) or molybdenum (Mo). A metal or a metal compound such as titanium nitride (TiN) can be used.

Next, a silicon oxide film 20 serving as an offset oxide film 15 is formed on the upper surface of the conductive film 19 by the CVD method.
Deposition is performed with a film thickness of 0 nm. As an example of specific film forming conditions of the silicon oxide film 20, the material gas: SiH ₄ , oxygen (O ₂ ) film forming temperature: 420 ° C. are set.

After that, a resist pattern (not shown) is formed on the silicon oxide film 20 by the lithography method. The resist pattern 17 is formed in the NMOS region 11
The shape of the gate electrode pattern is formed in a and the PMOS region 11b. Next, by using this resist pattern as a mask, anisotropic etching using, for example, a fluorocarbon gas is performed to pattern the silicon oxide film 20, thereby forming an offset oxide film 20a made of the silicon oxide film 20.

Next, in the fifth step, as shown in FIG. 1 (5), after the resist pattern is removed, for example, chlorine gas and oxygen gas are used as etching gas using the offset oxide film 20a as a mask. The conductive film 19 and the silicon film 15 are patterned by performing anisotropic etching. Then, in the NMOS region (N-type pattern formation region) 11a, the N-type pattern 2 having a laminated structure of the silicon film 15 in which the N-type impurity 16 is diffused and the conductive film 19 is formed.
Form one. The N-type pattern 21 becomes a gate electrode of NMOS. Similarly, in the PMOS region (P-type pattern formation region) 11b, a P-type pattern 22 having a laminated structure of the silicon film 15 in which the P-type impurity 18 is diffused and the conductive film 19 is formed. This P-type pattern 22 is a PMOS
Becomes the gate electrode.

Thereafter, as shown in FIG. 2, N-type impurities for forming an N-type LDD diffusion layer 23a are introduced into the exposed surface layer of the substrate 11 in the NMOS region 11a by ion implantation. As an example of specific impurity introduction conditions, N type impurity: arsenic ion (As ⁺ ) implantation energy: 20 keV implantation dose amount: 5 × 10 ¹³ / cm ² .

In the same manner as described above, the PMOS region 1
The P-type LDD diffusion layer 23 is formed on the exposed surface layer of the substrate 11 of 1b.
A P-type impurity for forming b is introduced. As an example of specific impurity introduction conditions, P-type impurity: boron difluoride ion (BF ₂ ⁺ ) implantation energy: 20 keV implantation dose amount: 2 × 10 ¹³ / cm ² .

Next, a silicon oxide film is deposited to a thickness of 150 nm by the low pressure CVD method, and anisotropic etching is performed to form sidewalls of the N-type pattern 21 and the offset oxide film 20a on the upper surface thereof, and the P-type pattern 22. Sidewalls 24 are formed on the sidewalls of the offset oxide film 20a on the upper surface thereof.

Next, an N type for forming an N type source diffusion layer and a drain diffusion layer (hereinafter referred to as a source / drain diffusion layer) 25a on the exposed surface layer of the substrate 11 in the NMOS region 11a by ion implantation. Introduce impurities. As an example of a specific impurity introduction condition, N-type impurity: As ⁺ implantation energy: 20 keV implantation dose amount: 3 × 10 ¹⁵ / cm ² .

Further, in the same manner as described above, the PMOS region 1
A P-type impurity for forming a P-type source / drain diffusion layer 25b is introduced into the exposed surface layer of the substrate 11 of 1b.
As an example of specific impurity introduction conditions, P-type impurity: BF ₂ ⁺ implantation energy: 20 keV implantation dose amount: 2 × 10 ¹⁵ pieces / cm ² .

Next, RTA is performed at 1000 ° C. for 10 seconds to activate the impurities introduced into the substrate 11. Thereafter, although not shown here, the gate electrode and the source / drain diffusion layer 25a formed of the N-type pattern 21 and the P-type pattern 22 are formed by forming an interlayer insulating film, forming a contact hole, and forming a wiring material such as Al (aluminum). 25
Wiring of b is performed, and thereby a CMOS circuit is formed.

In the method of the first embodiment, the silicon film 15 portion of the PMOS region 11b is etched back by a predetermined film thickness determined by the etching rate ratio of P-type silicon and N-type silicon, and then the silicon film 15 portion is removed. By introducing the P-type impurity 18, the silicon film 15 can be compared with the case where the above etchback is not performed.
The silicon film 15 portion is thinned with almost no change in the diffusion state of impurities therein. Therefore, in the process described with reference to FIG. 1C, the etching rate is increased by diffusing the P-type impurity 18 and the silicon film 15 portion where the etching rate is increased by diffusing the N-type impurity 16. Patterning is performed at the same time with the thinned silicon film 15 portion. Therefore, in the PMOS region 11b, the etching rate of the silicon film which is slower than that of the NMOS region 11a is covered by the thinning of the silicon film 15 portion. Become. Therefore, the NMOS region 11a and the PMOS region 11b are etched without excess or deficiency, and it is possible to prevent the substrate 11 portion of the NMOS region 11a from being dug and the etching residue from remaining on the stepped portion of the PMOS region 11b.

In the first embodiment, the mask for introducing the P-type impurity 18 into the silicon film 15 in the PMOS region 11b and the silicon film 1 in the PMOS region 11b are used.
Since the same resist pattern 17 is used as the mask for etching the five portions, the N-type pattern 21 and the P-type pattern 22 can be formed as described above without increasing the number of masks. .

Next, a second embodiment of the present invention will be described with reference to FIGS. 3 (1) to 3 (5). The difference between the second embodiment described here and the first embodiment is that the etching of the silicon film 15 described with reference to FIG. 1 (1) in the first embodiment is shown in FIG. 3 (2). After diffusing the N-type impurity 16 and the P-type impurity 18 into the silicon film 15 as described above and as shown in FIG. 3D, the conductive film 1 is formed on the silicon film 15.
9 is performed before the film is formed, that is, in the step shown in FIG. In this step, the resist pattern 31 newly formed on the silicon film 15 is used as a mask to perform P
The silicon film 15 portion of the MOS region 11b is etched. Then, the other steps are performed in the same manner as in the first embodiment.

According to the method of the second embodiment, the patterning shown in FIG. 3 (5) is performed in the same manner as in the first embodiment, and in the PMOS region 11b, the NMOS region 11a is formed.
Since the etching rate of the silicon film is slower than that of the NMOS region 1, the thinning of the silicon film 15 portion covers the NMOS region 1.
The end points of etching are almost the same in 1a and the PMOS region 11b. Therefore, the NMOS region 11a and the PMOS region 11b are etched without excess or deficiency, and the substrate 11 portion of the NMOS region 11a is dug or the PMOS region 11 is etched.
The N-type pattern 21 and the P-type pattern 22 are formed on the substrate 11 without leaving an etch residue on the stepped portion b.

Next, a third embodiment of the present invention will be described with reference to FIGS. First, the process shown in FIG. 4A is performed in the same manner as shown in FIG. 3A in the second embodiment, and the field oxide film 12 is used to form the NMOS region 11a and PM.
A silicon film 15 is formed on the surface of the substrate 11 separated from the OS region 11b, and an N-type impurity 16 is formed on the silicon film 15.
And P-type impurities 18 are introduced. Next, the step shown in FIG. 4B is performed in the same manner as that shown in FIG. 3B in the second embodiment, and the silicon film 15 in the NMOS region 11a of the substrate 11 is processed.
The N-type impurity 16 is diffused into the portion to form the PMOS region 11b.
The P-type impurity 18 is diffused into the silicon film 15 portion of the above.

Then, in a step shown in FIG. 4C, a second silicon film 41 made of amorphous silicon is formed on the upper surface of the silicon film 15 by a low pressure CVD method so as to have a thickness of 30 to 100 nm.
Deposition is performed with a film thickness of about the same. As an example of a specific film forming condition for the second silicon film 41, the material gas: SiH deposition temperature: 550 ° C. is set. The thickness of the second silicon film 41 is the same as that of the silicon film 1 in the NMOS region 11a in which N-type impurities are diffused.
5 part and PMOS region 11b in which P-type impurities are diffused
From the etching rate ratio with respect to the silicon film 15 portion, the second silicon film 41 is set to a value such that the end points of the etching of the respective silicon film portions become the same. That is, the etching rate of the silicon film 15 portion in the NMOS region 11a is vn and the film thickness is tn, the etching rate of the silicon film 15 portion in the PMOS region 11b is vp, and the silicon film 15 and the second silicon film 41 in the PMOS region 11b. the total thickness of the bets case of a tp _2, sets the film thickness such that tp ₂ satisfying _{tn / vn = tp 2 / vp} .

Next, a resist pattern (not shown) having a shape covering at least the NMOS region 11a and opening on the PMOS region 11b is formed by lithography. Then, using this resist pattern as a mask, the second silicon film 41 is etched to form the NMOS region 11
Silicon layer 4 consisting of second silicon film 41 only on a
1a is formed.

After performing the above steps, the step shown in FIG. 4 (4) is performed in the same manner as described in the first embodiment with reference to FIG. 1 (4), and the silicon film 15 and the silicon layer 41.
A conductive film 19 is formed on a, and an offset oxide film 20a is formed on the conductive layer 19. Next, the step shown in FIG. 4 (5) is performed in the same manner as described with reference to FIG. 1 (5) in the first embodiment. However, here, the silicon layer 41a is also patterned together with the conductive film 19 and the silicon film 15. Then, an N-type pattern 42 having a laminated structure of the silicon film 15 portion into which the N-type impurity 16 is introduced, the silicon layer 41a, and the conductive film 19 is formed in the NMOS region 11a, and the PMO is formed.
A P-type pattern 43 including the conductive film 19 and the portion of the silicon film 15 into which the P-type impurity 18 is introduced is formed in the S region 11b. After that, the CMOS and the CMOS circuit are formed by similarly performing the steps after the step described with reference to FIG. 2 of the first embodiment.

In the method of the third embodiment, since the silicon film 15 portion is thickened by forming the silicon layer 41a on the silicon film 15 in the NMOS region 11a, the silicon film 15 portion is thickened. Compared with the case where the silicon film 15 is not formed, the silicon film 15 portion is thinned with almost no change in the diffusion state of impurities in the silicon film 15. Therefore, in the process described with reference to FIG. 4C, the etching rate is increased and the silicon film 15 is thickened by diffusing the N-type impurity 16.
Patterning of the portion and the portion of the silicon film 15 in which the etching rate is slowed by diffusing the P-type impurity 18 are simultaneously performed. Therefore, in the PMOS region 11b, the etching rate of the silicon film which is higher than that of the PMOS region 11b is covered by the thickening of the silicon film 15 portion.
In the OS region 11b, the end points of etching are almost the same.
Then, the NMOS region 11a and the PMOS region 11b are etched without excess or deficiency, the substrate 11 portion of the NMOS region 11a is not dug, and the N-type pattern 42 and the etching residue are not left on the stepped portion of the PMOS region 11b. The P-type pattern 43 can be formed. Note that N-type impurities are diffused from the silicon film 15 into the silicon layer 41a in a subsequent heat treatment step, and the conductive state of the silicon layer 41a is secured.

In the third embodiment described above, after the impurities are diffused in the silicon film 15 in the step shown in FIG. 4B, the silicon film is formed before the conductive film 19 is formed in the step shown in FIG. The layer 41a was formed. However, this silicon layer 41a
May be formed at any step after the gate oxide film 14 is formed in the step shown in FIG. 4A and before the conductive film 19 is formed in the step shown in FIG. . Particularly, when the silicon layer 41a is formed before performing the step of diffusing the impurities in the silicon film 15, the impurities are also diffused in the silicon layer 41a in this diffusing step.

Although the silicon film 15 is formed as a single layer in the above-described first to third embodiments, fluctuations in the threshold voltage due to impurity interdiffusion in the Dual Gate Process and impurities in the gate oxide film 14 (mainly Considering the effect of preventing the penetration of boron, it is desirable that the silicon film 15 has a two-layer structure.

[0042]

According to the above-described method of manufacturing a semiconductor device of the present invention, the silicon film portion of the PMOS region is thinned or the NMOS region of the NMOS region is thinned without substantially changing the diffusion state of impurities in the silicon film. By thickening the silicon film portion, the N-type silicon film portion and P
The end points of the etching of the silicon film portion of the mold can be almost the same. Therefore, it is possible to etch the silicon film in the NMOS region (N-type pattern forming region) and the PMOS region (P-type pattern forming region) without excess or deficiency, and the substrate portion of the N-type pattern forming region is dug. P
An N-type pattern having a laminated structure of a silicon film in which N-type impurities are diffused and a metal-based conductive film, and silicon in which P-type impurities are diffused, without leaving an etching residue on the stepped portion of the type pattern formation region. A semiconductor device having a P-type pattern having a laminated structure of a film and a metal-based conductive film can be formed.

[Brief description of drawings]

FIG. 1 is a sectional process diagram illustrating a first embodiment.

FIG. 2 is a sectional process diagram illustrating an embodiment.

FIG. 3 is a sectional process diagram illustrating a second embodiment.

FIG. 4 is a cross-sectional process diagram illustrating a third embodiment.

FIG. 5 is a graph showing an etching rate with respect to a sheet resistance of polysilicon.

FIG. 6 is a cross-sectional view illustrating a problem of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

11 substrate 11a NMOS region (N-type pattern forming region) 11b PMOS region (P-type pattern forming region) 1
5 Silicon Film 16 N-type Impurity 18 P-type Impurity 19 Conductive Film 21,42 N-type Pattern 22,43 P-type Pattern 41a Silicon Layer

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[Procedure amendment]

[Submission date] June 19, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction contents]

After that, in the step shown in FIG.
Amorphous silicon is formed on the upper surface of the contact film 15 by the low pressure CVD method.
The second silicon film 41 made of silicon is formed in a thickness of 30 to 100 nm.
Deposition is performed with a film thickness of about the same. Specific second silicon film
As an example of the film forming condition of No. 41, the source gas: SiH deposition temperature: 550 ° C. is set. The film thickness of the second silicon film 41 is N type.
Silicon film 1 of NMOS region 11a in which impurities are diffused
5 part and PMOS region 11b in which P-type impurities are diffused
From the etching rate ratio with the silicon film 15 part of
The second silicon film 41 is used to etch each silicon film portion.
The value is set so that the end points of ching are the same. sand
That is, the silicon film 15 portion in the NMOS region 11a
The etching rate of vn and the film thickness are tn,
The etching rate of the con film 41 is v_Two, Film thickness t _Twoage,
Etching of the silicon film 15 portion in the PMOS region 11b
When the ching speed is vp and the film thickness is tp, tn / vn
+ T_Two/ V_Two= Film thickness t that satisfies tp / vp_TwoSet
You.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction contents]

In the method of the third embodiment, since the silicon film 15 portion is thickened by forming the silicon layer 41a on the silicon film 15 in the NMOS region 11a, the silicon film 15 portion is thickened. In comparison with the case where the silicon film 15 is not formed, the silicon film 15 portion of the PMOS region is thinned with almost no change in the diffusion state of impurities in the silicon film 15. For this reason, FIG.
In the process described using (5), the etching rate is increased by diffusing the N-type impurity 16, and the etching rate is increased by diffusing the P-type impurity 18 and the thickened silicon film 15. The patterning is performed simultaneously with the portion of the silicon film 15 where the delay has occurred. Therefore, P
In the MOS region 11b, the silicon film 15 has a higher etching rate than the PMOS region 11b.
It is covered by thickening the part, and NMO is used in the above turning.
The end points of etching are almost the same in the S region 11a and the PMOS region 11b. Then, the NMOS region 11a and the PM
Excessive and sufficient etching is performed in the OS region 11b,
The N-type pattern 42 and the P-type pattern 43 can be formed without digging the substrate 11 portion of the OS region 11a and leaving no etching residue on the stepped portion of the PMOS region 11b. Note that N-type impurities are diffused from the silicon film 15 into the silicon layer 41a in a subsequent heat treatment step, and the conductive state of the silicon layer 41a is secured.

Claims (4)

[Claims] 1. A first step of forming a silicon film on a substrate having an N-type pattern forming region and a P-type pattern forming region, and introducing an N-type impurity into the N-type pattern forming region of the silicon film. A second step of introducing a P-type impurity into the P-type pattern forming region of the silicon film, diffusing the N-type impurity into the N-type pattern forming region of the silicon film, and forming a P-type pattern of the silicon film. A third step of diffusing the P-type impurities in the region, a fourth step of forming a metal-based conductive film on the silicon film, and a step of patterning the silicon film and the conductive film by etching, A method of manufacturing a semiconductor device, comprising: performing a fifth step of simultaneously forming an N-type pattern and a P-type pattern on a substrate, wherein the silicon is used after the first step and in the second step. Of before introducing P-type impurities into the P-type pattern forming region,
A method of manufacturing a semiconductor device, which comprises performing a step of etching back a P-type pattern formation region of the silicon film by a predetermined thickness. 2. A first step of forming a silicon film on a substrate having an N-type pattern forming region and a P-type pattern forming region, and introducing an N-type impurity into the N-type pattern forming region of the silicon film. A second step of introducing a P-type impurity into the P-type pattern forming region of the silicon film, diffusing the N-type impurity into the N-type pattern forming region of the silicon film, and forming a P-type pattern of the silicon film. A third step of diffusing the P-type impurities in the region, a fourth step of forming a metal-based conductive film on the silicon film, and a step of patterning the silicon film and the conductive film by etching, A method of manufacturing a semiconductor device, comprising: performing a fifth step of simultaneously forming an N-type pattern and a P-type pattern on a substrate, wherein the silicon wafer is formed after the third step and before the fourth step. The method of manufacturing a semiconductor device characterized by a step of only etching back a predetermined thickness of the P-type pattern forming region of the membrane. 3. A first step of forming a silicon film on a substrate having an N-type pattern forming region and a P-type pattern forming region, and introducing an N-type impurity into the N-type pattern forming region of the silicon film. A second step of introducing a P-type impurity into the P-type pattern forming region of the silicon film, diffusing the N-type impurity into the N-type pattern forming region of the silicon film, and forming a P-type pattern of the silicon film. A third step of diffusing the P-type impurities in the region, a fourth step of forming a metal-based conductive film on the silicon film, and a step of patterning the silicon film and the conductive film by etching, A method for manufacturing a semiconductor device, which comprises a fifth step of simultaneously forming an N-type pattern and a P-type pattern on a substrate, comprising: forming the N-type pattern in a step before the fourth step. The method of manufacturing a semiconductor device characterized by a step of forming a silicon layer having a predetermined thickness on the substrate of the band or on the silicon layer of the N-type pattern forming region. 4. An N-type pattern having a laminated structure of a silicon film in which N-type impurities are diffused and a metal-based conductive film, a silicon film in which P-type impurities are diffused, and a metal-based conductive film on a substrate. In the semiconductor device having a P-type pattern having a laminated structure of, the silicon film forming the N-type pattern is thicker than the silicon film forming the P-type pattern by a predetermined thickness. .