JP3327109B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A complementary MOS transistor composed of an N-channel type MOS field effect transistor (hereinafter referred to as NMOSFET) and a P-channel type MOS field effect transistor (hereinafter referred to as PMOSFET) has low power consumption and high speed. It is widely used as a semiconductor device having a large number of LSI configurations, including a memory device and a logic device. The miniaturization of the FET gate length has been progressing along with the high integration, and at room temperature operation of MOSFETs having a gate length of 0.1 μm or less has been confirmed at present.

As the gate electrode of the conventional PMOSFET, an N.sup. ⁺ Type gate electrode is used similarly to the NMOSFET because of the simplicity of the process and the high performance due to the buried channel type. On the other hand, in MOSFETs of the so-called deep submicron generation or later, it is difficult to suppress the short channel effect in the buried channel type. Therefore, in order to suppress the short channel effect, the surface channel type P
⁺ Type gate application becomes effective. Therefore, NMOSF
ET is an N ⁺ type gate electrode, and PMOSFET is P ⁺
It has a so-called dual gate structure in which a gate electrode is used.

[0004]

SUMMARY OF THE INVENTION An NMOSFET is changed to N ⁺
In order to manufacture gate electrodes of different polarities, such as a P-type gate electrode and a PMOSFET, like a P ⁺ -type gate electrode, arsenic (As) or phosphorus is added to the polycrystalline silicon constituting the gate electrode and to the N ⁺ -type portion. In many cases, (P) is doped, and the P ⁺ -type portion is formed by doping boron (B) or boron difluoride (BF ₂ ). Doping is usually
It is often performed by ion implantation.

However, when a wiring structure (polycide structure) in which polycrystalline silicon and metal silicide of the gate electrode are laminated or a wiring structure in which polycrystalline silicon and metal are laminated is used, impurities such as metal silicide and impurities in the metal are removed. Since the diffusion rate is very high (about four orders of magnitude faster in diffusion coefficient) than the diffusion rate of impurities in silicon and the diffusion rate of impurities in silicon oxide (SiO ₂ ), P ⁺ -type impurities and N ⁺ -type The impurities cause interdiffusion, and the impurities in the polycrystalline silicon compensate each other.

Therefore, polycrystalline silicon of the gate electrode is converted into polycrystalline silicon having a large grain size, or ions are implanted into the polycrystalline silicon, and then impurities are diffused into the polycrystalline silicon by annealing. Methods for depositing metals have been proposed. However, also in the above method, since the N ⁺ -type region and the P ⁺ -type region of the polycrystalline silicon are simultaneously patterned, the N ⁺ -type polycrystalline silicon, the P ⁺ -type polycrystalline silicon, and the non-doped The respective etching rates of polycrystalline silicon are significantly different.

As shown in FIG. 7, an element isolation region 114 for separating an N-type region 112 and a P-type region 113 is formed on a silicon substrate 111, and a gate insulating film 121 is formed. Form. Thereafter, impurities are introduced into the polycrystalline silicon film by an ion implantation method to form an N ⁺ -type polycrystalline silicon film 122N and a P ⁺ -type polycrystalline silicon film 122P. Next, after the silicide film 123 is formed, the silicide film 123 and the polycrystalline silicon films 122N,
By etching 2P, an N-type pattern 125 and a P-type pattern 126 are formed. In such a case, when the P ⁺ -type polycrystalline silicon film 122P is etched so that no residue is generated, the gate insulating film 121 serving as a base of the N ⁺ -type polycrystalline silicon film 122N having a high etching rate is formed. The silicon substrate 111 is dug by being excessively etched (portion indicated by A in FIG. 7).
If etching is performed so that the first N-type region 112 is not dug, a problem arises in that a polysilicon residue 131 is generated in an etching region of the P ⁺ -type polycrystalline silicon film 122P having a low etching rate, particularly in a step portion. There is. This is because the N ⁺ -type polycrystalline silicon film 122N having a high etching rate is excessively etched and the P ⁺ -type polycrystalline silicon film 122P having a low etching rate is excessively etched.

In particular, N⁺Shaped polycrystalline silicon etchin
Great is P⁺Type polycrystalline silicon, non-doped polycrystalline
The etching rate is very fast compared to crystalline silicon.
And is known. Where etching rate and sheet resistance
Will be described with reference to FIG. In FIG. 8, the vertical axis is
Indicate the switching speed, and log the sheet resistance on the horizontal axis
Show. As shown in FIG.⁺Type of polycrystalline silicon
The switching rate is not only the dose of phosphorus (P),
N⁺Closely related to the resistivity of polycrystalline silicon (phosphorus addition)
Involved. Even with the same impurity dose, N⁺
Type polycrystalline silicon has lower etching rate
Fast, P⁺Type polycrystalline silicon (boron added), no
The difference between the etching rate and the added polycrystalline silicon is large.
Become. Note that N⁺Mold for forming polycrystalline silicon
The ion implantation conditions are acceleration energy 150 keV,
1 × 10¹⁶Pieces / cm^Two, P⁺Mold polycrystalline silicon
The ion implantation conditions for forming are an acceleration energy of 50
keV, dose amount 1 × 10¹⁶Pieces / cm^TwoSet to. Ma
The etching of the polycrystalline silicon is performed using chlorine (Cl). _Two)gas
And the etching atmosphere was set to 13.3 kPa.

[0009]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems. That is, in the first manufacturing method, a silicon film is formed on a substrate in a first step, an N-type impurity is introduced into a region of the silicon film where an N-type pattern is to be formed in a second step, and a P-type pattern is to be formed. A P-type impurity is introduced into the region, and the N-type impurity is diffused into the silicon film in the region where the N-type pattern is to be formed and the P-type impurity is diffused into the silicon film in the region where the P-type pattern is to be formed by annealing in the third step. Let it. Then, in a fourth step, a metal-based conductive film is formed on the silicon film, and in a fifth step, the silicon film is patterned together with the metal-based conductive film by etching to form an N-type pattern and a P-type pattern simultaneously. After the third step and before the fifth step, a heat treatment for causing impurities at lattice points of the silicon film to be in a supersaturated state is performed at a predetermined temperature in the range of 700 ° C to 900 ° C.

In a second manufacturing method, a silicon film is formed on a substrate in a first step, and an N-type impurity is introduced into a region of the silicon film where an N-type pattern is to be formed in a second step to form a P-type pattern. A P-type impurity is introduced into the planned region, and an N-type impurity is diffused into the silicon film in the region where the N-type pattern is to be formed by annealing in the third step, and the P-type impurity is silicon in the region where the P-type pattern is to be formed. Diffusion in the film.
Thereafter, when the silicon film is patterned by etching in the fourth step to form an N-type pattern and a P-type pattern at the same time, after the third step and before the fourth step, impurities at lattice points of the silicon film are formed. Is performed at a predetermined temperature in the range of 700C to 900C.

In each of the above manufacturing methods, the heat treatment for supersaturating impurities at lattice points of the silicon film is performed at a predetermined temperature in the range of 700 ° C. to 900 ° C. before the etching of the silicon film. The resistivity can be increased. As a result, the etching rate of the N-type region of the silicon film decreases, and the etching rate of the P-type region of the silicon film increases. Therefore, the difference between the two etching rates becomes smaller. Therefore, even if the N-type region of the silicon film and the P-type region of the silicon film are etched at the same time, the difference between the two etching rates is small. When a silicon substrate is dug or a P-type region of a silicon film having a low etching rate is etched, residue of the silicon film does not occur at a step portion.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an example of the first embodiment according to the first invention having a manufacturing process for forming a metal-based conductive film on a silicon film will be described with reference to FIGS. 1 and 2. It will be explained by. 1 and 2, the complementary MIS (Me
tal Insulator semiconductor) An example of forming a transistor is shown.

As shown in FIG. 1A, for example, a local oxidation method [for example, LOCO by wet oxidation at 950 ° C.]
S (Local Oxidation of Silicon) method], a field oxide film 12 serving as an element isolation region is formed on the front surface side of the silicon substrate 11.

Next, for example, by ion implantation, NM
A P-type well region (not shown) is formed in a region where the OSFET is to be formed, and a buried layer (not shown) for preventing punch-through of the transistor is formed.
Further, ion implantation for adjusting the threshold voltage Vth of the transistor is performed to form the NMOS channel formation region 13.
To form Similarly, for example, by ion implantation, P
An N-type well region (not shown) is formed in a region where the MOSFET is formed, and a buried layer (not shown) for preventing punch-through of the transistor is formed.
Further, ion implantation for adjusting the threshold voltage Vth of the transistor is performed to form the PMOS channel formation region 14.
To form

As shown in FIG. 1B, the exposed silicon substrate 11 is subjected to thermal oxidation (eg, pyrogenic oxidation in an atmosphere consisting of hydrogen and oxygen at 850 ° C.). A gate oxide film 15 on the surface;
For example, it is formed to a thickness of 8 nm.

Next, as a first step, chemical vapor deposition (hereinafter referred to as CVD) under reduced pressure
A silicon film 16 is formed on the field oxide film 12 and the gate oxide film 15 by an apour deposition method. First, a polycrystalline silicon film 17 is deposited to a thickness of, for example, 70 nm. In the reduced pressure CVD method,
As an example, the polycrystalline silicon film 17 was formed under the following conditions: source gas: monosilane (SiH ₄ ); film formation temperature: 610 ° C. Subsequently, an amorphous silicon film 18 is formed on the polycrystalline silicon film 17 by, for example,
m. In this low-pressure CVD method, the amorphous silicon film 18 was formed under the conditions of, for example, a raw material gas: monosilane (SiH ₄ ) and a film forming temperature: 550 ° C. Here, the polycrystalline silicon film 17 and the amorphous silicon film 18 are referred to as a silicon film 16.

As shown in FIG. 1C, as a second step, a region where an N-type pattern is to be formed (here, an NMOSFET is to be formed) is formed on the amorphous silicon film 18 by a coating technique and a lithography technique. Area) 19
A resist mask (not shown) having an upper opening is formed.
Thereafter, an N-type impurity is ion-implanted by an ion implantation method using the resist mask. In the above-described ion implantation method, for example, the ion implantation was performed under the following conditions: N-type impurities: phosphorus ions (P ⁺ ), acceleration energy: 10 keV, and dose: 5 × 10 ¹⁵ / cm ² . Thereafter, the resist mask is removed by, for example, ashing.

Subsequently, a resist mask (shown in the figure) having an opening on a region where a P-type pattern is to be formed (here, a region where a PMOSFET is to be formed) 20 is formed on the amorphous silicon film 18 by a coating technique and a lithography technique. (Omitted). Thereafter, P-type impurities are ion-implanted by an ion implantation method using the resist mask. In the above-described ion implantation method, for example, the ion implantation was performed under the following conditions: P-type impurity: boron ion (B ⁺ ), acceleration energy: 5 keV, dose amount: 5 × 10 ¹⁵ / cm ² . . Thereafter, the resist mask is removed by, for example, ashing.

Next, annealing is performed as a third step. In this annealing, the amorphous silicon film 18 is crystallized to generate a polycrystalline silicon film having a crystal grain size larger than that of the polycrystalline silicon film 17 formed by the CVD method. Hereinafter, the polycrystalline silicon film formed here and the polycrystalline silicon film 17 are referred to as a polycrystalline silicon film 21. In the above-mentioned annealing, as an example, a processing apparatus: a furnace annealing apparatus (furnace annealing apparatus) a processing atmosphere: an inert atmosphere [for example, nitrogen (N ₂ ),
Argon (Ar), etc.], annealing temperature: 650 ° C., annealing time: 10 hours, the annealing was performed.

Subsequently, a rapid heating process (hereinafter, referred to as RTA, RTA stands for Rapid Thermal Annealing) is performed to remove impurities distributed on the surface of the polycrystalline silicon film 21 by ion implantation into the polycrystalline silicon film 21. Spreads and activates. In the above RTA, as an example, the RTA was performed under the conditions of an annealing temperature of 1000 ° C. and an annealing time of 10 seconds. as a result,
An N ⁺ type region 21N and a P ⁺ type region 21P were formed in the polycrystalline silicon film 21.

Next, as shown in FIG. 1D, as a fourth step, for example, a tungsten silicide (WSi ₂ ) film is formed as a metal-based conductive film 22 on the polycrystalline silicon film 21 by a low pressure CVD method. Deposit to a thickness of 70 nm. Further, a silicon oxide film having a thickness of, for example, 150 nm is formed on the metal-based conductive film 22 by a CVD method. In the CVD method for forming the metal-based conductive film 22 made of tungsten silicide, for example, the conditions are set as follows: source gas: tungsten hexafluoride (WF ₆ ) and monosilane (SiH ₄ ); film formation temperature: 380 ° C. Then, the metal-based conductive film 22 was formed. The CVD conditions for the silicon oxide film were set, for example, as follows: source gas: monosilane (SiH ₄ ) and oxygen (O ₂ ); film formation temperature: 420 ° C., and the silicon oxide film was formed.

Next, a resist mask (not shown) is formed by a coating technique and a lithography technique, and then the silicon oxide film is patterned by anisotropic etching using the resist mask to form a gate electrode pattern. An insulating film pattern 23 serving as an etching mask is formed. In the anisotropic etching, for example, a fluorocarbon-based gas was used as an etching gas. Subsequently, the resist mask is removed by ashing and cleaning. FIG. 1D shows a state where the resist mask is removed.

Thereafter, a heat treatment (hereinafter referred to as "annealing") for making the impurities at the lattice points of the polycrystalline silicon film 21 supersaturated is performed. This annealing is performed at a predetermined temperature in the range of 700 ° C. to 900 ° C., preferably 800 ° C.
This is performed at a predetermined temperature in a range of not less than 850 ° C. In the above annealing, as an example, the annealing was performed under the conditions of an annealing atmosphere: a nitrogen (N ₂ ) atmosphere, an annealing temperature: 800 ° C., and an annealing time: 10 minutes. Needless to say, the annealing atmosphere and the annealing time are not limited to the above-mentioned times, and the annealing atmosphere may be an inert atmosphere, and the annealing time is set so that the impurities at the lattice points of the polycrystalline silicon film 21 are supersaturated. It is sufficient if it is a sufficient time to make it. As a result of this annealing, the conductivity of the polycrystalline silicon film 21 decreases. This annealing is performed by the activation annealing (R
After performing TA), it is sufficient to form the silicon oxide film before forming the metal-based conductive film 22 or after forming the metal-based conductive film 22, for example, before forming the gate electrode pattern in the next step. You may go before doing.

Next, as shown in FIG. 1 (5), as a fifth step, anisotropic etching using the insulating film pattern 23 as an etching mask [etching gas: chlorine (Cl)
By ₂₎ and oxygen (O _2)], and etching of the tungsten polycide a tungsten silicide metallic conductive film 22 made of a polycrystalline silicon film 21, the N ⁺ -type gate electrode pattern N-type pattern 24 and the P ^A P-type pattern 25 serving as a ⁺ -type gate electrode pattern is formed. At this time, since the annealing lowers the conductivity of the polycrystalline silicon film 21, the chlorine (C
In the etching according to 1), the N
The etching rate of the ⁺ type region 21N is lower than before the annealing, and the etching rate of the P ⁺ type region 21P is higher than before the annealing. Therefore, the etching rate of N ⁺ type region 21N of polycrystalline silicon film 21 and P
The difference from the etching rate in ⁺ type region 21P is reduced.

Then, as shown in FIG. 2, an N-type LDD (Lightweight) is formed by, for example, a coating technique and a lithography technique.
tly Doped Drain) After forming a resist pattern (not shown) with an opening formed on the region where the diffusion layer is to be formed,
By ion implantation using this resist pattern as a mask, N-type impurity ions are implanted into the silicon substrate 11 to form an N-type LDD diffusion layer. In the above-described ion implantation, as an example, the ion implantation was performed under the following conditions: N-type impurity ion: arsenic ion (As ⁺ ), acceleration voltage: 20 keV, and dose: 5 × 10 ¹³ / cm ² . Thereafter, the resist pattern is removed by, for example, ashing and a cleaning process.

Subsequently, a resist pattern (not shown) having an opening formed on a region where a P-type LDD diffusion layer is to be formed is formed by, for example, a coating technique and a lithography technique, and this resist pattern is used as a mask. P-type impurity ions are implanted into the silicon substrate 11 by ion implantation.
To form a P-type LDD diffusion layer 27. In the above ion implantation, as an example, a P-type impurity ion: boron difluoride ion (B
F ₂ ⁺ ), acceleration voltage: 20 keV, dose: 2 × 10 ¹³ / cm ² , and the ion implantation was performed. Thereafter, the resist pattern is removed by, for example, ashing and a cleaning process.

Thereafter, a silicon oxide film is deposited to a thickness of, for example, 150 nm by a low pressure CVD method. Thereafter, the silicon oxide film is etched by anisotropic etching to form a sidewall insulating film 28 on each side wall of the N-type pattern 24 and the P-type pattern 25.

Next, a resist pattern (not shown) having an opening formed on a region where an N ⁺ -type source / drain diffusion layer is to be formed is formed by, for example, a coating technique and a lithography technique. Subsequently, N-type impurity ions are implanted into the silicon substrate 11 by an ion implantation method using this resist pattern as a mask to form an N ⁺ -type source / drain diffusion layer 29. In this ion implantation, N
The pattern 24 and the sidewall insulating film 28 also serve as a mask. In the above-described ion implantation, as an example, the ion implantation was performed under the following conditions: N-type impurity ion: arsenic ion (As ⁺ ), acceleration voltage: 20 keV, and dose: 3 × 10 ¹⁵ / cm ² . Thereafter, the resist pattern is removed by, for example, ashing and a cleaning process.

Subsequently, a resist pattern (not shown) having an opening in a region where a P ⁺ type source / drain diffusion layer is to be formed is formed by, for example, a coating technique and a lithography technique. Subsequently, P-type impurity ions are implanted into the silicon substrate 11 by an ion implantation method using the resist pattern as a mask to form a P ⁺ -type source / drain diffusion layer 30. In this ion implantation, P
The mold pattern 25 and the sidewall insulating film 28 also serve as a mask. In the above ion implantation, as an example, a P-type impurity ion: boron difluoride ion (B
F ₂ ⁺ ), the acceleration voltage: 20 keV, the dose: 3 × 10 ¹⁵ / cm ² , and the ion implantation was performed. Thereafter, the resist pattern is removed by, for example, ashing and a cleaning process.

Next, impurities are activated by RTA. In the RTA, as an example, the annealing was performed under the conditions of an annealing temperature of 1000 ° C. and an annealing time of 10 seconds.

As described above, NMOSFET 1 and P
MOSFET 2 and complementary MIS transistor 3
Was formed.

In the first embodiment, the N-type pattern 24
Before the etching for forming the P-type pattern 25, the polycrystalline silicon film 2 is subjected to RTA at 1000 ° C. for 10 seconds.
Activated by introducing impurities into one lattice point,
Since the annealing is performed at a predetermined temperature in the range of 00 ° C., the impurities in the lattice points of the polycrystalline silicon film 21 become supersaturated, and at least a part thereof becomes inactive. Therefore, the conductivity of polycrystalline silicon film 21 decreases. In other words, the sheet resistance can be increased. When the annealing temperature is higher than 900 ° C., the supersaturated state of impurities is reduced, so that the conductivity does not decrease. In the region where boron is introduced, penetration of boron occurs. On the other hand, when the annealing temperature is lower than 700 ° C., the impurities themselves do not move, so that the supersaturated state is not achieved. Therefore, no inactivation occurs.

The etching rate of polycrystalline silicon is conductive.
The mechanism that depends on rate is considered as follows. silicon
(Polycrystalline silicon) is etched with chlorine radio
After ion adsorption, energy of ion bombardment is given
By using silicon chloride (SiCl _x)
As a result, the etching reaction proceeds. Where halogen
The more electrons attach to radicals and become negative radicals, the more
Activation energy for the etching reaction decreases,
Rate increases. In other words, silicon (polycrystalline silicon)
Kon) is N⁺The higher the carrier concentration in the mold, the more etching
The concentration of negative radicals in the film increases and the etching rate increases
Will be added. Also, P⁺About the type, the explanation above
Due to the reverse mechanism, the higher the carrier concentration, the
Great decreases.

FIGS. 3 and 4 show the relationship between the sheet resistance of polycrystalline silicon and the annealing temperature when annealing is performed for 10 minutes after RTA processing at 1000 ° C. for 10 seconds . In each figure, the vertical axis shows the sheet resistance, and the horizontal axis shows the annealing temperature.

FIG. 3A shows N ⁺ type silicon (polycrystalline silicon) formed by ion-implanting phosphorus, followed by RTA at 1000 ° C. for 10 seconds, and then at each temperature for 10 minutes. 3 shows the sheet resistance when annealing was performed. As shown in this figure, approximately 800
At ° C, the sheet resistance is maximum (conductivity is minimum). Therefore, the etching rate of N ⁺ -type silicon (polycrystalline silicon) into which phosphorus has been introduced by annealing is reduced.

FIG. 3 (2) shows that after P ⁺ type silicon (polycrystalline silicon) is formed by ion implantation of boron, RTA is performed at 1000 ° C. for 10 seconds, and then at each temperature for 10 minutes. 3 shows the sheet resistance when annealing was performed. As shown in this figure, approximately 80
At 0 ° C. or higher (up to 900 ° C. in the figure), the sheet resistance becomes maximum (conductivity is minimum). Therefore, the etching rate of P ⁺ -type silicon (polycrystalline silicon) into which boron has been introduced by annealing is increased.

FIG. 4A shows an N ⁺ type silicon (polycrystalline silicon) formed by ion implantation of arsenic, followed by RTA at 1000 ° C. for 10 seconds, and then at each temperature for 10 minutes. 3 shows the sheet resistance when annealing was performed. As shown in this figure, approximately 800
The sheet resistance becomes maximum (conductivity is minimum) between 850 ° C. and 850 ° C. Therefore, the etching rate of N ⁺ -type silicon (polycrystalline silicon) into which arsenic is introduced by annealing is reduced.

FIG. 4 (2) shows that after P ⁺ type silicon (polycrystalline silicon) is formed by ion-implanting boron difluoride, RTA is performed at 1000 ° C. for 10 seconds, and then at each temperature. 3 shows the sheet resistance when annealing was performed for 10 minutes. As shown in this figure,
At about 800 ° C. or higher (up to 900 ° C. in the figure), the sheet resistance becomes maximum (conductivity is minimum). Therefore, the etching rate of P ⁺ type silicon (polycrystalline silicon) implanted with boron difluoride by annealing is increased.

What has been described with reference to FIGS. 3 and 4
As is evident from⁺Type silicon (polycrystalline silicon)
N) and P⁺Mold silicon (polycrystalline silicon)
By performing annealing at 800 ° C. to 850 ° C.
The sheet resistance is maximum (conductivity is minimum). in this way
The effect of increasing the sheet resistance is as follows.
Appear in the ring. Therefore, the annealing temperature range
Enclosed at 700 ° C. or more and 900 ° C. or less, preferably 80 ° C.
The temperature was set to 0 ° C or higher and 850 ° C or lower. As a result, N⁺Mold series
Con (polycrystalline silicon) reduces the etching rate,
P⁺Etching on silicon (polycrystalline silicon)
Increase, so N ⁺Type silicon (polycrystalline silicon)
N) and P⁺Type silicon (polycrystalline silicon)
The difference in the switching rates will be reduced.

Therefore, the first embodiment will be described.
As described above, the N⁺Type area and many
P of crystalline silicon film 21⁺Etch simultaneously with mold area
Even if patterning is performed by
N of 1⁺Rate of polysilicon region and polycrystalline silicon film
21 P⁺The difference from the etching rate of the mold area is reduced
You. For this reason, conventionally, the etching rate was high
N of crystalline silicon film 21 ⁺Exposure when etching the mold area
The problem that the silicon substrate 11 to be output can be dug, and
Conventionally, a polycrystalline silicon film 2 having a low etching rate
1 P⁺When the region is etched, the polycrystalline silicon
The problem that recon residue is generated is solved.

Next, an example of the second embodiment according to the first invention having a manufacturing process for forming a metal-based conductive film on a silicon film will be described with reference to the manufacturing process diagram of FIG. FIG.
Here, an example in which a complementary MIS transistor is formed as in FIGS. 1 and 2 will be described. The same components as those described in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 5A, the field oxide film 12 is formed on the surface side of the silicon substrate 11 in the same manner as in the first embodiment described with reference to FIGS.
To form Next, P is added to the region where the NMOSFET is formed.
A mold well region (not shown) is formed, and a buried layer (not shown) for preventing punch-through of the transistor is formed. Further, ion implantation for adjusting the threshold voltage Vth of the transistor is performed,
A channel forming region 13 is formed. Similarly, PMOSF
An N-type well region (not shown) is formed in a region where the ET is to be formed, and a buried layer (not shown) for preventing punch-through of the transistor is formed. Further, ion implantation for adjusting the threshold voltage Vth of the transistor is performed to form the PMOS channel formation region 14.

Next, a gate oxide film 15 is formed on the exposed surface of the silicon substrate 11. Next, as a first step, a silicon film 16 is formed on the field oxide film 12 and the gate oxide film 15 by a polycrystalline silicon film 17.
(For example, a thickness of 70 nm) and an amorphous silicon film 18 (for example, a thickness of 50 nm).

Next, as shown in FIG. 5A, as a second step, an N-type pattern formation region (here, NMOSFET formation) is formed on the amorphous silicon film 18 by a coating technique and a lithography technique. (Scheduled area)
A resist mask (not shown) having an opening on top of 19 is formed. Thereafter, an N-type impurity is ion-implanted by an ion implantation method using the resist mask. In the ion implantation of the N-type impurity, the ion implantation was performed under the same conditions as those described in the first embodiment. Thereafter, the resist mask is removed by, for example, ashing.

Subsequently, a resist mask having an opening on a region where a P-type pattern is to be formed (here, a region where a PMOSFET is to be formed) 20 is formed on the amorphous silicon film 18 by a coating technique and a lithography technique. (Omitted). Thereafter, P-type impurities are ion-implanted by an ion implantation method using the resist mask. In the P-type impurity ion implantation method, the ion implantation was performed under the same conditions as those described in the first embodiment. Thereafter, the resist mask is removed by, for example, ashing.

Next, annealing is performed as a third step. By performing this annealing, the amorphous silicon film 18 is formed.
Is crystallized to generate polycrystalline silicon having a crystal grain size larger than that of the polycrystalline silicon formed by the CVD method. Hereinafter, the polycrystalline silicon film formed here and the polycrystalline silicon film 17 are combined with the polycrystalline silicon film 2.
Let it be 1. At the same time, impurities are added to the polycrystalline silicon film 2.
Diffusion into 1. Specifically, the silicon substrate 11 is
It is put into an annealing atmosphere (for example, a nitrogen atmosphere) heated to 00 ° C., and is heated from 600 ° C. to 800 ° C. at a rate of 5 ° C./min or less. Thereby, the grain size of the amorphous silicon film 18 is increased. Subsequently, the impurities at the lattice points of the polycrystalline silicon film 21 are supersaturated by maintaining the temperature at 800 ° C. for 10 minutes. As a result, the conductivity of the polycrystalline silicon film 21 decreases. In the same annealing step, the impurity is diffused and the impurity is activated. As a result, an N ⁺ type region 21N and a P ⁺ type region 21P were formed in the polycrystalline silicon film 21.

As a matter of course, the annealing temperature, the annealing atmosphere, and the annealing time are not limited to the above. The annealing temperature is a predetermined temperature in a range of 700 ° C. or more and 900 ° C. or less, which desirably makes impurities at lattice points of the polycrystalline silicon film 21 into a supersaturated state.
The temperature may be a predetermined temperature in the range of 50 ° C. or less. The annealing atmosphere may be an inert atmosphere. Furthermore, the annealing time may be a time sufficient to make the impurities at the lattice points of the polycrystalline silicon film 21 into a supersaturated state.

By performing such annealing, the annealing can be simplified more than in the first embodiment. Therefore, the throughput can be improved. Although the temperature rise start temperature is set to 600 ° C., the temperature rise may be started from a lower temperature.

Next, as shown in FIG. 5B, a polycrystalline silicon film 21 is formed on the polysilicon film 21 in the same manner as in the first embodiment.
As the metal-based conductive film 22, for example, a tungsten silicide film is deposited to a thickness of 70 nm. Further, a silicon oxide film having a thickness of, for example, 150 nm is formed on the metal-based conductive film 22 to form a so-called tungsten polycide wiring layer with an offset oxide film.

Next, the silicon oxide film is patterned by a coating technique and a lithography technique to form an insulating film pattern 23 serving as an etching mask when forming a gate electrode pattern. Next, the insulating film pattern 2
3 is a metal-based conductive film 22 made of tungsten silicide by anisotropic etching using 3 as an etching mask.
And etching of a tungsten polycide made of a polycrystalline silicon film 21 (for example, a mixed gas of chlorine and oxygen is used as an etching gas) to form an N-type pattern 24 serving as an N-type gate electrode pattern and a P-type And a P-type pattern 25 serving as the gate electrode pattern of FIG. At this time, since the annealing lowers the conductivity of the polycrystalline silicon film 21, the etching rate of the N ⁺ -type region 21N of the polycrystalline silicon film 21 in the etching with chlorine is lower than that before the annealing , and the P ⁺ -type etching is performed. The etching rate of the region 21P is higher than before the annealing . Therefore, the N ⁺ type region 2 of the polycrystalline silicon film 21
The difference between the etching rate at 1N and the etching rate at P ⁺ -type region 21P is reduced.

In the same manner as in the first embodiment described above with reference to FIG. 2, as shown in FIG. 5C, an N-type L
A DD diffusion layer 26 is formed, and a P-type pattern 25 is formed.
A P-type LDD diffusion layer 27 is formed on the silicon substrate 11 on the side of the above. After that, a sidewall insulating film 28 is formed on each side wall of the N-type pattern 24 and the P-type pattern 25.

Next, the LDD on the side of the N-type pattern 24 is placed on the silicon substrate 11 on the side of the N-type pattern 24.
An N ⁺ type source / drain diffusion layer 29 is formed through a part of the diffusion layer 26. Similarly, a P ⁺ -type source / drain diffusion layer 30 is formed on the silicon substrate 11 on the side of the P-type pattern 25 via a part of the LDD diffusion layer 27 on the P-type pattern 25 side. Next, each impurity of the LDD diffusion layers 26 and 27 and the source / drain diffusion layers 29 and 30 is activated by RTA.

As described above, NMOSFET 1 and P
MOSFET 2 and complementary MIS transistor 3
Was formed.

In the second embodiment, the temperature is raised from 600 ° C., heated to 800 ° C. to 850 ° C., and
A predetermined temperature in a range of 0 ° C. to 850 ° C. for a predetermined time (for example, 1
(0 min), the annealing is performed, so that the grain size of polycide, the impurity diffusion, and the activation treatment are also used, and the number of steps is reduced as compared with the process described in the first embodiment. The effect is obtained. Therefore, this second
Even in the manufacturing method according to the embodiment, as described in the first embodiment, when the N ⁺ -type region 21N and the P ⁺ -type region 21P of the polycrystalline silicon film 21 are simultaneously etched, the N ⁺ prevents the etching rate of the etching rate and the P ⁺ -type region 21P type region 21N are significantly different, the silicon substrate 11 fast N ⁺ -type region 21N etching rate is dug, and etching rate slow P ⁺ -type region 21P The problem that polycrystalline silicon residue is generated at the step portion is solved.

In the first and second embodiments, the silicon film 16 has a two-layer structure including the polycrystalline silicon film 17 and the amorphous silicon film 18, but may be a single-layer silicon film. Further, the tungsten polycide structure using a tungsten silicon film for the metal-based conductive film 22 has been described. However, the metal-based conductive film 22 may be a so-called high-melting metal silicide such as titanium silicide or cobalt silicide, or a so-called tungsten silicide or molybdenum. A metal compound such as a high melting point metal, titanium nitride, or titanium nitride oxide may be used. Alternatively, a stacked structure thereof may be used.

Further, in each of the above-described embodiments, before forming the metal-based conductive film 22, impurities distributed at a high concentration near the upper layer of the polycrystalline silicide film 21 are formed in the lower layer direction of the polycrystalline silicon film 21. Spreading. for that reason,
It has been confirmed that even if impurities in the polycrystalline silicon film 21 are absorbed into the metal-based conductive film 22 by annealing after the formation of the metal-based conductive film 22, the characteristics are not adversely affected.

In each of the above embodiments, since the metal-based conductive film 22 is a tungsten silicide film, a self-aligned silicide is formed when a structure in which the above-described polycide structure is applied to the gate electrode is formed. A low-resistance wiring layer (gate electrode) is formed without causing a thin line effect caused by the formation.

Next, an example of an embodiment according to the second invention having a manufacturing process for patterning only silicon films having different conductivity types will be described as a third embodiment with reference to the manufacturing process diagram of FIG. In FIG. 6, the same components as those described in the first embodiment are denoted by the same reference numerals.

In the same manner as described in the first embodiment, a field oxide film 12, a gate insulating film 15 and the like are formed on the surface side of a silicon substrate 11, as shown in FIG. ing. Although not shown, a P-type well region, an N-type well region and the like are formed on the silicon substrate 11. Next, as a first step, a polycrystalline silicon film 17 to be a silicon film 16 and an amorphous silicon film 18 are formed on the field oxide film 12 and the gate insulating film 15 by, for example, a CVD method.

Subsequently, as shown in FIG. 6B, as a second step, an N-type impurity is introduced into the region 19 where the N-type pattern is to be formed of the amorphous silicon film 18 by, for example, an ion implantation method. . Further, a P-type impurity is introduced into the region 20 for forming the P-type pattern of the amorphous silicon film 18 by, for example, an ion implantation method. As a matter of course,
In each of the above ion implantation methods, a resist pattern (not shown) is formed as a mask. Therefore, the resist pattern used as a mask after each ion implantation is removed each time.

Next, annealing is performed as a third step. First, for example, the amorphous silicon film 18 is crystallized by furnace annealing at 650 ° C. for 10 hours, so that the polycrystalline silicon film has a larger crystal grain size than the polycrystalline silicon film 17 formed by the CVD method. Generate Hereinafter, the polycrystalline silicon film formed here and the polycrystalline silicon film 17 are referred to as a polycrystalline silicon film 21. Subsequently, for example, RTA at 1000 ° C. for 10 seconds is performed to diffuse and activate the impurities distributed on the surface of the polycrystalline silicon film 21 into the polycrystalline silicon film 21.

Next, as shown in FIG. 6C, a silicon oxide film is formed on the polycrystalline silicon film 21 by, for example, CV.
Formed by Method D. Then, the silicon oxide film is patterned by a normal lithography technique and an anisotropic etching technique to form an insulating film pattern 23 serving as an etching mask when forming an N-type pattern and a P-type pattern. Subsequently, the resist mask is removed by ashing and cleaning. FIG. 6C shows a state in which the resist mask has been removed.

Thereafter, a heat treatment (hereinafter referred to as "annealing") for making the impurities at the lattice points of the polycrystalline silicon film 21 into a supersaturated state is performed. This annealing is performed at a predetermined temperature in the range of 700 ° C. to 900 ° C., preferably 800 ° C.
This is performed at a predetermined temperature in a range of not less than 850 ° C. In the above annealing, as an example, the annealing was performed under the conditions of an annealing atmosphere: a nitrogen (N ₂ ) atmosphere, an annealing temperature: 800 ° C., and an annealing time: 10 minutes. Needless to say, the annealing atmosphere and the annealing time are not limited to the above-mentioned times, and the annealing atmosphere may be an inert atmosphere, and the annealing time is set so that the impurities at the lattice points of the polycrystalline silicon film 21 are supersaturated. It is sufficient if it is a sufficient time to make it. As a result of this annealing, the conductivity of the polycrystalline silicon film 21 decreases. Or
The annealing at 800 ° C. for 10 minutes may be performed without forming the insulating film pattern 23 made of the silicon oxide film.

Next, as described in the first embodiment,
Then, as shown in FIG. 6D, as a fourth step,
The difference using the insulating film pattern 23 as an etching mask
Anisotropic etching (using chlorine and oxygen as etching gas
), The polycrystalline silicon film 21 is etched.
Thus, an N-type pattern 41 and a P-type pattern 42 are formed.
You. At this time, the polycrystalline silicon
Since the conductivity of the oxidation film 21 decreases, the chlorine
In the anisotropic etching, the N ⁺Type
The etching rate of the region 21N is lower than before the annealing.
Lower, P⁺The etching rate of the mold region 21P is
Increase from before. Therefore, the polycrystalline silicon film 21
N⁺Rate and P in mold region 21N⁺Type
The difference from the etching rate in the region 21P is small.
You.

In the manufacturing method according to the third embodiment, the conductivity of the polycrystalline silicon film 21 can be reduced as in the first embodiment. Therefore, when the polycrystalline silicon film 21 is patterned by etching, the N ⁺ -type region 21N and the P ⁺ -type region 21
The difference in etching rate between P and P becomes smaller. Therefore, even if over-etching is performed to prevent polycrystalline silicon residue from being generated in the P ⁺ -type region 21P, the silicon substrate 11 underlying the N ⁺ -type region 21N will not be dug, and the underlying substrate of the N ⁺ -type region 21N will not be dug. Silicon substrate 11
Before digging, the polycrystalline silicon residue in the P ⁺ type region 21P is etched.

In the embodiment according to the second invention, the same annealing (heating at 600 ° C. to 800 ° C. at a rate of 5 ° C./min or less as in the second embodiment according to the first invention, Even if annealing is performed at 800 ° C. for 10 minutes, the conductivity of the polycrystalline silicon film 21 can be reduced.

[0067]

As described above, according to the present invention,
700 before etching to pattern the silicon film
A predetermined temperature in the range of ℃ to 900 ℃, preferably 800 ℃
Since the heat treatment is performed at a predetermined temperature in the range of 850 ° C. to 850 ° C., the resistivity of the silicon film increases, and as a result, the etching rate of the N-type region of the silicon film decreases,
The etching rate of the mold region increases. Therefore, the difference between the etching rates of the two becomes small, and when the N-type region of the silicon film and the P-type region of the silicon film are simultaneously etched, the N-type of the silicon film having a high etching rate becomes high.
Excessive etching of the silicon substrate exposed when the mold region is etched can be prevented, and when a P-type region of a silicon film having a low etching rate is etched, residue of the silicon film can be eliminated at a step portion. .

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a first embodiment according to the first invention.

FIG. 2 is a manufacturing step diagram (continued) of the first embodiment according to the first invention.

FIG. 3 is a relationship diagram between sheet resistance and annealing temperature.

FIG. 4 is a relationship diagram between sheet resistance and annealing temperature.

FIG. 5 is a manufacturing process diagram of the second embodiment according to the first invention.

FIG. 6 is a manufacturing process diagram of the first embodiment according to the second invention.

FIG. 7 is an explanatory diagram of a problem.

FIG. 8 is a diagram illustrating a relationship between an etching rate and a sheet resistance.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Silicon substrate 16 Silicon film 19 N-type pattern formation area 20 P-type pattern formation area 22 Metal-based conductive film 24 N-type pattern 25
P-type pattern

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8238 H01L 27/092

Claims (4)

(57) [Claims] A first step of forming a silicon film on a substrate; introducing an n-type impurity into a region of the silicon film where an n-type pattern is to be formed; A second step of introducing a P-type impurity, and annealing, the N-type impurity is diffused into the silicon film in the region where the N-type pattern is to be formed, and the P-type impurity is diffused in the region where the P-type pattern is to be formed. A third step of diffusing into the silicon film, a fourth step of forming a metal-based conductive film on the silicon film, and patterning the silicon film together with the metal-based conductive film by etching to form an N-type pattern and a P-type conductive film. A fifth step of simultaneously forming a mold pattern, the method comprising the steps of: forming a silicon pattern after the third step and before the fifth step; The method of manufacturing a semiconductor device which is characterized in that the heat treatment for the impurity of the grid points of the film supersaturated. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed in an atmosphere at a temperature of 700 ° C. or more and 900 ° C. or less. A first step of forming a silicon film on the substrate; introducing an n-type impurity into a region of the silicon film where an n-type pattern is to be formed; A second step of introducing a P-type impurity, and annealing, the N-type impurity is diffused into the silicon film in the region where the N-type pattern is to be formed, and the P-type impurity is diffused in the region where the P-type pattern is to be formed. A method of manufacturing a semiconductor device, comprising: a third step of diffusing into a silicon film; and a fourth step of patterning the silicon film by etching to simultaneously form an N-type pattern and a P-type pattern. After the step and before the fourth step, a heat treatment for supersaturating impurities at lattice points of the silicon film is performed. The method of production. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the heat treatment is performed in an atmosphere at a temperature of 700 ° C. or more and 900 ° C. or less.