JPH09260668A - Thin film transistor and method of manufacturing the same - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: To be used for a liquid crystal display device and to have a low wiring resistance
Provided are a thin film transistor having a high aperture ratio and high performance, and a manufacturing method thereof. A source line and a light shielding film are formed by metal 4 deposited on the surface of an insulating substrate having a groove formed on the surface, and a source insulating film is formed on a transparent insulating film on the source line. The semiconductor layer 7 formed on the source line 24 and the transparent insulating film 5 through the contact hole 6
And are connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used as a switching element for selecting pixels in a liquid crystal display device and a method for manufacturing the thin film transistor.

[0002]

2. Description of the Related Art In recent years, in an active matrix type liquid crystal display device in which thin film transistors are formed in a matrix on a transparent insulating substrate such as glass and the thin film transistors are used as switching elements, the display screen has been enlarged and the resolution has been improved. Is becoming more popular. In the active matrix type liquid crystal display device, in order to improve the aperture ratio,
There is a tendency to make the wiring of the thin film transistor thinner,
The thinner the wiring, the higher the resistance of the wiring and the more likely the disconnection failure occurs. Therefore, in order to increase the size and definition of the display screen in the active matrix liquid crystal display device, lowering the resistance of the wiring of the thin film transistor and improving the reliability of the element of the thin film transistor are more important than ever before.

In the above-mentioned active matrix type liquid crystal display device, for the purpose of suppressing an increase in light leak current due to light sneak from the back surface of the transparent insulating substrate,
There has been proposed a thin film transistor having a structure in which a light shielding film is provided below the thin film transistor so as to block light from entering the thin film transistor. As an example of such a thin film transistor, a poly Si transistor having a light shielding film is schematically shown in FIG.

A method of manufacturing the thin film transistor shown in FIG. 6 will be described below.

First, a Ta film is formed on a transparent insulating substrate 101 such as glass, and the Ta film is etched to form a light shielding film 118. Next, a base insulating film (base coat) 105 is deposited. Base insulating film 105
After the island-shaped semiconductor layer 107 is formed on the top of the semiconductor layer 107, the semiconductor layer 107 is crystallized by laser irradiation or high-temperature heat treatment at a temperature of about 600 ° C. Next, the gate electrode 1
A resist mask that is slightly larger than 13 is used as the semiconductor layer 10
7 is formed on the semiconductor layer 107, P ions or B ions are implanted into the semiconductor layer 107, and the impurities are activated by laser annealing to form the source region 109, the drain region 110, and the offset region 111. Further, SiO ₂ is deposited on the upper part of these regions to form the gate insulating film 11
Form 2 Next, the gate electrode 113 is formed by depositing an alloy containing Al as a main component, Ta, or the like on the gate insulating film 112. Further, SiO ₂ is deposited to form an interlayer insulating film 119. Next, ITO is deposited and patterned on the interlayer insulating film 119 to form the pixel electrode 114.
Source region 109 and drain region 1 after forming
Contact holes 106 and 116 are formed on the respective layers 10. Then, a metal such as an Al alloy is sputtered to form the source line 120 and the drain electrode 121.

As a transistor for the purpose of lowering the resistance of the wiring and suppressing the disconnection failure, Japanese Patent Publication No. 7-5438 shown in FIG.
There is a thin film transistor disclosed in Japanese Patent No. 6 (Mitsubishi Electric). In the thin film transistor of Japanese Patent Publication No. 7-54386, the second source line 209 is formed on the transparent insulating substrate 201 at the same time as the light shielding film 202. The second source line 209 is connected to the first source line electrode 204 through the contact hole 210. The second source line 209 is parallel to the first source line 204, and the first source line 204 and the second source line 209 form a two-layer source line. 203
Is a passivation film, 205 is a drain / pixel electrode,
206 is a semiconductor film, 207 is a gate insulating film, 208 is a gate electrode, and 211 is a contact film.

Further, as disclosed in JP-A-6-16586 (Fujitsu) and JP-A-6-224221 (Nippon Sheet Glass), a metal is deposited in a groove (recess) provided in a substrate. There is also a thin film transistor having a gate wiring formed by the above.

[0008]

As shown in FIG. 6, in the conventional structure in which the light shielding film 118 is formed under the thin film transistor, the light shielding film 118 is in an electrically floating state, so that stray capacitance is generated. Therefore, the reliability of the thin film transistor is low. Therefore, in order to improve the reliability, it is necessary to devise a special wiring for fixing the potential of the light shielding film 118, or to connect the light shielding film 118 to any one of the source electrode and the gate electrode. is there. In addition, the manufacturing process is complicated because a process for forming the source line and the drain electrode is required at a level above the gate line. Further, in the stepped portion of the gate, the source line is broken, or the source line is thinned even if the broken line does not occur, so that there is a problem that the reliability of the wiring is low. There is also a problem that a leak current is likely to occur between the source line, the drain electrode, and the gate line. When the Al alloy and ITO are in contact with each other as in the structure shown in FIG. 6, corrosion due to the battery effect occurs at the contact portion, and the characteristics deteriorate.

In the thin film transistor disclosed in Japanese Patent Publication No. 7-54386, as described above, the second source line 209 formed simultaneously with the light shielding film 202 on the transparent insulating substrate 201 has the first source line 209. The line electrode 204 and the contact hole 210 are connected in parallel to form a two-layer source line, but the light-shielding film 202 is in an electrically floating state. Since the light shielding film 202 is in an electrically floating state, there is the above-mentioned problem. Second source line 2
If the material of 09 is an Al alloy, the second source line cannot withstand the laser processing and the high temperature heat treatment in the subsequent process. On the other hand, if the material of the second source line 209 is a practical refractory metal, the second source line 209 has a higher resistivity than the Al alloy, so that the second source line 209 has a practical resistance value. It is necessary to increase the thickness of the film and increase the line width of the wiring. However, the second source line 20
If the film thickness of 9 is increased, the step portion (first source line 2
04 and the second source line 209 overlap each other, leading to disconnection of the upper layer film (first source line 204) and deterioration of reliability. Further, if the line width of the second source line 209 is increased, problems such as a decrease in aperture ratio occur.

In the manufacturing method disclosed in Japanese Patent Laid-Open No. 6-163586, a metal is formed on the resist and the contact portion by a plating method,
Since the metal other than the contact portion is lifted off together with the resist to form the gate electrode, impurities such as C are mixed in the gate electrode, and a highly reliable electrode cannot be formed. Further, it is impossible to endure the post-process heat treatment at 500 ° C. to 600 ° C. or higher.

In each of the publications, a buried metal is used as a gate electrode, but it is difficult to obtain a good characteristic in a bottom gate type transistor because it is difficult to completely flatten the surface.

An object of the present invention is to provide a thin film transistor having good characteristics and high reliability, and a method for manufacturing the same.

[0013]

A thin film transistor formed on an insulating substrate according to the present invention is deposited on a grooved surface of an insulating substrate including a groove formed on the surface of the insulating substrate. A source line and a light shielding film are formed from a conductor, and the source line and the semiconductor layer formed on the transparent insulating film are connected through a contact hole formed in the transparent insulating film on the source line. Therefore, the above object is achieved.

The conductor may be a metal.

It is preferable that the potential of the source line and the potential of the light shielding film are the same.

A method of manufacturing a thin film transistor formed on an insulating substrate according to the present invention comprises a step of forming a groove on the surface of the insulating substrate, a step of forming metal in the groove and forming the groove of the insulating substrate. Forming a metal layer by depositing the metal on the surface, forming a source line and a light-shielding film by processing the metal layer, and forming a transparent insulating film on the source line and the light-shielding film. The method includes a step, a step of forming a contact hole in the transparent insulating film, and a step of forming a semiconductor layer connected to the source line through the contact hole on the transparent insulating film. The above object is achieved.

The step of processing the metal layer to form the source line and the light shielding film may include a step of etching back the metal layer.

As a result, the metal can be embedded in the groove without voids and a thin light-shielding film can be formed.

In the thin film transistor formed on the insulating substrate according to the present invention, the source line is formed of the metal embedded in the groove provided on the surface of the insulating substrate,
Thereby, the above object is achieved.

In the thin film transistor, an insulating film provided on the surface of the insulating substrate on which the groove is provided, a contact hole provided in the insulating film, and the source line through the contact hole. A semiconductor layer connected to the insulating film and provided on the insulating film, and a gate electrode provided on the semiconductor layer.

A method of manufacturing a thin film transistor formed on an insulating substrate according to the present invention comprises a step of forming a groove on the surface of the insulating substrate, a step of burying a metal in the groove to form a source line, and the source. Forming an insulating film on a line and the insulating substrate; forming a contact hole in the insulating film; and forming a semiconductor layer connected to the source line through the contact hole on the insulating film. And a process for achieving the above object.

In the manufacturing method, a step of burying a metal in the groove to form a source line includes burying the metal in the groove and depositing the metal on a surface of the insulating substrate on which the groove is formed. The method may include a step of depositing to form a metal layer and a step of removing the metal layer on the insulating substrate other than the metal in the groove.

According to the present invention, by forming a groove in the insulating substrate, the space in the depth direction of the substrate is utilized,
A source line with low resistance and high reliability can be formed. Further, since the step is eliminated at the intersection of the source line and the gate line, the thin film transistor can be flattened and the characteristics of the thin film transistor are improved. Furthermore, since the line width of the source line can be reduced, the aperture ratio is improved. If the source line and the light-shielding film are formed at the same time, the potential of the source line and the light-shielding film are always at the same potential, so that no special wiring for fixing the potential of the light-shielding film is needed and stray capacitance is not generated. It can be prevented.

[0024]

First, an outline of a method of manufacturing a thin film transistor according to the present invention will be described. Details of the thin film transistor according to the present invention and the method for manufacturing the same will be described in Examples below.

In the method of manufacturing a thin film transistor according to the present invention, a groove is formed by a dry etching method in a region where a source line of a transparent insulating substrate is formed, and an adhesion layer is provided on the groove and the transparent insulating substrate. Adhesion layer is Ti, TiN, Ti
W, W, WSi _x, etc. are formed by a sputtering method.

After that, a source line is formed in the groove by completely filling the groove with a refractory metal by a chemical vapor deposition method (CVD method) or the like, and this is formed on the entire surface of the adhesion layer on the transparent insulating substrate. A refractory metal is deposited to form a refractory metal film.

As a method for burying a refractory metal in a groove provided in a region for forming a source line on a transparent insulating substrate, there is a W full surface CVD method or the like. The full-face CVD method is a common method in the field of LSI as a method for filling a high aspect ratio contact hole or a through hole.

After that, etching back is performed until the refractory metal film on the insulating substrate has a desired film thickness. When the film thickness of the refractory metal film is small, a void is generated at the center of the groove during the etch back. In order to completely fill the trench with the refractory metal without using the CVD method, it is necessary to deposit the refractory metal film at least at least half the width of the trench. Therefore,
From the viewpoint of productivity (cost, throughput, etc.), it is preferable that the width of the groove is narrow. The width of the groove is preferably about 1 μm or less. When it is necessary to widen the width of the source line in order to reduce the resistance of the source line, a plurality of grooves may be formed or the grooves may be formed deep. The specific resistance of the W-CVD film is about 10 to 12 μΩcm, and it is possible to form a low resistance source line. After the entire surface is etched back by the dry etching method, the refractory metal film is processed into a desired source line and light shielding film shape, and a transparent insulating film is deposited thereon.

After forming a contact hole in the transparent insulating film, a semiconductor layer is formed and the semiconductor layer and the source line are connected.

Next, after depositing a gate insulating film, a gate electrode is formed, and further, so as to be connected to the drain region,
A pixel electrode is formed by depositing and patterning a transparent conductive film on the drain region.

The method of manufacturing a thin film transistor according to the present invention includes the steps described above.

The above manufacturing method is a manufacturing method of a thin film transistor having a light shielding film. On the other hand, a thin film transistor having no light-shielding film is manufactured as follows.

First, a groove is formed on a transparent insulating substrate by a dry etching method, an adhesion layer is formed in the groove and on the transparent insulating substrate, and then a refractory metal is deposited on the entire surface by a CVD method to completely form the groove. Form a buried source line. The steps up to this point are the same as in the manufacturing method described above.

Next, etching back is performed until the refractory metal on the transparent insulating substrate other than the groove is completely removed.

Then, similarly to the above-mentioned manufacturing method, after depositing the transparent insulating film, forming a contact hole on the source line, forming a Si layer, and directly connecting the Si layer and the source line.

Hereinafter, a gate electrode is formed after depositing a gate insulating film, a transparent conductive film is deposited on the drain region so that the pixel electrode is connected to the drain region, and patterning is performed to form a pixel electrode having a desired shape. To form.

The method of manufacturing a thin film transistor having no light-shielding film according to the present invention includes the above steps.

The method of forming the refractory metal film is not limited to the above-mentioned method, but may be a reflow sputtering method, for example. A chemical mechanical polishing (CMP) method may be used as another method for removing the refractory metal on the insulating substrate other than the groove.

When Cu is used as the refractory metal,
The MOCVD method can also be used for the reflow sputtering method to fill the groove and form a film on the substrate. When Cu is used, the refractory metal film on the insulating substrate other than the groove may be removed and planarized by the CMP method. Cu is A
Since the specific resistance is lower than that of the 1-alloy, the wiring can be further reduced in resistance and miniaturized as compared with the case of using Al. Less than,
An embodiment of the present invention will be described.

(First Embodiment) FIG. 1 is a plan view showing a thin film transistor 30 having a light shielding film according to the present invention. Hereinafter, FIG. 2 corresponding to a cross-sectional view taken along the line AA of FIG.
A manufacturing process of the thin film transistor 30 according to the present invention will be described with reference to (a) to (k).

First, a groove 2 having a width of 1 μm and a depth of 2 μm is formed by a dry etching method in a region where a source line is to be formed on a glass substrate 1 as a transparent insulating substrate. Then, on the glass substrate 1 and in the groove 2, a TiW layer 3 having a thickness of 50 nm is deposited by a sputtering method as an adhesion layer of the glass substrate, and further 550 nm W is deposited on the TiW layer 3 by a full-scale CVD method. Then, the W layer 4 is formed (FIG. 2A).

Then, etching back is performed until the total film thickness of the TiW layer 3 and the W layer 4 on the glass substrate 1 reaches 100 nm (FIG. 2B). The reason for performing etch back is to thin the W layer 4. By thinning the W layer 4, a light shielding film 23 described later is formed thin. As a result, a semiconductor layer having less steps described later is formed, and as a result, a flat thin film transistor can be obtained.

The film formation and etch back of the W layer 4 can be continuously performed by a multi-chamber system apparatus, and can be performed by a known method.

Next, the TiW layer 3 and the W layer 4 are patterned into a desired shape by the photolithography method and the dry etching method to form the source line 24 and the light shielding film 23 (FIG. 2C).

After SiO ₂ is deposited to 100 nm on the glass substrate 1 and the source line 24 to form the interlayer insulating film 5, the contact hole 6 is formed on the source line 24 of the interlayer insulating film 5 (FIG. 2 (d). )).

Amorphous silicon is set to 50 nm.
The semiconductor layer 7 is formed by depositing and processing it into an island shape (see FIG. 2).
(E)). At this time, the source line 24 and the semiconductor layer 7 are electrically connected through the contact hole 6.

Next, laser irradiation is performed to polycrystallize the semiconductor layer 7. In order to provide an offset region at the channel end, a resist mask 8 which is slightly larger than a gate electrode described later is used as a mask to form it on the semiconductor layer 7, and PH ₃ + H ₂ gas plasma is used to accelerate at an acceleration voltage of 80 k.
Impurity ions (P ions) having a dose amount of 5 × 10 ¹⁵ / cm ² are implanted at eV (FIG. 2F).

After removing the resist 8, the impurities injected into the semiconductor layer 7 are activated by a laser having an irradiation energy of 350 mJ / cm ^{2 in} a room temperature atmosphere using a Xe-Cl excimer laser to activate the source region 9 and The drain region 10 is formed. An ohmic contact is formed at the contact portion between the source line 24 and the source region 9 of the semiconductor layer. P ions are not implanted into the region of the semiconductor layer 7 located under the resist mask 8 (see FIG. 2).
(G)).

Next, after depositing 100 nm of SiO ₂ to form the gate insulating film 12, Ta is formed on the gate insulating film 12.
Layer 15 is deposited to 350 nm (FIG. 2 (h)). After this,
The Ta layer 15 is patterned using the resist mask 18 to form the gate electrode 13 (FIG. 2 (i)). Between the source region 9 and the channel region and the drain region 10
An offset region 11 is formed between and the channel region.

The gate insulating film 12 is etched by using the gate electrode 13 as a mask (FIG. 2 (j)), and the transparent conductive film I is formed so as to overlap the exposed drain region 10.
TO is deposited to a thickness of 100 nm to form the pixel electrode 14 (FIG. 2 (k)).

Although Ta is used as the material of the gate electrode 13 in this embodiment, Al alloy, refractory metal, refractory metal silicide, or polycrystalline silicon may be used as the material for the gate electrode. Further, the gate electrode 13 may be formed in a laminated structure of silicide and polycrystalline silicon.

(Second Embodiment) FIG. 3 is a plan view showing a thin film transistor 50 without a light shielding film according to the present invention.
Hereinafter, FIG. 4A to FIG. 4A corresponding to the cross-sectional view taken along the line BB of FIG.
The manufacturing process of the thin film transistor 50 will be described with reference to (i).

First, a groove 32 having a width of 1 μm and a depth of 2 μm is formed by a dry etching method in a region where a source line is to be formed on a glass substrate 31 as a transparent insulating substrate. Next, a TiW layer 33 having a thickness of 50 nm is deposited as an adhesion layer on the glass substrate 31 and in the groove 32 by a sputtering method, and further 550 nm of W is deposited on the TiW layer 33 by a full-scale CVD method. The layer 39 is formed (FIG. 4A).

Subsequently, the TiW layers 33 and W on the glass substrate 1 other than the TiW layer 33 and the W layer 39 in the groove 32 are formed.
The layer 39 is etched back and completely removed (FIG. 4).
(B)). The W layer 4 may be deposited and etched back by a known method. A source line 34 is formed in the groove 32.

Next, after depositing 100 nm of SiO ₂ to form an interlayer insulating film 35, a contact hole 36 is formed above the source line 34 of the interlayer insulating film 35 (FIG. 4).
(C)).

Amorphous silicon is set to 50 nm.
The semiconductor layer 37 is formed by depositing and processing the semiconductor layer 37 (FIG. 4D). At this time, the source line 34 and the semiconductor layer 37 are electrically connected through the contact hole 36.

Next, laser irradiation is performed to polycrystallize the semiconductor layer 37. In order to provide an offset region at the channel end, a resist mask 38, which is slightly larger than a gate electrode, which will be described later, is formed on the semiconductor layer 37 as a mask, and PH ₃ + H ₂ gas plasma is used at an acceleration voltage of 80 keV and a dose of P ions of 5 × 10 ¹⁵ / cm ² are implanted (FIG. 4E).

After removing the resist 38, the impurities implanted into the semiconductor layer 37 are activated by a laser having an irradiation energy of 350 mJ / cm ^{2 in} a room temperature atmosphere using a Xe-Cl excimer laser to activate the source region 39 and The drain region 40 is formed. An ohmic contact is formed at the contact portion between the source line 34 and the drain region 39 of the semiconductor layer. P ions are not implanted into the region of the semiconductor layer 37 located under the resist mask 38 (FIG. 4F).

Next, SiO ₂ is deposited to 100 nm to form the gate insulating film 42, and Ta is deposited to 350 nm. Then, using the resist mask 45, the deposited Ta layer is patterned to form the gate electrode 43 (FIG. 4).
(G)). Offset regions 41 are formed between the source region 39 and the channel region and between the drain region 40 and the channel region.

The gate insulating film 42 is etched by using the gate electrode 43 as a mask (FIG. 4 (h)), and the transparent conductive film I is formed so as to overlap with a part of the exposed drain region 40.
TO is deposited to a thickness of 100 nm to form the pixel electrode 44 (FIG. 4 (i)).

Although Ta is used as the material of the gate electrode 43 in this embodiment, Al alloy, refractory metal, refractory metal silicide, or polycrystalline silicon may be used as the gate electrode material. Further, the gate electrode 43 may be formed in a laminated structure of silicide and polycrystalline silicon.

(Third Embodiment) A third embodiment of the method of manufacturing a thin film transistor according to the present invention will be described with reference to FIGS.

First, a groove 52 having a width of 1 μm and a depth of 1 μm is formed by a dry etching method in a region where a source line is to be formed on a glass substrate 51 as a transparent insulating substrate. Next, TiN is deposited as a barrier metal by a sputtering method to form a TiN layer 65 having a thickness of 100 nm.
Cu was deposited on the entire surface of the TiN layer 65 by the OCVD method to 550
m is deposited to form a Cu layer 66 (FIG. 5A). Note that the reflow sputtering method may be used instead of the CVD method.

Then, the TiN layer 65 and the Cu layer 66 on the glass substrate 51 other than the TiN layer 65 and the Cu layer 66 in the groove 52 are completely removed by the CMP method (FIG. 5B).

Next, SiN is deposited to a thickness of 200 nm to form an interlayer insulating film 67. The interlayer insulating film 67 becomes a barrier layer. Then, the contact hole 56 is formed above the source line 74 of the interlayer insulating film 67 (FIG. 5C).

Amorphous silicon is set to 50 nm.
The semiconductor layer 57 is formed by depositing and processing into an island shape (FIG. 5).
(D)). At this time, the source line 74 and the semiconductor layer 57 are electrically connected through the contact hole 56.

Next, laser irradiation is performed to polycrystallize the semiconductor layer 57. In order to provide an offset region at the channel end, a resist mask 58, which is slightly larger than a gate electrode, which will be described later, is formed on the semiconductor layer 57 as a mask, and PH ₃ + H ₂ gas plasma is used at an acceleration voltage of 80 keV and a dosage of P ions of 5 × 10 ¹⁵ / cm ² are implanted (FIG. 5E).

After the resist 58 is peeled off, the impurities injected into the semiconductor layer 57 are activated by a laser having an irradiation energy of 350 mJ / cm ^{2 in} a room temperature atmosphere using a Xe-Cl excimer laser to activate the source region 59 and the source region 59. The drain region 60 is formed. An ohmic contact is formed at the contact portion between the source line 74 and the source region 59 of the semiconductor layer. P ions are not implanted into the region of the semiconductor layer 57 located below the resist mask 58 (FIG. 5F).

Next, SiO ₂ is deposited to 100 nm to form a gate insulating film 62, Ta is deposited to 350 nm, and then,
The deposited Ta layer is patterned using the resist mask 68 to form the gate electrode 63 (FIG. 5).
(G)).

The gate insulating film 62 is etched by using the gate electrode 63 as a mask (FIG. 5H), and is a transparent conductive film I so as to overlap with a part of the exposed drain region 60.
TO is deposited to a thickness of 100 nm to form the pixel electrode 64 (FIG. 5 (i)).

[0071]

As described above, according to the present invention, the source line is formed in the groove provided in the insulating substrate, and there is no level difference at the intersection of the source line and the gate line. A thin film transistor can be easily formed. Therefore, it is possible to easily obtain a thin film transistor having low resistance and high reliability.

Since the thin film transistor according to the present invention has a low resistance and a highly reliable source line in which a short circuit failure is unlikely to occur, even when the thin film transistor according to the present invention is applied to a large-capacity, large-screen display, the wiring Since the propagation delay is reduced, there is no deterioration in image quality. In addition, since the line width of the source line can be reduced without increasing the resistance of the source line, the aperture ratio is improved in the display device using the thin film transistor according to the present invention.

According to the present invention, the source line and the light shielding film are integrally formed at the same time, so that the manufacturing process can be simplified and the light shielding film and the source line are always at the same potential. Therefore, a special wiring for fixing the potential of the light-shielding film is not required, and a thin film transistor with good characteristics in which stray capacitance is less likely to occur can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a thin film transistor having a light shielding film according to the present invention.

2A to 2K are views for explaining an embodiment of a method of manufacturing a thin film transistor according to the present invention.

FIG. 3 is a plan view showing an embodiment of a thin film transistor having no light shielding film according to the present invention.

4 (a) to (i) are views for explaining another embodiment of the method of manufacturing a thin film transistor according to the present invention.

5A to 5I are views for explaining another embodiment of the method of manufacturing a thin film transistor according to the present invention.

FIG. 6 is a diagram showing a conventional thin film transistor.

FIG. 7 is a diagram illustrating a thin film transistor disclosed in Japanese Patent Publication No. 7-54386.

[Explanation of symbols]

 1 glass substrate 2 groove 3 TiW layer 4 W layer 5 interlayer insulating film 6 contact hole 7 semiconductor layer 8 resist mask 9 source region 10 drain region 13 gate electrode 14 pixel electrode 23 light-shielding film 24 source line

Claims (9)

[Claims] 1. A thin film transistor formed on an insulating substrate, wherein a source line is formed from a conductor deposited on the grooved surface of an insulating substrate including a groove formed on the surface of the insulating substrate. A thin film transistor in which a light shielding film is formed, and the source line and the semiconductor layer formed on the transparent insulating film are connected via a contact hole formed in the transparent insulating film on the source line. 2. The thin film transistor according to claim 1, wherein the conductor is a metal. 3. The thin film transistor according to claim 1, wherein the potential of the source line and the potential of the light shielding film are the same. 4. A method of manufacturing a thin film transistor formed on an insulating substrate, comprising the steps of forming a groove on the surface of the insulating substrate, embedding a metal in the groove and forming the groove of the insulating substrate. A step of depositing the metal on the surface on which the metal is formed to form a metal layer, a step of processing the metal layer to form a source line and a light shielding film, and a transparent insulating film on the source line and the light shielding film. And a step of forming a contact hole in the transparent insulating film, and a step of forming a semiconductor layer connected to the source line through the contact hole on the transparent insulating film. Production method. 5. The method of manufacturing a thin film transistor according to claim 4, wherein the step of processing the metal layer to form the source line and the light shielding film includes the step of etching back the metal layer. 6. A thin film transistor formed on an insulating substrate, wherein a source line is formed of a metal embedded in a groove provided on the surface of the insulating substrate. 7. An insulating film provided on the surface of the surface of the insulating substrate on which the groove is provided, a contact hole provided above the source line of the insulating film, and the contact hole 7. The thin film transistor according to claim 6, further comprising a semiconductor layer connected to the source line and provided on the insulating film, and a gate electrode provided on the semiconductor layer. 8. A method of manufacturing a thin film transistor formed on an insulating substrate, comprising: forming a groove on the surface of the insulating substrate; and forming a source line by embedding a metal in the groove. A step of forming an insulating film on the source line and the insulating substrate; a step of forming a contact hole in the insulating film; and a semiconductor layer connected to the source line through the contact hole on the insulating film. And a step of forming the thin film transistor. 9. The step of burying a metal in the groove to form a source line includes burying the metal in the groove and depositing the metal on a surface of the insulating substrate on which the groove is formed. The method of manufacturing a thin film transistor according to claim 8, further comprising: a step of forming a metal layer; and a step of removing the metal layer on the insulating substrate other than the metal in the groove.