JPH09260629A - Manufacture of amplified solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive the simplification of a wiring structure in a pixel region and an increase in the uniformity of the pixel characteristics of an amplified solid-state image pickup element. SOLUTION: Before the gate electrodes are formed, source and drain regions 39 and 40 and impurity regions 41 and 42, which are respectively positioned under the regions 39 and 40, are formed in a self-alignment manner by an ion implantation, using the same mask and after that, the gate electrodes and a wiring layer 45, which links the fellow gate electrodes to each other, are formed by patterning the same conductive layer. Other wiring is connected to this wiring layer 45, located outside of a channel region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an amplification type solid state image pickup device.

[0002]

2. Description of the Related Art In recent years, in response to a demand for higher resolution of a solid-state imaging device, an amplification type solid-state imaging device which has no smear and can realize fine pixels has been developed in place of a CCD solid-state imaging device. This amplification type solid-state imaging device includes a MOS type transistor for amplifying an optical signal for each pixel,
A signal is read out by using the electric charge accumulated in the pixel by photoelectric conversion as the current modulation of the transistor.

[0003]

8 and 9 show a comparative example of the previously proposed amplification type solid-state image pickup device. As shown in FIG. 9, this amplification type solid-state imaging device 1 has a second conductivity type, that is, n, on a silicon semiconductor substrate 2 of a first conductivity type, for example, p type.
Type semiconductor region, that is, an overflow barrier region 3 and a p-type semiconductor well region 4 are formed, and an annular gate capable of transmitting light through a gate insulating film 5 made of SiO ₂ or the like on the p-type semiconductor well region 4. An electrode 6 is formed, an n-type source region 7 and a drain region 8 are formed in a region corresponding to the center hole and the outer periphery of the ring-shaped gate electrode 6, and a p-type semiconductor well under the regions 7 and 8 is formed. Area 4
Impurity regions 9 and 10 of the same conductivity type as the source and drain regions, that is, n-type impurity regions are formed therein, and a p-type charge having a higher impurity concentration than the p-type semiconductor well region 4 is formed in a region corresponding to a channel under the gate electrode 6. An accumulation well region, a so-called sensor well region 12, is formed, and an MO that constitutes one pixel is formed therein.
An S-type transistor (hereinafter referred to as a pixel MOS transistor) 13 is formed. The ring-shaped gate electrode 6 is made of a thin material or a transparent material so as to absorb light as little as possible. In this example, thin-film polycrystalline silicon is used.

This pixel MOS transistor 13 is shown in FIG.
As shown in FIG. 2, a plurality of pixels, for example, V-shaped pixels formed of the first wiring material so as to straddle the annular gate electrodes 6 of two pixel MOS transistors 13 that are arranged in a matrix and are adjacent to each other in the horizontal direction. The inter-wiring layer 15 is connected. Then, the vertical selection line 17 made of the second wiring material connected to the inter-pixel wiring layer 15 is arranged along the horizontal direction at a position corresponding to each row of the pixel MOS transistors 13.

Further, a common signal line 16 made of a third wiring material formed along the vertical direction is connected to the source region 7 of the pixel MOS transistor 13 corresponding to each column. Further, a drain power supply line 18 made of a third wiring material connected to the drain region 8 is formed between the pixel MOS transistors 13 not extending over the inter-pixel wiring layer 15 so as to be parallel to the signal line 16.

Reference numeral 20 is a contact portion between the inter-pixel wiring layer 15 and the gate electrode 6, 21 is a contact portion between the inter-pixel wiring layer 15 and the vertical selection line 17, and 22 is a source region 7 and the signal line 1.
Reference numeral 6 is a source contact portion, and 23 is a drain contact portion between the drain region 8 and the drain power supply line 18.
Reference numeral 24 represents a pixel region in which the pixel MOS transistor 13 is formed.

In this pixel MOS transistor 13, the light transmitted through the ring-shaped gate electrode 6 is photoelectrically converted in silicon to generate electrons-holes, and one of these charges, in this example, holes is a signal charge. Is accumulated in the sensor well region 12 below the annular gate electrode 6. When a high voltage is applied to the ring-shaped gate electrode 6 through the vertical selection line 17 and the pixel MOS transistor 13 is turned on, a drain current (so-called channel current) flows in the surface channel, and this drain current changes due to signal charges. Since this is received, this drain current is output through the signal line 16, and the amount of change is used as a signal output.

The sensor well region 12 in which the signal charges (holes) are accumulated has a shallow source region 7 and a shallow drain region 8.
Is deeply surrounded by the deep impurity regions 9 and 10 and the overflow barrier region 3 which is deeper.
Excess accumulated charges when receiving a large amount of light are discharged to the substrate 2 side through the overflow barrier region 3. Overflow barrier region 3 is several μm in order to obtain red sensitivity
It is usually formed at a deep position of.

Therefore, the deep impurity regions 9 and 10 are
The shallow source region 7 and drain region 8 and the overflow barrier region 3 must be electrically connected. That is, the impurity region 10 below the drain region 8 is
Of the photoelectrically converted electrons and holes, the charges on the non-accumulation side (electrons on this side) are allowed to escape to the shallow drain region 8 and the accumulated charges are prevented from leaking to an adjacent pixel. It plays the role of a potential barrier to prevent blooming.

Usually, the shallow source region 7 and the drain region 8 are formed in a self-aligned manner with the gate electrode 6 as a mask. On the other hand, deep n-type impurity regions 9 and 10
Is formed by ion implantation before forming the gate electrode 6 through another resist mask because the gate electrode 6 is thin and does not serve as a mask for ion implantation.

In the amplification type solid-state image pickup device 1 of the comparative example described above, the gate electrode 6 forming the pixel MOS transistor 13 is inevitably electrically separated for each pixel, and therefore the channel region 11 of the pixel region is formed. It is necessary to provide an opening for the contact portion 20 on the gate electrode 6 for wiring. Due to the wiring layout, first, the inter-pixel wiring layer 15
After forming, the vertical selection line 17 is formed in the horizontal direction.

The signal line 16 and the drain power source line 18, which are connected to the source region 7 and the drain region 8, respectively, are
Since each of them is formed along the vertical direction, it has a three-layer wiring structure and a complicated structure. In addition, there are problems in that there are many optical diffused reflections between wirings, uneven sensitivity, and large steps make it difficult to process.

In particular, the channel current and the sensor well region 1
In such a structure in which the contact hole must be opened immediately above the second structure, the following problems were practically serious obstacles.

Below the contact portion 20 with the gate electrode 6, a work function difference between the inter-pixel wiring layer 15 and the first wiring material,
The channel potential locally changes due to generation of charges in the oxide film due to process damage at the time of etching the contact hole, which causes variations in characteristics among pixels, which causes unevenness in the threshold voltage Vth and fixed patterns. Noise was aggravated and image quality was degraded.

Further, since the gate electrode 6 having a length of 1 μm or less is contacted, there is a problem that even a small contact opening of 0.5 μm has a margin of alignment of only 0.25 μm and the yield cannot be increased due to manufacturing variations. This processing problem is a major obstacle to miniaturization of pixels.

On the other hand, in the amplification type solid-state imaging device 1 of the above-mentioned comparative example, the shallow source region 7 and the drain region 8 and the deep impurity regions 9 and 1 in the pixel MOS transistor 13 are used.
There is a misalignment with 0. When misalignment occurs, the potential of the sensor well region 12 formed in an annular shape becomes uneven, and the distribution of the accumulated charges becomes non-uniform within the pixel, and at the same time, the current flowing through the channel becomes non-uniform.

As a result, the obtained electric signal varies. Therefore, for the amplification type solid-state imaging device, the shallow source region 7 and the drain region 8 and the deep impurity regions 9 and 10 must be formed in a self-aligning manner. However, the formation of the impurity regions 9 and 10 at deep positions requires ion implantation with high energy, and there is a problem that the thin gate electrode 6 cannot be used as a mask for self-alignment.

In view of the above points, the present invention provides a method for manufacturing an amplification type solid-state image pickup device which enables simplification of a wiring structure and uniformization of pixel characteristics.

[0019]

According to the method of manufacturing an amplification type solid-state image pickup device according to the present invention, before forming a gate electrode, a source region and a drain region are formed using the same mask, and the source region and the drain region. The lower impurity region is formed by ion implantation in a self-aligning manner, and then a wiring layer connecting the gate electrodes and the gate electrodes is formed by patterning the same conductive layer. Then, another wiring is connected to this wiring layer outside the channel region.

In this manufacturing method, since the source region and the drain region and the impurity region therebelow are formed in a self-aligning manner, there is no misalignment between the source region and the drain region and the impurity region therebelow. Since the wiring layer connecting the pixels is integrally formed of the same conductive layer as the gate electrode, the wiring structure can be simplified as a whole, and the amplification type solid-state imaging device can be stably manufactured with high yield. Further, by connecting another wiring to the wiring layer connecting the gate electrodes, there is no contact of the gate electrode on the channel region. Therefore, it is possible to manufacture an amplification type solid-state imaging device having uniform pixel characteristics and excellent image quality.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A method for manufacturing an amplification type solid-state image pickup device according to the present invention includes a source region and a drain region of a pixel using the same mask in the pixel region, and an impurity region below the source region and the drain region. And forming a conductive layer on the region where the source region and the drain region are formed, and patterning the conductive layer to connect the pixel gate electrode and the wiring layer connecting the gate electrodes to each other. And a step of connecting other wiring to the wiring layer.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 and 2 show an example of an amplification type solid-state image pickup device according to the present invention. The amplification type solid-state imaging device 31 according to the present example is of the first conductivity type, for example, p-type silicon semiconductor substrate 3
A second conductivity type, that is, an n-type semiconductor layer, that is, an overflow barrier region 33 and a p-type semiconductor well region 34 is formed on the second electrode 2, and a p-type charge accumulation well region that forms a channel, a so-called sensor well region 35 is formed. An annular gate electrode 37 capable of transmitting light is formed on the sensor well region 35 through a gate insulating film 36 made of SiO ₂ or the like.
The n-type source region 39 and the drain region 4 are formed corresponding to the center hole and the outer periphery of the ring-shaped gate electrode 37.
0 and the n-type impurity regions 41 and 42 are formed in the p-type semiconductor well region 34 below the uniform source region 39 and the drain region 40 to form a pixel M.
The OS transistor 43 is configured.

In this example, in particular, the adjacent pixels M
The gate electrodes 37 of the OS transistor 43 are connected to each other by the inter-pixel wiring layer 45 extending integrally with the gate electrode 37 on the insulating film of the drain region 40. The gate electrode 37 and the inter-pixel wiring layer 45 are formed of the same electrode material by simultaneous patterning.

The n-type impurity regions 41 and 42 are formed so as to electrically connect the shallow source region 39 and drain region 40 to the overflow barrier region 33, respectively.
For example, the n-type impurity regions 41 and 42 may be formed from the source region 39 and the drain region 40 to the overflow barrier region 33, respectively, or the source region 3
9 may be formed between the source region 39 and the drain region 40 and the overflow barrier region 33 so that the potential dip is not formed from the drain region 40 and the drain region 40 to the overflow barrier region 33.

The impurity concentrations of the n-type impurity regions 41 and 42 are set to be lower than the impurity concentrations of the source region 39 and the drain region 40 and higher than that of the overflow barrier region 33.

In particular, the impurity region 4 below the drain region 40
Similarly to the case described with reference to FIGS. 8 and 9, 2 is to allow the charges (electrons in this example) on the non-accumulation side of the photoelectrically converted electrons and holes to escape to the shallow drain region 40, and Of the electric field (potential barrier) for preventing blooming (that is, for preventing stored charges (holes in this example) from leaking to adjacent pixels, that is, a so-called channel stop region.

On the other hand, the impurity concentration relationship among the p-type semiconductor substrate 32, the p-type semiconductor well region 34 and the p-type sensor well region 35 is highest in the sensor well region 35, and then p
The type semiconductor substrate 32 and the p type semiconductor well region 34 are lowered in this order.

The ring-shaped gate electrode 37 is made of a thin material or a transparent material so as not to absorb light as much as possible. For example, polycrystalline silicon, tungsten polycide, tungsten silicide or the like can be used. In this example, a thin film of polycrystalline silicon having a good light-transmitting property is used.

This pixel MOS transistor 43 is shown in FIG.
As shown in FIG. 3, the source regions 3 of the pixel MOS transistors 43 corresponding to each column are arranged in a matrix.
9 is connected to a common signal line 51 made of, for example, the first layer Al formed along the vertical direction, and is provided at a position corresponding to each row of the pixel MOS transistors 43 so as to be orthogonal to the signal line 51, for example, the second layer. A vertical selection line 52 made of Al is formed along the horizontal direction, and the vertical selection line 52 and the inter-pixel wiring layer 45 integrally extending from the gate electrode 37 are connected.

Further, between the pixel MOS transistors 43 which are not connected by the inter-pixel wiring layer 45, a drain power supply line 53 made of, for example, the first layer Al connected to the drain region 40 is formed. Reference numeral 55 is a drain contact portion between the drain power supply line 53 and the drain region 40, 56 is a source contact portion between the source region 39 and the signal line 51, and 57 is a contact portion between the inter-pixel wiring layer 45 and the vertical selection line 52. In FIG. 1, reference numeral 58 represents a pixel region in which the pixel MOS transistors 43 are arranged.

The operation of this amplification type solid-state image pickup device 31 is the same as that described above, and the light passing through the ring-shaped gate electrode 37 is photoelectrically converted so that one of the charges, that is, the hole h, becomes the gate electrode 37.
It is accumulated in the lower sensor well region 35. Then, when a high voltage is applied to the ring-shaped gate electrode 37 through the vertical selection line 52 and the pixel MOS transistor 43 is turned on, a drain current (so-called channel current) flows into a channel on the surface of the sensor well region 35, and this drain is drained. When the current is changed by the signal charge h, this drain current is output through the signal line 51, and the amount of change is used as a signal output.

In the amplification type solid-state image pickup device 31 described above, since the inter-pixel wiring layer 45 connecting the adjacent gate electrodes 37 is formed by the extended portion from the gate electrode 37 itself, the gate electrode of FIG. The inter-pixel wiring layer formed separately from is omitted, and the two-layer wiring of the first layer Al wiring and the second layer Al wiring is sufficient. Therefore, the wiring structure is simplified, diffused reflection between the wirings is reduced optically, and sensitivity unevenness is reduced.

Since the gate electrode 37 has no contact portion, it is possible to realize a pixel structure having a high aperture ratio optically. Since there is no contact with the gate electrode 37,
Therefore, further miniaturization of pixels becomes possible.

Since there is no contact with the gate electrode 37 on the channel region, the local change of the channel potential is eliminated and the characteristics of each pixel become uniform. Therefore, the image quality can be improved.

Next, an example of a method of manufacturing the amplification type solid-state image pickup device 31 will be described.

In this example, as shown in FIG. 3A, p
An n-type overflow barrier region 33 and a p-type semiconductor well region 34 are sequentially formed on the type silicon substrate 32 by, for example, ion implantation, and a p-type sensor well region 35 is further formed by, for example, ion implantation, and then the sensor well region 35 is formed. An insulating film 64 made of, for example, SiO ₂ is formed on the surface of the.

Next, as shown in FIG. 3B, using the resist layer 60 patterned in the channel shape of the pixel, that is, the shape of the ring-shaped gate electrode as a mask, the overflow barrier region 33 has the same conductivity type, that is, the first n-type. To form the shallow source region 39 and the drain region 40 by ion implantation of the impurity 61, and ion implantation of the n-type second impurity 62 is performed using the same resist layer 60 as a mask to form the n-type impurity region 41 at a deep position.
And 42 are formed. As a result, the impurity regions 41 and 4 corresponding to the source region 39 and the drain region 40 are formed.
2 is formed as a self line. At the same time, the channel shape and the sensor well region 35 for charge storage are formed in a self-aligning manner, and uniform pixel characteristics are obtained.

Next, after removing the insulating film 64 contaminated by ion implantation or the resist layer 60 by wet etching, FIG.
As shown in C, a gate insulating film 36 of the pixel transistor is formed of SiO ₂ or the like, and a gate electrode material layer, for example, a polycrystalline silicon film 37A is formed on the gate insulating film 36.
It grows from 0 nm to several 100 nm.

If cleaning is performed to remove the contamination on the insulating film 64 contaminated with the resist, the insulating film 64 can be used as it is as the gate insulating film 36 without reoxidation. The polycrystalline silicon film 37A may be used as a conductor by growing doped polycrystalline silicon that grows while simultaneously doping impurities, or by diffusing phosphorus after growing polycrystalline silicon.

Then, on the polycrystalline silicon film 37A, an inter-pixel wiring layer (that is, a lead-out wiring layer for making a contact outside the channel) connecting two adjacent gate electrodes and an equal gate electrode by using the lithography technique. A resist layer 65 having a pattern corresponding to the integrated shape of and is formed. A portion of the resist layer 65 corresponding to the gate pattern completely covers at least the channel region, and further, in consideration of misalignment, the source region 39 and the drain region 40.
Is formed to take up to. This is to prevent the current driving capability from being significantly reduced when the gate electrode is separated from the drain region 40 or the source region 39.

Next, as shown in FIG. 4D, the resist layer 6
The polycrystalline silicon film 37A is patterned by dry etching using No. 5 as a mask to simultaneously form the gate electrodes 37, 37 of adjacent pixels and the inter-pixel wiring layer 45 connecting them. As a result, the pixel gate electrodes 37, 37
They are connected to each other to form a pixel MOS transistor 43.

Thereafter, the signal line 5 connected to the source region 37
1. The drain power supply line 53 connected to the drain region 40 and the vertical selection line 52 connected to the inter-pixel wiring layer 45 are wired to obtain the target amplification type solid-state imaging device 31 shown in FIG.

According to the above-mentioned manufacturing method, the processing pattern of the polycrystalline silicon film 37A forming the gate electrode 37 can be formed in a free form, completely independent of the charge storage characteristic of the pixel and the channel current characteristic. Is possible. That is, since the gate electrode 37 itself is extended and the extended portion is used as the inter-pixel wiring layer 45, the number of wiring layers is reduced, the number of manufacturing steps is reduced, the step is reduced, and stable manufacturing with high yield is enabled. At the same time, it enables wiring with a high degree of freedom. That is, as is apparent from other embodiments described later, the wiring layout can be freely set, which is suitable for forming finer pixels.

Since the gate electrode 37 and the inter-pixel wiring layer 45 are integrally formed of the same material so that the gate electrode 37 does not have a contact portion with the inter-pixel wiring layer 45, the optical aperture ratio of the pixel is increased. It is also possible to eliminate the local change in the channel potential.

By integrally forming the gate electrode 37 and the inter-pixel wiring layer 45 with the same material, it is possible to further miniaturize the pixel.

Further, the source region 39 and the drain region 40 and the deep impurity regions 41 and 42 can be formed in a self-aligning manner by ion implantation using the same mask. Therefore, it is possible to reduce the nonuniformity of the channel potential due to the misalignment of the source region 39 and the drain region 40 and the deep impurity regions 41 and 42, which is one of the causes of the pixel characteristic variation.

5 to 7 show other examples of the wiring layout in the pixel region of the amplification type solid-state image pickup device according to the present invention.

In the embodiment shown in FIG. 5, a wide common electrode that covers the entire gate portion (so-called channel region), that is, the gate electrode 37 and the inter-pixel wiring so as to connect all the gate electrodes 37 of the pixel MOS transistors 43 in the horizontal direction. A common electrode 71 that also serves as the layer 45 is formed and configured. Other than that, the signal line 51, the vertical selection line 52, and the drain power supply line 5 similar to those in FIG.
3 is formed.

With this structure, there is a margin for misalignment in the horizontal direction when processing the polycrystalline silicon film to be the gate electrode 37. That is, misalignment of the gate electrode 37 in the horizontal direction can be avoided.

In the embodiment of FIG. 6, when the total number of pixels is small,
Alternatively, this is an example suitable when the propagation delay of the gate electrode wiring does not pose a problem such as when the frame rate is slow, and as shown in the figure, the gate portion is formed so as to connect all the gate electrodes 37 of the pixel MOS transistors 43 in the horizontal direction. Forming a common electrode that also covers the gate electrode 37 and the inter-pixel wiring layer 45, and contacts the other wiring 73 at the end of the common electrode 72 that is led out of the pixel region 58. Can be configured. In this structure, the common electrode 72 also serves as a so-called vertical selection line. The other signal lines 51 and drain power supply lines 53 are wired in the same manner as in FIG.

According to this structure, the wiring of the gate electrode 37, the inter-pixel wiring layer 45 and the vertical selection line 52 can be realized with the single layer of the common electrode 72, and the wiring structure is further simplified.

Further, the embodiment of FIG. 7 is an example suitable for the case where the resistance of the drain common to each pixel does not matter,
As shown, the horizontal pixel MOS transistor 4
A strip-shaped common electrode having the same width, which covers all the gate portions, that is, the common electrode 74 which also serves as the gate electrode 37 and the inter-pixel wiring layer 45 is formed so as to connect the gate electrodes of No. 3, and the pixel electrode 58 of the common electrode 74 is formed. At the externally derived end,
The wiring 75 is connected, and the power supply line 76 is connected to the drain region at the end of the pixel region 58.

According to this structure, the drain power supply line 53 of Al shown in FIG. 1 is omitted, the wiring structure can be further simplified, and the sampling period is optically uniform, which is excellent. There is an advantage that the aperture of the pixel (that is, the area of the gate electrode for receiving light) is also increased.

The common electrodes 71 and 74 shown in FIGS.
By changing the pattern of the resist layer 65 when patterning the polycrystalline silicon film 37A of FIG. 4C,
It can be easily formed.

In the above example, the pixel MOS transistor 43
Although the n-channel type has been described as above, the same applies to the p-channel type.

[0057]

According to the method for manufacturing an amplification type solid-state image pickup device according to the present invention, since the number of wiring layers can be reduced, the number of steps is reduced and the number of steps is reduced, and this type of solid-state image pickup device is stable with high yield. Can be manufactured.

A pixel region having a small number of wiring layers and a simplified wiring structure can be formed, and a pixel transistor having an optically high aperture ratio can be obtained.

Since the wiring layer is formed by the gate electrode itself,
The degree of freedom in wiring layout is increased, and finer pixels can be formed.

The source region and the drain region and the impurity region below them can be formed in a self-aligned manner, and the nonuniformity of the sensor potential due to misalignment, which is one of the causes of pixel characteristic variations, can be reduced. can do.

Since contact is made outside the channel region,
That is, since the gate electrode has no contact portion, uniform pixel characteristics can be realized, and an amplification type solid-state imaging device with excellent image quality can be manufactured.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of an amplification type solid-state imaging device according to the present invention.

FIG. 2 is a sectional view of a portion of a pixel MOS transistor of FIG.

FIG. 3A is a manufacturing process diagram of an amplification type solid-state imaging device according to the present invention. B is a manufacturing process diagram of an amplification type solid-state imaging device according to the present invention.

FIG. 4C is a manufacturing process diagram of the amplification type solid-state imaging device according to the present invention. D is a manufacturing process diagram of the amplification type solid-state imaging device according to the present invention.

FIG. 5 is a plan view showing another example of the amplification type solid-state imaging device according to the present invention.

FIG. 6 is a plan view showing another example of the amplification type solid-state imaging device according to the present invention.

FIG. 7 is a plan view showing another example of the amplification type solid-state imaging device according to the present invention.

FIG. 8 is a plan view of an amplification type solid-state imaging device according to a comparative example.

9 is a cross-sectional view of a pixel MOS transistor portion of FIG.

[Explanation of symbols]

31 amplification type solid state imaging device, 32 p type semiconductor substrate, 3
3 overflow barrier region, 34 p-type semiconductor well region, 35 sensor well region, 36 gate insulating film, 37 gate electrode, 37A polycrystalline silicon film, 3
9 source region, 40 drain region, 41, 42 impurity concentration, 43 pixel MOS transistor, 45 inter-pixel wiring layer, 64 insulating film, 60, 65 resist layer, 6
1,62 ion-implanted impurities, 71,72 common wiring layer

Claims (1)

[Claims] 1. A step of forming a source region and a drain region of a pixel and an impurity region under the source region and the drain region by ion implantation in a self-aligned manner by using the same mask in the pixel region, the source region And a step of forming a conductive layer on the region where the drain region is formed, and patterning the conductive layer to simultaneously form a gate electrode of a pixel and a wiring layer connecting the gate electrodes, and another wiring in the wiring layer. A method for manufacturing an amplification type solid-state imaging device, which comprises a step of connecting