JPH09246882A - Bias stabilizing circuit for field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize bias without receiving the effect of the variation of a device characteristic and the fluctuation of a power source voltage without using an external component and without adjusting. SOLUTION: A bias stabilizing circuit by a current mirror system stabilizing the bias of FET 13 is provided with FET 19 for bias control constituting a current mirror circuit with FET 13 and a current saturated resistor Rcs as load resistance for FET 19. In the current saturated resistor Rcs , a current is increased in proportion to an applied voltage until the applied voltage reaches a prescribed voltage but when the applied voltage is more than the prescribed voltage, the current is saturated to be nearly constant. By the current saturated resistor Rcs , a current Idd1 on FET 19 side is kept constant and a current Idd2 on FET 13 side is also kept constant as the result, independently of the variation of the characteristic of FETs 13 and 19 and the fluctuation of the power source voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor bias stabilizing circuit for stabilizing the bias of a field effect transistor in, for example, a monolithic microwave integrated circuit.

[0002]

2. Description of the Related Art A monolithic microwave integrated circuit (hereinafter referred to as MMIC) having a field effect transistor (hereinafter also referred to as FET) using a compound semiconductor such as gallium arsenide.
It is written. ) Is excellent in high frequency characteristics and has low noise, and is therefore widely used in high frequency systems represented by mobile communications. For equipment in such high-frequency systems, one of the key points for cost reduction is how to easily make the characteristics uniform.
It is referred to as IC. ) Is required without adjustment. Further, in the above device, from the viewpoint of ensuring the operation time, that is, the usability, it is indispensable to guarantee the characteristics of the IC against the fluctuation of the power supply voltage.

Hereinafter, referring to FIGS. 16 to 23, F
Taking the case of an MMIC having ET as an example, consideration will be given to the adjustmentlessness of the above-mentioned IC and the guarantee of the characteristic of the IC against the fluctuation of the power supply voltage. FIG. 16 shows a configuration of a typical circuit of a one-stage amplifier based on MMIC. The MMIC 100 shown in this figure has an input terminal 101 for inputting a radio frequency (hereinafter referred to as RF) input signal, and an R terminal.
An output terminal 102 for outputting an F output signal, an FET 103 using a compound semiconductor such as gallium arsenide, a capacitor 104 provided between the input terminal 101 and the gate of the FET 103, and one end connected to the gate of the FET 103. A resistor 105 to which the DC gate bias voltage V _gg is applied to the other end, a capacitor 106 provided between the output terminal 102 and the drain of the FET 103, and one end of the FE
The coil 107 is connected to the drain of T103 and has the other end to which the power supply voltage V _dd ′ is applied, and the capacitor 108 having one end connected to the other end of the coil 107 and the other end grounded. Capacitors 106 and 108 and coil 107
Constitutes an output matching circuit for obtaining gain and output impedance matching in a desired frequency band.

In the MMIC 100 shown in FIG. 16, the FE
In order to stabilize the IC operating current against variations in the threshold voltage of T103, and in order to make the high frequency characteristics of the IC uniform, the gate bias voltage V _{gg is set} to the individual MM.
It had to be adjusted for each IC100. Therefore, conventionally, as disclosed in, for example, Japanese Patent Laid-Open No. 6-283942, an MMI is mounted on a substrate on which the MMIC 100 is mounted.
A bias non-adjustment circuit 110 as shown in FIG. 17 is provided separately from C100.

The bias non-adjusting circuit 110 shown in FIG.
Is a PNP bipolar transistor 111, a resistor R ₁ having one end connected to the base of the transistor 111 and the power supply voltage V _dd applied to the other end, one end connected to the base of the transistor 111 and the other end grounded. Resistance R
₂ , a resistor R _e having one end connected to the emitter of the transistor 111 and the other end to which the power supply voltage V _dd is applied, and a resistor R _c having one end connected to the collector of the transistor 111 and the other end grounded. the emitter of transistor 111 'is connected to the input terminal of the power supply voltage V _dd of the MMIC 100' MMIC 100 of the power supply voltage V _dd shown in FIG. 16 supplies a collector of the transistor 111 is connected to the gate of the FET103 in FIG 16 , The gate bias voltage V _gg of the FET 103 is supplied.

The bias non-adjusting circuit 110 shown in FIG.
Is a FET that feeds back the voltage drop across the resistor R _e
The bias of 103 is stabilized. When the bias-unadjusted circuit 110 is used, for example, the FET 10
3 increases, the voltage drop across the resistor R _e increases, resulting in a collector potential of the transistor 111, ie, the gate bias voltage V _{gg of the} MMIC 100.
And the increase of the drain current of the FET 103 is suppressed.

[0007]

However, FIG.
The bias non-adjustment circuit 110 as shown in FIG.
If it is provided on the substrate separately from 00, there is a problem that the number of components and the mounting area increase.

To cope with this, FIG. 18 or FIG.
MMIC including a bias stabilizing circuit configured as shown in FIG.
Has also been proposed.

The MMIC 120 shown in FIG. 18 uses a self-bias method, and its configuration is shown in FIG.
The source of the FET 103 in the MMIC 100 shown in (4) is grounded via a parallel circuit of a resistor R _s and a bypass capacitor C _s1 . Note that in FIG. 18, the power supply voltage of the MMIC 120 is V _dd . In the MMIC 120, if the gate bias voltage V _gg is fixed, the source-gate voltage V _{gs of the} FET 103
On the other hand, since negative feedback is applied through the resistor R _s based on the change in the drain current I _dd due to the variation in the threshold value V _th of the FET 103, the bias unadjusted shown in FIG. 17 in the MMIC 100 shown in FIG. The change in the drain current I _dd can be reduced as compared with the case where the circuit 110 is not provided.

However, in the circuit shown in FIG.
Since the resistance R _s is provided, the source-drain voltage V
_{Although ds} decreases, if the resistance value of the resistor R _s is increased to increase the stability of the drain current I _dd , the amount of decrease in the source-drain voltage V _ds increases, and the high frequency characteristics of the FET 103 may change. There is a problem called. Thus the increasing that the stability of the drain current I _dd keep the source-drain voltage V _ds of the FET103 is a trade-off, can not be eliminated variations in the drain current I _dd.

As a circuit for generating the gate bias voltage V _gg of the FET 103 in the MMIC 120 shown in FIG. 18, there is a circuit as shown in FIG. This circuit includes a resistor R ₃ to the power supply voltage V _dd to the one end is applied, and a R ₄ which is the other end one end connected to the other end of the resistor R ₃ is grounded, the resistor R _3, R ₄ The connection point is connected to the gate of the FET 103 shown in FIG. 18 and supplies the gate bias voltage V _gg of the FET 103. When the gate bias voltage V _gg is supplied by using the circuit shown in FIG.
_{Since the} gate bias voltage V _gg fluctuates due to the fluctuation of _dd , it becomes more difficult to stabilize the drain current I _dd .

On the other hand, the MMIC 130 shown in FIG.
For example, an active bias stabilizing circuit using a current mirror system as disclosed in JP-A-6-204757 is used. This MMIC 130 is shown in FIG.
There is no resistor 105 at
And a resistor R ₅ having one end connected to the drain of the FET 131 and the power supply voltage V _dd applied to the other end, and one end having the FET 13
A resistor R _g1 other end is connected to a gate connected to the gate of the FET103 of 1 and the other end is connected to the gate of one end FET131 and a capacitor C _s2 is grounded. The drain and gate of the FET 131 are connected, and the source is grounded.

According to the structure shown in FIG. 20, the FET 103 is different from the structure using the bias system shown in FIG.
Since it is not necessary to provide the bypass capacitor C _{s1 in} parallel with the source resistance (resistor R _s in FIG. 18) of, the chip area is significantly reduced, or the number of pins is reduced when a capacitor as a chip component is externally attached. Also contribute to. In addition, as shown in FIG. 18, there is no voltage drop when the source resistance R _s is used, so that the power supply voltage can be lowered.

The operating principle of the circuit shown in FIG. 20 will be described with reference to FIG. For simplicity,
The power supply voltage V _dd in FIG.
131 and FET 103 have the same device characteristics (however,
Only the gate width is different from W _g1 and W _g2 , respectively. ), The drain conductance is sufficiently small. FET13
In No. 1, since the gate and the drain are short-circuited and in the enhancement mode, the drain current (V _d1 ) _-drain current (I _dd1 ) characteristic is always in the drain current saturation region. 21 and behaves as shown by the characteristic line 141 in FIG. In the equation (1), k is a constant determined by the gate length, electron mobility and gate capacitance of the FET 131, and V _th is the threshold value of the FET 131.

[0015]

## _EQU1 ## I _dd1 = k (V _d1 −V _th ) ² (1)

Since the resistor R ₅ is attached to the drain side of the FET 131 as a load resistor, assuming that the voltage at the node n10 (connection point between the gate and drain of the FET 131) in FIG. 20 is V _g1 (= V _d1 ), Equation (2) is established. In the equation (2), R ₅ is the resistance value of the resistor R ₅ . Further, the characteristic of the equation (2) is shown by the characteristic line 142 in FIG.

[0017]

## _EQU2 ## V _dd = I _dd1 × R ₅ + V _g1 ∴I _dd1 = (-1 / R ₅ ) V _g1 + V _dd / R ₅ (2)

Therefore, the voltage V _{g1 of the} node n10 and the current I _dd1 of the bias stabilizing circuit (on the FET 131 side) are shown in FIG.
The voltage V _a and the current I _{a at} the intersection A of the characteristic line 141 and the characteristic line 142 in FIG. The resistor R _g and the capacitor C _s2 in FIG. 20 form a low-pass filter inserted to insulate the bias stabilizing circuit unit and the high frequency operation unit (on the FET 103 side) in terms of high frequency, and the resistance of the resistor R _g . When the value is set to several tens of kilohms and the capacitance of the capacitor C _s2 is set to about several picofarads, the gate voltage applied to the FET 103 can also be regarded as V _a because the gate current of the FET 103 is small. Therefore, the FET 103
The drain current I _dd2 flowing through the can be expressed by the following equation (3).

[0019]

(Equation 3)

Here, consider a case where the threshold values _Vth of the FETs 103 and 131 are changed. FIG. 22 shows the FET 10.
3 shows changes in the characteristic line 141 when the respective threshold values _{Vth of} 3,131 change. As shown in this figure, when the threshold values V _th of the _{FETs 103 and 131} are changed, I _dd1 is changed from the equation (1).
_dd1 corresponds to the increase / decrease of each threshold value _Vth of the FETs ₁₀₃ and 131, and is denoted by reference numeral 141a or 14 in FIG.
The characteristic line changes as shown by 1b. In this case, the intersection points A of the characteristic lines 141 and 142 are A1 and A, respectively.
From moving to 2, since the changes to the current I _a is also I _a1, I _a2, I _dd2 also changes from (3).

Next, consider the case where the power supply voltage V _dd changes. FIG. 23 shows a change in the characteristic line 142 when the power supply voltage V _dd changes. As shown in this figure, when the power supply voltage V _dd changes, I
_{Since dd1} changes, I _dd1 changes to a characteristic line as indicated by reference numeral 142a or 142b in response to an increase or decrease in the power supply voltage V _dd . In this case, the characteristic line 141 and the characteristic line 14
Since the intersection A with 2 moves to A3 and A4, respectively, the current I _a also changes to I _a3 and I _a4 , so that I _dd2 also changes from the equation (3).

Thus, conventionally, without using any external parts and without adjustment, an MMIC in which the drain current I _dd2 of the FET ₁₀₃ is not affected by variations in the characteristics of the FETs 103 and 113 and variations in the power supply voltage is realized. This is insufficient in both the self-bias system and the current mirror system.

The present invention has been made in view of the above problems, and the problem is that it is not affected by variations in characteristics of field effect transistors or variations in power supply voltage without using external parts and without adjustment. Another object of the present invention is to provide a bias stabilizing circuit for a field effect transistor, which can stabilize the bias of the field effect transistor.

[0024]

A bias stabilizing circuit for a field effect transistor according to claim 1, wherein an enhancement mode for bias control forms a current mirror circuit together with an enhancement mode field effect transistor which is an object of bias stabilization. In a bias stabilization circuit for a field-effect transistor using a current mirror method for stabilizing the bias of a field-effect transistor that is subject to bias stabilization, a predetermined load resistance for the field-effect transistor for bias control is specified. A current saturation resistance is provided so that the current saturates for an applied voltage of a value or more.

According to a second aspect of the present invention, there is provided a bias stabilizing circuit for a field effect transistor, comprising a field effect transistor for bias control which constitutes a current mirror circuit together with a field effect transistor which is a target of bias stabilization. In a bias stabilization circuit for a field effect transistor by a current mirror system that stabilizes the bias of the field effect transistor, the current saturates as a load resistance for the field effect transistor for bias control when an applied voltage of a predetermined value or more is applied. A current saturation resistance is provided, and a diode for forming a predetermined potential difference is provided between the gate of the field effect transistor for bias control and the electrode on the current saturation resistance side.

In the bias stabilizing circuit of the field effect transistor according to the first aspect, the current saturation resistance causes the current on the side of the field effect transistor for bias control without depending on the characteristic change of the field effect transistor or the power supply voltage. Is held constant, and as a result, the current on the side of the field effect transistor, which is the target of bias stabilization, is also held constant.

In the bias stabilizing circuit of the field effect transistor according to the second aspect, the diode forms a predetermined potential difference between the electrode on the current saturation resistance side of the field effect transistor for bias control and the gate. Not only when the field effect transistor targeted for bias stabilization and the field effect transistor for bias control are enhancement mode field effect transistors, but also when they are depletion mode field effect transistors, The field effect transistor can be operated in the saturation region, and the current saturation resistance keeps the current on the side of the field effect transistor, which is the target of bias stabilization, constant regardless of variations in the characteristics of the field effect transistor and fluctuations in the power supply voltage. Can be held at.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an MMIC that includes a bias stabilizing circuit for a field effect transistor according to a first embodiment of the present invention and that constitutes a one-stage amplifier.
The MMIC 10 includes an input terminal 11 for inputting an RF input signal, an output terminal 12 for outputting an RF output signal, and an enhancement mode FET that is a target of bias stabilization using a compound semiconductor such as gallium arsenide.
13, a capacitor 14 provided between the input terminal 11 and the gate of the FET 13, the output terminal 12 and the FET 13
And a capacitor 16 provided between the drain and the drain of the FET, one end of which is connected to the drain of the FET 13 and the other end of which is the power supply voltage V _dd.
And a capacitor 18 having one end connected to the other end of the coil 17 and the other end grounded. The capacitors 16 and 18 and the coil 17 constitute an output matching circuit for obtaining gain and output impedance matching in a desired frequency band.

The MMIC 10 is further connected to the drain of the FET 19 and an enhancement mode FET 19 for bias control which constitutes a current mirror circuit together with the FET 13 as a bias mirror circuit of the current mirror system for stabilizing the bias of the FET 13. And the current saturation resistance R _cs as a load resistance for the FET 19 to which the power supply voltage V _dd is applied to the other end and the FET 1 at one end.
It has a resistor R _g connected to the gate of the FET 9 and the other end of which is connected to the gate of the FET 13, and a capacitor C _s whose one end is connected to the gate of the FET 19 and whose other end is grounded. F
The drain and gate of ET19 are connected, and the source is grounded. As FETs 13 and 19,
Specifically, for example, MESFET (metal semiconductor FET)
A JFET (junction type FET) is used.

FIG. 2 shows the voltage-current characteristics of the current saturation resistance R _cs . As shown in this figure, in the current saturation resistance R _cs , the current increases in proportion to the applied voltage until the applied voltage reaches the predetermined voltage V _cs , but the applied voltage is the predetermined voltage V _cs.
When it is more than _cs , the current is saturated and becomes almost constant. Less than,
V _cs is called a saturation voltage, and a current when saturated is described as a saturation current I _cs . The properties shown in FIG. 2 are GaAs, A
It is found in gallium arsenide-based compound semiconductors such as 1GaAs / GaAs (heterojunction of AlGaAs and GaAs). Therefore, the current saturation resistance R _cs is GaAs, AlG
A gallium arsenide-based compound semiconductor such as aAs / GaAs is used. As the material of the current saturation resistance R _cs, taking the case of using the most typical GaAs compound semiconductor as an example, the electric field of the electron traveling direction in the current saturation resistance R _cs is about 3.
At a voltage of 5 × 10 ³ V / cm (hereinafter referred to as E _cs ) or more, the electron traveling speed is saturated. This phenomenon is based on electron-valley (valley of conduction band) transition due to energy obtained from the electric field, and steep velocity saturation occurs in a relatively low electric field because the energy difference between the valleys is 0.29.
This is because eV is small (at an absolute temperature of 300 ° C.), the electron mobility in a low electric field is high and the acceleration by the electric field is good, and the electron mobility of the valley after the transition is much smaller than that before the transition. That is, the current saturation resistance R _cs
Is a device that utilizes physical properties peculiar to GaAs and the like and cannot be obtained by silicon.

FIG. 3 is a plan view showing an example of the element structure of the current saturation resistance R _cs using gallium arsenide, and FIG. 4 is a sectional view of FIG. In the current saturation resistance R _cs shown in these figures, a channel 21 made of an N-type impurity layer is formed on the semi-insulating GaAs substrate 20 to form the resistance layer 22.
The channel 21 at a position facing each other with the resistance layer 22 in between.
The ohmic electrodes 23 and 24 are joined on the upper side. The channel 21 is formed by, for example, ion implantation or crystal growth. Note that, in the example shown in FIG. 4, for simplification, the portions below the ohmic electrodes 23 and 24 in the channel 21 have the same impurity concentration as that of the resistance layer 22, but the impurity concentration is higher than that of the resistance layer 22. It may be a dark layer. Thus, the element structure of the current saturation resistance R _cs is M
It has the same structure as the normal resistance in the MIC10.
There is no additional process step in forming the current saturation resistance R _cs in the IC 10.

Here, the sheet resistance of the resistance layer 22 is ρ _s ,
In the channel 21, the ohmic contact resistance between the ohmic electrodes 23 and 24 and the channel 21 is R _c , the width of the resistance layer 22 between the ohmic electrodes 23 and 24 is W, and the length is L as shown in FIG. Assuming that the electric field distribution is uniform, the saturation voltage V _cs and the saturation current I _cs are expressed by the following equations.

[0034]

V _cs = E _cs × L + 2R _c × I _cs I _cs = V _cs / {(ρ _s × L / W) + 2R _c }

That is, the characteristics of the current saturation resistance R _cs of the structure shown in FIGS. 3 and 4 are determined by the device dimensions (W, L) and the process conditions, but both ρ _s and R _c are determined after the conditions are determined. Since the variation of is relatively small, the current saturation resistance R _cs can be created with stable characteristics.

Next, the operation of the MMIC 10 including the bias stabilizing circuit for the field effect transistor according to the present embodiment will be described.

As in the case of the example shown in FIGS. 20 and 21, for simplification, the power supply voltage V _dd in FIG. 1 is sufficiently large, and FET 19 and FET 13 have the same device characteristics (however, only the gate width is different). , W _g1 and W _g2 respectively
And different. ), The drain conductance is sufficiently small. Since the gate and drain of the FET 19 are short-circuited and in the enhancement mode, the FET 19 is always in the drain current saturation region and its drain voltage (V _d1 ).
The _−drain current (I _dd1 ) characteristic behaves as shown by the characteristic line 41 in the equation (1) and FIG.

Since the current saturation resistance R _cs is attached to the drain side of the FET 19 as a load resistance, the drain current I _dd1 of the FET ₁₉ is a constant value I _cs until V _d1 reaches V _dd -V _cs . When V _d1 becomes V _dd −V _cs or more, V _dd
Decreases linearly until. This characteristic is shown by the characteristic line 42 in FIG.

Therefore, the node n1 (FET
19 gate-drain connection point) voltage V _g1 (=
V _d1 ) and the current I _dd1 of the bias stabilizing circuit (on the side of the FET 19) become the voltage V _b and the current I _{cs at} the intersection B between the characteristic line 41 and the characteristic line 42 in FIG. 5, respectively. Further, if the resistance value of the resistor R _g is set to several tens of kilo ohms and the capacity of the capacitor C _s is set to about several picofarads, the gate voltage applied to the FET 13 can be regarded as V _{b in} combination with the small gate current of the FET 13. . Therefore, the FET
The drain current I _dd2 flowing through 13 can be expressed by the following equation (4).

[0040]

(Equation 5)

Here, consider a case where the threshold values V _{th of the} FET 13 and the FET 19 are changed. FIG. 6 shows FET1
3 shows changes in the characteristic line 41 when the respective threshold values V _{th of the} FET 19 are changed. As shown in this figure, FET 13, when the threshold V _th of the FET19 is varied (1) for I _dd1 changes from the equation, I _dd1
Changes to a characteristic line as indicated by reference numeral 41a or 41b in FIG. 6 in response to increase / decrease of each threshold value V _th of the FET 13 and the FET 19. In this case, the intersection B between the characteristic line 41 and the characteristic line 42 moves to B1 and B2, respectively, but the current I _dd1 remains I _cs , and therefore I _dd2 does not change from the equation (4).

Next, consider the case where the power supply voltage V _dd changes. FIG. 7 shows changes in the characteristic line 42 when the power supply voltage V _dd changes. As shown in this figure, when the power supply voltage V _dd changes, I _dd1 becomes the power supply voltage V _dd.
In response to the increase or decrease of, the characteristic line changes as indicated by reference numeral 42a or 42b. In this case, since the intersection B between the characteristic line 41 and the characteristic line 42 does not move, the current I still remains.
_dd1 does not change as I _cs , and I _dd2 does not change from the equation (4).

As described above, in the present embodiment, the power supply voltage V _dd is large as the saturation voltage V _cs of the current saturation resistance R _cs satisfies the condition of the following expression (5), and the FET characteristic is FET1.
Assuming that the variations between 3 and 19 are sufficiently small, and their drain conductances are sufficiently small, I _dd1 , I
_dd2 both current saturation resistance R _cs saturation current I _cs and FET1
It is determined by the gate width of 3,19. Therefore, I _dd1 , I _dd2
The total power supply current I _dd , which is the sum of
It does not depend on variations in FET characteristics such as variations in the threshold voltage _Vth of 13 and 19 and variations in power supply voltage.

[0044]

## _EQU6 ## V _cs ≤V _dd -V _b (5)

Here, the simulation results of the circuit simulator (SPICE) of this embodiment will be described. In this example, V _dd = 3V, W _g1 = 4 μm, W _g2
= 200 μm, I _dd is a low noise amplifier of about 4 mA. Here, although there is no variation in the FET characteristics between the FETs 13 and 19, as the FET characteristics, the DC characteristic extraction result of the actual device is used for each threshold value V _th . Therefore, regarding drain conductance (4)
It is not small enough to satisfy the formula. Regarding the current saturation resistance R _cs , V _cs = 1.0 V, I _cs = 6
The characteristic was 0 μA. Further, it is assumed that the threshold voltages V _{th of the} FETs 13 and 19 may fluctuate ± 0.2 V with respect to the center value 0.3 V, and the power supply voltage V _dd fluctuates ± 10% with respect to the center value 3 V. . These assumptions are common in MMICs for mobile communications. FIG. 8 shows the results of the simulation based on the above conditions.
19 threshold voltage V _th , current I _dd2 and power supply voltage V
_It shows the relationship of _dd .

For comparison, FIG. 9 shows a similar simulation result in the case of using the conventional active bias stabilizing circuit of the current mirror system shown in FIG. Comparing FIG. 8 and FIG. 9, it can be seen that the stability of the current I _dd2 is obviously higher when the bias stabilizing circuit according to the present embodiment is used.

As described above, according to the bias stabilizing circuit of the present embodiment, the current saturation resistance R _cs is provided as the load resistance for the FET 19 for bias control. Therefore, the current saturation resistance R _cs causes the FETs 13 and 19 to operate. F for bias control, regardless of variations in characteristics and fluctuations in power supply voltage
ET19 side current I _dd1 is held constant, as a result,
Current I _dd2 on the FET 13 side that is the target of bias stabilization
Is also kept constant. Therefore, it is possible to stabilize the bias of the FET 13 without using external parts and without adjustment, without being affected by variations in the characteristics of the FET and variations in the power supply voltage. As a result, IC and set cost reduction by improving yield and reducing parts, IC
It can be expected to improve usability. Further, the provision of the current saturation resistance R _cs in the MMIC 10 can be performed without changing the process steps in the conventional MMIC.

Next, a bias stabilizing circuit for a field effect transistor according to a second embodiment of the present invention will be described.

In the conventional active bias stabilizing circuit of the current mirror system as shown in FIG. 20, in order to maintain stability, the FET1 on the bias stabilizing circuit side is used.
31 must operate in the drain current saturation region,
In the circuit in which the gate and the drain are directly connected, there is a restriction that the FET 131 is limited to the enhancement mode.
This restriction is the same as in the bias stabilizing circuit according to the first embodiment of the present invention.

By the way, in a power amplifier MMIC or the like used in a transmitter of a mobile communication device, a depletion mode FET is usually used in order to earn output saturation power. In this case, normally, the bias stabilizing circuit having the configuration shown in FIG. 20 is not used, and the self-bias method shown in FIG. 18 is a candidate. , Especially the source resistance R _s
Since the voltage drop at 1 leads to a reduction in the output saturation power of the MMIC, it is rarely used in the power amplifier MMIC.

As described above, conventionally, regarding the MMIC using the depletion mode FET, an effective means for stabilizing the bias without being influenced by the fluctuation of the FET characteristics and the fluctuation of the power supply voltage is There wasn't.
The bias stabilization circuit for the field effect transistor according to the present embodiment is not limited to the circuit using the enhancement mode FET, and the circuit using the depletion mode FET is similar to that of the first embodiment. FET
The bias can be stabilized without being affected by the variation in the characteristics of (1) and the fluctuation of the power supply voltage.

FIG. 10 includes a bias stabilizing circuit for a field effect transistor according to the second embodiment of the present invention.
It is a circuit diagram which shows the structure of MMIC which comprises a stage amplifier. This MMIC 30 is different from the MMIC 10 shown in FIG. 1 in that the gate and drain of the FET 19 are not directly connected but a diode 31 is newly provided in which the anode is connected to the drain of the FET 19 and the cathode is connected to the gate of the FET 19. Is. In the present embodiment, the FETs 19 and 13 may be either in the enhancement mode or the depletion mode. Other configurations are similar to those of the first embodiment.

Next, the operation of the MMIC 30 including the bias stabilizing circuit for the field effect transistor according to the present embodiment will be described.

For simplification, the power supply voltage V _dd in FIG. 10 is sufficiently large, and the FET 19 and FET 13 have the same device characteristics (however, only the gate width is W, respectively).
Different from _g1 and W _g2 . ), The drain conductance is sufficiently small.

First, consider the conditions under which the FET operates in the drain current saturation region. When the drain-source voltage of the FET is V _ds and the gate-source voltage is V _gs ,
The condition that the FET operates in the drain current saturation region is expressed by the following equation (6).

[0056]

(7) V _ds ≧ V _gs −V _th (6)

When the gate and drain of the FET 19 are directly connected as shown in FIG. 1, V _gs = V _ds , and therefore (6)
The expression is V _th > 0, that is, FE in enhancement mode.
Only when T is satisfied. On the other hand, when the equation (6) is rewritten for the depletion mode FET, the following equation (7) is obtained.

[0058]

[Equation 8] 0 <| V _th | ≦ V _ds −V _gs (where V _th <0) (7)

In other words, V _ds may be made larger than V _gs by at least the absolute value of V _th . Therefore, in the present embodiment, the diode 31 is inserted between the gate and drain of the FET 19 so that the drain side serves as the anode and the gate side serves as the cathode. In a mobile communication device, since it is necessary to operate the entire device as a positive power supply, it is desired that the gate bias of the MMIC is originally a positive power supply. in this case,
Always 0 <for depletion mode FET
V _gs . Now, replace the diode 31 in FIG.
The same type as the gate of ET19 (for example, FET19 is M
The diode 31 is a Schottky junction type when ESFET is used, and the diode 31 is P when FET 19 is JFET.
N-junction type). Since the gate current of the FET 19 flows through the diode 19, when the turn-on voltage of the diode 19 is V _diode , the junction width W _diode of the diode 19 is selected smaller than W _g1 so that | V _th | ≦ V _diode . Accordingly, since V _diode is V _d1 −V _g1 in the FET 19, the following equation (8) is established,
From the equation (7), the FET 19 operates in the saturation region.

[0060]

[Equation 9] | V _th | ≦ V _diode = V _d1 −V _g1 (8)

If | V _th | becomes larger than the turn-on voltage V _diode of one diode 19, if a plurality of diodes 19 are connected in series and the sum of those turn-on voltages is V _diode , _{│V th} │≤V
The relational expression of _diode is kept. However, it should be noted that if | V _th | is too large, it may violate the condition of the equation (11) described later.

Next, a bias stabilizing operation in the MMIC 30 including the bias stabilizing circuit for the field effect transistor according to the present embodiment will be described with reference to FIG.

The FET 19 has the FE
Since T13 has a sufficiently large power supply voltage V _dd , both are in the drain current saturation region. The drain voltage (V _d1 ) _-drain current (I _dd1 ) characteristics of the _{FET 19} are the following (9).
It is expressed by an equation. In the equation (9), k is an FET
19 is a constant determined by the gate length, electron mobility, and gate capacitance.

[0064]

I _dd1 = k (V _g1 + | V _th |) ² = k {V _d1 − (V _diode − | V _th |)} ² (where V _th <0) ... (9)

From the equation (8), V _diode − | V _th | ≧ 0, and the equation (9) has the characteristic shown by the characteristic line 51 in FIG. Here, since the current saturation resistance R _cs are attached as a load resistor to the drain side of the FET 19, the drain current I _dd1 of FET 19 is to V _d1 reaches V _dd -V _cs is constant I _cs, V _d1 is V _dd Above −V _cs , it decreases linearly until it reaches V _dd . This characteristic is shown by the characteristic line 52 in FIG.

Therefore, the node n2 (FET
Voltage V _{d1 at} the connection point between the drain of No. 19 and the current saturation resistance R _cs and the current I at the bias stabilizing circuit (on the side of the FET 19)
_dd1 is the voltage V _c and the current I _{cs at} the intersection C between the characteristic line 51 and the characteristic line 52 in FIG. 11, respectively. Therefore,
The gate voltage of the FET19 becomes V _c -V _diode. FIG.
The resistor R _g and the capacitor C _{s2 at} 0 constitute a low-pass filter inserted to insulate the bias stabilizing circuit unit and the high frequency operation unit (on the FET 13 side) in high frequency, and the resistance value of the resistor R _g . If the capacitance of the capacitor C _s is about several picofarads, then the FET
In combination with the small gate current of FET 13,
The gate voltage applied to V can also be regarded as V _c −V _diode . Therefore, the drain current I _dd2 flowing through the FET ₁₃
Can be expressed by the above-mentioned equation (4) as in the first embodiment.

Here, consider a case where the threshold values V _{th of the} FET 13 and the FET 19 are changed. Figure 12 shows FET1
3 shows changes in the characteristic line 51 when the respective threshold values V _{th of the} FET 19 are changed. As shown in this figure, when the threshold values V _{th of the} FET 13 and the FET ₁₉ change, I _dd1 changes according to the equation (9). _Therefore , I _dd1
Changes to a characteristic line as indicated by reference numeral 51a or 51b in FIG. 12 in response to increase / decrease in each threshold value V _th of the FET 13 and FET 19. In this case, the intersection C of the characteristic line 51 and the characteristic line 52 moves to C1 and C2, respectively, but the current I _dd1 remains I _cs , and therefore (4)
From the formula, I _dd2 also does not change.

Next, consider the case where the power supply voltage V _dd fluctuates. FIG. 13 shows a change in the characteristic line 52 when the power supply voltage V _dd changes. As shown in this figure, when the power supply voltage V _dd changes, I _dd1 becomes the power supply voltage V _dd.
The characteristic line changes as indicated by reference numeral 52a or 52b in accordance with the increase or decrease of _dd . In this case, the intersection C between the characteristic line 51 and the characteristic line 52 because it does not move, also the current I _dd1 does not change from I _cs, (4) I _dd2 also unchanged from the equation.

As described above, in the present embodiment, the power supply voltage V _dd is large as the saturation voltage V _cs of the current saturation resistance R _cs satisfies the condition of the following expression (10), and the FET characteristic is FET1.
Assuming that the variations between 3 and 19 are sufficiently small, and their drain conductances are sufficiently small, I _dd1 , I
_dd2 both current saturation resistance R _cs saturation current I _cs and FET1
It is determined by the gate width of 3,19. Therefore, I _dd1 , I _dd2
The total power supply current I _dd , which is the sum of
It does not depend on variations in FET characteristics such as variations in the threshold voltage _Vth of 13 and 19 and variations in power supply voltage.

[0070]

(11) V _cs ≦ V _dd −V _c (10)

Since V _c is the drain voltage of the FET 19, V _dd must satisfy the condition of the following formula (11) from the formulas (8) and (10).

[0072]

[ _Equation 12] V _g1 + V _diode + V _c ≦ V _dd (11)

Here, the simulation results of the circuit simulator (SPICE) of this embodiment will be described. In this example, V _dd = 3V, W _g1 = 8 μm, W
The power amplifier is _diode = 4 μm, W _g2 = 2 mm, and I _dd is about 180 mA. Here, FETs 13 and 19
Although there is no variation in the FET characteristics between the FETs, the FET characteristics are obtained by extracting the DC characteristics of the actual device for each threshold value V _th . Therefore, the drain conductance cannot be said to be sufficiently small to satisfy the equation (4). Regarding the current saturation resistance R _cs , the characteristics of V _cs = 1.0 V and I _cs = 0.6 mA were set based on the actual measurement results. Further, the threshold voltage V _{th of the} FETs 13 and 19 fluctuates ± 0.2 V with respect to the center value −0.3 V, and the power supply voltage V _dd
Is supposed to fluctuate ± 10% with respect to the center value of 3V. These assumptions are common in MMICs for mobile communications.

Simulation results based on the above conditions are shown in FIGS. FIG. 14 shows FETs 13 and 1
9 threshold voltages V _th and V _g1 , V _g1 + | V _th |, V _d1 ,
It shows the relationship with V _dd -V _d1 . FIG.
_Shows the relationship between V _th and I _dd2 . FIG.
Therefore, this example satisfies both the condition that the FET 19 operates in the drain current saturation region (equation (7)) and the condition that a sufficient voltage is applied to the current saturation resistance R _cs (equation (10)). I understand. Further, from FIG. 15, I
_dd2 has a current fluctuation width of about 20 with _{respect to} fluctuations of V _dd and V _th.
mA (about ± 10 mA (± 5.6%) with respect to the center value) is kept small, and according to the bias stabilizing circuit of the present embodiment, the stability of the current I _dd2 is _improved even in an actual device. It turns out to be expensive.

As described above, according to the bias stabilizing circuit of the present embodiment, as in the first embodiment, the FET characteristic variation and the power supply voltage are adjusted without using external parts and without adjustment. FET unaffected by fluctuations in
The bias of 13 can be stabilized. As a result, it is expected that the yield of the IC and the cost of the IC and the set will be reduced by reducing the number of parts, and the usability of the IC will be improved. Moreover, the bias stabilizing circuit according to the present embodiment is not limited to the circuit using the enhancement mode FET,
Since it can be applied to a circuit using a depletion mode FET, current stabilization of a power amplifier, which occupies a large amount of current consumption in a mobile communication device, can be realized. It becomes a very effective means. Further, the provision of the current saturation resistance R _cs and the diode 31 in the MMIC 30 can be performed without changing the process steps in the conventional MMIC.

The present invention is not limited to the above-mentioned respective embodiments. For example, the circuit to which the present invention is applied is not limited to the circuit having the configuration shown in FIG. 1 or FIG. , MMIC, and can be applied to circuits for other purposes.

[0077]

As described above, according to the bias stabilizing circuit for a field effect transistor of the first aspect, in the bias stabilizing circuit for a field effect transistor according to the current mirror system, the load on the field effect transistor for bias control is increased. As the resistance, a current saturation resistor that saturates the current with respect to an applied voltage of a predetermined value or more is provided, so that the current on the side of the field effect transistor for bias control is held constant, and as a result, it becomes the target of bias stabilization. The current on the side of the field effect transistor is also kept constant, and without adjustment of external parts and without adjustment, the bias of the field effect transistor in the enhancement mode is not affected by the characteristic variation of the field effect transistor and the fluctuation of the power supply voltage. The effect of being able to stabilize is produced.

According to the bias stabilizing circuit for a field effect transistor of the present invention, a current saturation resistor is provided as a load resistance for the field effect transistor for bias control, and the gate of the field effect transistor for bias control is provided. Since a diode for forming a predetermined potential difference is provided between the electrode on the current saturation resistance side, in addition to the above effects, not only a circuit using an enhancement mode field effect transistor but also a depletion mode electric field There is an effect that it can be applied to a circuit using an effect transistor.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an MMIC including a bias stabilizing circuit for a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing voltage-current characteristics of the current saturation resistance in FIG.

FIG. 3 is a plan view showing an example of an element structure of a current saturation resistance using gallium arsenide.

4 is a cross-sectional view of the element structure of the current saturation resistance shown in FIG.

5 is a characteristic diagram showing a drain voltage-drain current characteristic of the FET for bias control in FIG.

6 is a characteristic diagram showing changes in drain voltage-drain current characteristics when the threshold value of the FET in FIG. 1 changes.

FIG. 7 is a characteristic diagram showing changes in drain voltage-drain current characteristics of the FET when the power supply voltage in FIG. 1 varies.

FIG. 8 is a characteristic diagram showing a simulation result of the bias stabilizing circuit for the field effect transistor according to the first embodiment of the invention.

FIG. 9 is a characteristic diagram showing a simulation result in the case where an active bias stabilizing circuit by a conventional current mirror method is used.

FIG. 10 is a circuit diagram showing a configuration of an MMIC including a bias stabilizing circuit for a field effect transistor according to a second embodiment of the present invention.

11 is a characteristic diagram showing drain voltage-drain current characteristics of the FET for bias control in FIG.

12 is a characteristic diagram showing changes in drain voltage-drain current characteristics when the threshold value of the FET in FIG. 10 changes.

13 is a characteristic diagram showing changes in the drain voltage-drain current characteristics of the FET when the power supply voltage in FIG. 10 varies.

FIG. 14 is a characteristic diagram showing a simulation result of a bias stabilizing circuit for a field effect transistor according to a second embodiment of the present invention.

FIG. 15 is a characteristic diagram showing a simulation result of the bias stabilizing circuit for the field effect transistor according to the second embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of a typical circuit of a conventional one-stage amplifier based on MMIC.

FIG. 17 is a circuit diagram showing a configuration of a conventional bias-unadjusted circuit.

FIG. 18 is a conventional MMIC using a self-bias method.
FIG. 3 is a circuit diagram showing the configuration of FIG.

19 is a circuit diagram showing a configuration of a circuit for generating a gate bias voltage of the circuit shown in FIG.

FIG. 20 is a circuit diagram showing a configuration of an MMIC including an active bias stabilizing circuit according to a conventional current mirror method.

FIG. 21 is a characteristic diagram showing drain voltage-drain current characteristics of the FET for bias control in FIG. 20.

22 is a characteristic diagram showing changes in drain voltage-drain current characteristics when the threshold value of the FET in FIG. 20 changes.

23 is a characteristic diagram showing changes in the drain voltage-drain current characteristics of the FET when the power supply voltage in FIG. 20 varies.

[Explanation of symbols]

10 ... MMIC, 13, 19 ... FET, 31 ... Diode, R _cs ... Current saturation resistance

Claims (2)

[Claims] 1. A bias of an enhancement mode field effect transistor for bias control, comprising an enhancement mode field effect transistor for bias control, which constitutes a current mirror circuit together with an enhancement mode field effect transistor for bias stabilization. In a bias stabilization circuit of a field effect transistor by a current mirror method for stabilizing the voltage, a current saturation resistance that current saturates at an applied voltage of a predetermined value or more is provided as a load resistance for the field effect transistor for bias control. A bias stabilizing circuit for a field effect transistor, characterized in that: 2. A current mirror having a field-effect transistor for bias control, which constitutes a current mirror circuit together with a field-effect transistor to be bias-stabilized, for stabilizing the bias of the field-effect transistor to be bias-stabilized. In a bias stabilizing circuit for a field effect transistor according to the method, as a load resistance for the field effect transistor for bias control, a current saturation resistance for saturating a current with respect to an applied voltage of a predetermined value or more is provided, A bias stabilizing circuit for a field effect transistor, wherein a diode for forming a predetermined potential difference is provided between the gate of the field effect transistor and the electrode on the side of the current saturation resistance.