JPH1126776A - Dual gate fet and high frequency circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high frequency circuit having a power amplifier circuit which can reduce the power consumption and improve the power efficiency, without increasing the distortion, and realize a high performance, small size and high efficiency of a dual gate FET using this power amplifier circuit. SOLUTION: With high frequency signals fed to first gates at the drain side of dual gate FETs 2, 3 and DC bias voltages fed to second gates at the source side thereof, the DC bias voltages control the output power of a power amplifier circuit 1. The second gate electrode length of the dual gate FETs 2, 3 are made shorter than the first gate electrode length.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a dual gate F
The present invention relates to an ET and a high-frequency circuit using the dual-gate FET, and particularly to a high-frequency circuit used for a wireless communication device such as a mobile phone.

[0002]

2. Description of the Related Art In a radio communication device, particularly a portable telephone, the size of the telephone is reduced in order to improve portability, and the integration of circuits is promoted in order to reduce the number of parts used. . However, the largest and heaviest thing in a telephone is a battery, and it is necessary to reduce the power consumption of the circuit in order to reduce the size of the battery. In addition, since the current consumption of the power amplifier used in a mobile phone is almost proportional to the output power of the mobile phone, when the mobile phone is used near a base station, the output power of the radio signal from the mobile phone is reduced. Therefore, the power consumption of the mobile phone has been reduced by changing the output power of the wireless signal from the mobile phone according to the distance between the mobile phone and the base station.

[0003] In such portable telephones and simple portable telephones (PHS: Personal Handyphone System), the frequency used is 0.9 GHz or 1.5 GHz for portable telephones.
Since a simple mobile phone has a frequency of 1.9 GHz, a gallium arsenide (GaAs) element, which consumes less power at a high frequency than a silicon (Si) element, is used as a power amplifier. Next, a power amplifier using a field effect transistor (hereinafter, referred to as an FET) as a gallium arsenide element will be described.

FIG. 11 is a schematic circuit diagram showing a conventional example of a high-frequency circuit. FIG. 11 shows an example of a power amplifier circuit used in a wireless communication device such as a mobile phone. In FIG. 11, a high-frequency circuit 100 includes a power amplifying unit 101 including a power amplifier, a control circuit unit 102, an IF circuit unit 1
03, power detector 104, single-gate FET 10
5 and the battery 106. IF circuit section 103
Is a circuit for converting a transmission signal of an intermediate frequency into a high-frequency signal, and the power amplifying section 101 amplifies and outputs the transmission signal converted to a high-frequency signal by the IF circuit section 103. The power detection unit 104 detects the output power of the power amplification unit 101, and the control circuit unit 102 determines the power amplification unit 101, the IF, based on the power value detected by the power detection unit.
The circuit unit 103 and the FET 105 are controlled.

The power amplifying section 101 has a single gate F
ETs 111 to 114, matching circuits 115 to 119 for impedance matching, and resistors 120 and 121 are formed. The transmission signal converted into a high-frequency signal by the IF circuit unit 103 is input from the input terminal IN of the power amplification unit 101 to the gate of the FET 112 via the matching circuit 115,
The power is amplified by the power amplifier 101 and output from the output terminal OUT. The FET 105 changes the voltage supplied from the battery 106 in accordance with a control signal from the control circuit unit 102, and supplies the voltage from the drain voltage input terminal Din to the drains of the FETs 111 and 113 of the power amplification unit 101. Further, the control circuit unit 102 controls the FETs 111 and 1 of the power amplification unit 101 via the gate voltage input terminal Gin.
A voltage is supplied to each of the gates 13.

Here, the input power input to the input terminal IN is Pin, the output power output from the output terminal OUT is Pout, the voltage input to the drain voltage input terminal Din is Va, and the gate voltage input is The voltage input to the terminal Gin is Vb. The control circuit unit 102 changes the output power of the IF circuit unit 103 according to the output power Pout detected by the power detection unit 104.
Control. Further, the control circuit unit 102 controls the FET 1 in accordance with the output power Pout detected by the power detection unit 104.
05 to control the drain voltage input terminal Din
And the voltage supplied to the gate voltage input terminal Gin is controlled.

FIG. 12 shows the power amplifier 10 shown in FIG.
FIG. 2 is a diagram illustrating input / output characteristics of the first embodiment. As can be seen from FIG. 12, the output power Pout increases with an increase in the input power Pin, and in the range where the input power Pin is about 0 dBm or less, the output power Pout increases in proportion to the input power Pin. In the range where the power Pin exceeds 0 dBm, the output power Pou
The increase in t slows down and saturates. The power efficiency η also increases with an increase in the input power Pin in a range where the input power Pin is small, increases sharply when the input power Pin reaches a certain value, and increases when the input power Pin further increases and increases. Increases slowly, and decreases when the input power Pin exceeds a certain value. In the power amplifying section 101, power consumption can be reduced by using the power amplifying section η so as to increase the power efficiency η.

Further, FIG. 12 shows a distortion IM, which is, for example, a third-order distortion. The distortion IM is, for example, a frequency f1 and a frequency f that is Δf away from the frequency f1.
2 are input to the power amplification unit 101, and (f)
This is a comparison between the power of the output signal wave of the power amplifying unit 101 having the frequency component of 1−Δf) or (f2 + Δf) and the power of the output signal wave of the power amplifying unit 101 having the frequency component of the frequency f1. In FIG. 12, the distortion IM decreases as the input power Pin decreases.

In the power amplifying section 101 as described above,
It is difficult to make the power efficiency η equal when the output power Pout is small and when the output power Pout is large. Therefore,
The control circuit unit 102 adjusts the voltage Va and the voltage Vb according to the output power Pout of the power amplification unit 101 detected by the power detection unit 104. For example, in FIG.
When 0 dBm, Pout = 25 dBm, η = 30%, I
When M = −35 dBc and Pin = −10 dBm,
Pout = 15 dBm, η = 8%, IM <−60 dBc. In this case, the control circuit unit 102 outputs the output power Pout
Is 15 dBm, the voltage Vb is reduced to improve the power efficiency η.

FIG. 13 is a diagram showing input / output characteristics of the power amplifying unit 101 when the voltage Vb is reduced. FIG.
As can be seen from the graph, when Pin = −9 dBm, Pout =
15 dBm, η = 15%, and IM <−38 dBc.
Thus, when the input power Pin is small, the voltage Vb
Is small, the gain of the power amplification unit 101 hardly changes, but the power efficiency η can be improved about twice.

FIG. 14 is a diagram showing the relationship between the voltage Vb in the power amplifier 101 and the current Ic flowing to the drain voltage input terminal Din. As can be seen from FIG. 14, when the voltage Vb is reduced, Ic is also reduced, and the power efficiency η = (Pout−Pin)
/ (Va × Ic), the power efficiency η of the power amplification unit 101 increases. For example, when the voltage Vb is changed from -0.5V to-
When reduced to 0.8 V, Ic is from 240 mA to 120 m
A. However, if the voltage Vb is -0.8 V or less, Ic becomes too small, so that the distortion IM increases and the output power Pout decreases.

FIG. 15 shows Va in the power amplifying section 101.
FIG. 4 is a diagram showing the relationship between Ic and Ic. As can be seen from FIG. 15, since the amount of change of Ic with respect to the change of voltage Va is small, the effect on power efficiency η of power amplifying section 101 is small even if voltage Va is changed. Here, Ic does not change and voltage Va
When only the voltage Va decreases, the power consumption of the power amplifying unit 101 in the direct current is Va × Ic, and thus decreases as the voltage Va decreases.

However, for controlling the voltage Va, the FET 1
05, and a voltage proportional to the gate voltage of the FET 105 is supplied to the drain voltage input terminal Din. In such a configuration, since the voltage from the battery 106 is constant even when the voltage Va decreases, the power is consumed by the FET 105 by an amount corresponding to the decrease in the voltage Va. Cannot be reduced.
For this reason, it is desirable to reduce the power consumption of the power amplifying section 101 by controlling the voltage Vb.

[0014]

Here, in a radio communication device using the spread spectrum method, when there are many terminals performing radio communication, the radio communication device does not interfere with other radio devices. It is necessary to reduce the output power. A digital mobile phone (PDC: Personal Digital Cellular System) used in the same manner as the above-mentioned frequency spread system.
For example, in a portable telephone or the like, the output voltage is distorted due to the nonlinearity of the input / output characteristics of the power amplifier. The occurrence of the distortion is
Since a signal outside the range of the frequency to be used is output, it is necessary to reduce the noise to other radio equipment so that the noise falls within the standard.

On the other hand, in the method of changing the voltage Va or the voltage Vb as described above, when the power amplifying section 101 reduces the power consumption, the distortion IM when the same input power is used.
Becomes larger. For this reason, in the case of a digital wireless communication device or a base station of the wireless communication device in which the occurrence of distortion is a problem, it is necessary to reduce the power consumption and the input power. This will be described based on the operation of the FET. FIG. 16 shows the FET shown in FIG.
FIG. 4 is a diagram showing load lines when the device is operated at a high frequency.
FIG. 16 shows the static characteristics of the FET, showing the relationship among the gate voltage Vg, the drain voltage Vd, and the drain current Id, and also showing the load curve.

In FIG. 16, the load curve is indicated by an ellipse, and takes a locus of a large ellipse when the power input to the gate of the FET is large. The drain current Id increases with an increase in the gate voltage Vg, and furthermore, the drain current Id
Increases with an increase in the drain voltage Vd up to a certain value of the drain voltage Vd, but when the drain voltage Vd exceeds a certain value, the increase in the drain current Id decreases. From such a relationship between the gate voltage Vg and the drain current Id, the transconductance gm is defined by the following equation (1). gm = ΔId / ΔVg (1) That is, the larger the gm, the greater the increase in the drain current Id due to the increase in the gate voltage Vg, and the better the characteristics of the FET. In the above equation (1), ΔId
Is the change amount of the drain current Id, and ΔVg is the gate voltage Vg
Indicates the amount of change.

The transconductance gm shown in the above equation (1) has a relation of gm∝1 / Rs with respect to the resistance Rs between the gate and the source in the FET. The resistance Rs is F
The value of the resistor Rs cannot be changed after the power amplifying unit 101 is configured because it is determined by the process parameters when the ET is manufactured. That is, FIG.
The static characteristics of the FET indicated by
1 cannot be changed when used. FIG.
FIG. 6 shows a load curve when Vd = 3 V and Vg = -0.5 V. The voltage Va at the drain voltage input terminal Din becomes the drain voltage Vd of the FET, and the voltage Vb at the gate voltage input terminal Gin is This is a value when the gate voltage Vg of the FET is set.

As described above, since the static characteristics of the FET cannot be changed, the position of the load curve is changed by changing the voltage Va or the voltage Vb. FIG. 17 shows that the gate voltage Vg of the FET in FIG. 16 is changed from -0.5 V to -0.8.
FIG. 18 is a diagram showing a load curve when V is set to V. FIG.
The drain voltage Vd of the FET in FIG.
FIG. 7 is a diagram showing a load curve when V is set. 17 and 18, it can be seen that the load curve when the power input to the gate of the FET is large is distorted as compared with FIG. From this, in the power amplification unit 101,
When the voltage Va or the voltage Vb is changed, such a distortion is output to the output power Pout when the input power Pin is increased.

In FIG. 16, if the FET is used at a bias point where the transconductance gm is small,
Since the gain of the FE becomes small, the FE
It may be used at a bias point where the transconductance gm of T changes greatly. However, in this case, in FIG. 16, for example, the drain voltage Vd is set to 1 V or less, and the gate voltage Vg is set to −
The voltage must be between 1.2 V and -0.8 V. If the drain voltage Vd and the gate voltage Vg deviate even a little, the characteristics greatly change. Therefore, it is very difficult to control the transconductance gm. However, it was difficult to use at a bias point where the value greatly changed. As described above, in FIG. 11, if Va or Vb of the power amplifying unit 101 is changed, it is necessary to reduce the input power Pin, and it becomes necessary to control the output power of the IF circuit unit 103. It could not be operated in the most efficient state.

On the other hand, Japanese Patent Application Laid-Open No. 2-303206 discloses a high frequency power amplifier using a dual gate type field effect transistor. JP-A-2-3032
In Japanese Patent Application Publication No. 06-2006, a high-frequency signal is input to a first gate that is a source-side gate electrode of a dual-gate field-effect transistor that forms a power amplifier, and a DC signal is supplied to a second gate that is a drain-side gate electrode. Signal voltage is being applied. Here, a dual gate type field effect transistor is composed of a first FET having a first gate, and a second FET having a second gate.
When divided into a second FET constituted by a gate, the gain of the second FET can be changed by performing the same operation as that of the variable resistor controlled by the voltage of the second gate.

However, in such a configuration, when the voltage of the second gate is changed, the drain voltage of the first FET can be changed, but the source resistance of the first FET cannot be changed. Thus, although the gain can be changed by the control signal voltage which is a DC signal, the bias point of the first gate to which the high-frequency signal is input cannot be changed, so that the distortion cannot be reduced. is there.

Japanese Unexamined Patent Publications Nos. 2-125473 and 6-252396 each disclose a dual-gate type FET in which distortion of the FET itself is reduced. In Japanese Patent Application Laid-Open No. 2-125473, a GaAs dual-gate FET having a structure in which a substrate at the drain end of a gate is carved is disclosed. A gate type FET is disclosed.

In Japanese Patent Application Laid-Open No. 2-125473, it is considered that a high-frequency signal is input to the first gate because the substrate in contact with the first gate, which is the gate electrode on the source side, is carved. Generally, when the gate length is shortened, FE
Since the gain of T is improved, the gate length of the first gate to which the high-frequency signal is input is shortened. In addition, Japanese Unexamined Patent Publication No.
JP-A-252396 assumes that a high-frequency signal is input to the first gate electrode. from these things,
When such a dual-gate FET is used in a high-frequency power amplifier, the same problem as in the case of Japanese Patent Application Laid-Open No. 2-303206 can be considered.

Further, in the 1996 IEICE General Conference C-83, a dual gate F
Instead of ET, a cascade FET constructed by connecting the drain of a common-source FET with a spiral inductor inserted between the drain and source and the source of an amplification FET
2 shows an amplifier that performs gain control by changing the gate voltage of the common-source FET. A high-frequency signal is input to the gate of the amplifying FET, and a DC signal is input to the gate of the common-source FET. However, in the amplifier having such a configuration, the high-frequency signal flows through the common-source FET, but the DC signal is grounded by the spiral inductor.

For this reason, in the DC signal, the amplifying F
The source potential of ET becomes the ground potential, and the source-grounded FET
The source potential of the amplifying FET does not change even if the gate potential VCONT is changed. That is, in order to change the drain current of the amplifying FET, it is necessary to change the gate potential (VGG1 or VGG2) of the amplifying FET. When the gate potential of the common-source FET is changed in this manner, the common-source FET operates as a source resistance in the case of a high-frequency signal, but is bypassed by a spiral inductor in the case of a DC signal.

For this reason, although the gain with respect to the high-frequency signal is reduced, there is a problem that the power consumption of the power amplifier cannot be changed and the power consumption cannot be reduced. Furthermore, since a spiral inductor is connected between the drain and the source of the common-source FET, the number of components increases, and the cost increases because the dual-gate FET cannot be used and the chip area increases. There is.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a power amplifier capable of reducing power consumption without increasing distortion and improving power efficiency. A high frequency circuit having a circuit and a dual gate F used for the power amplifier circuit
It is an object of the present invention to improve the performance of the ET, particularly to reduce the size and the efficiency.

[0028]

A dual-gate FET according to the present invention is a dual-gate FET for amplifying a high-frequency signal, wherein the gate electrode of the second gate, which is the source-side gate, has a gate length of the drain side. The gate electrode is formed so as to be shorter than the gate length of the gate electrode forming the first gate.

The dual gate FE according to the present invention
In claim 1, T is the gate length of the gate electrode forming the first gate is 0.7 μm to 1.5 μm, and the gate length of the gate electrode forming the second gate is 0.2 μm to 0.2 μm.
6 μm.

Further, the dual gate FE according to the present invention
T is a dual-gate FET that amplifies a high-frequency signal, in which a conductive layer is formed by dividing the concentration of electrons injected into the semiconductor substrate into three or more types, and the conductive layer is a first electrode serving as a drain-side gate electrode. The lower part of the second gate electrode, which is the gate electrode and the gate electrode on the source side, is formed so as to have the lowest electron concentration, and the lower part of the drain electrode and the source electrode has the highest electron concentration. The formed region with the lowest electron concentration is formed adjacent to the region where the source electrode is formed and the region where the electron concentration is highest formed on the first gate electrode side.

Further, the dual gate FE according to the present invention
In claim 3, T is the conductive layer according to claim 3, wherein the region having the lowest electron concentration formed under the first gate electrode is the region where the drain electrode is formed and the region where the second gate electrode is formed. It is formed so as to be connected to a region having the highest electron concentration adjacent to the first gate electrode side through a region having an intermediate electron concentration.

Further, the dual gate FE according to the present invention
In the dual-gate FET that amplifies a high-frequency signal, the thickness of the conductive layer formed on the semiconductor substrate is set to be greater than that of the region on which the first gate electrode, which is the drain-side gate electrode, is formed. Is formed such that the region where the second gate electrode is formed is thinner.

Further, the high-frequency circuit according to the present invention is a high-frequency circuit having at least one power amplifying circuit using at least one dual-gate FET for amplifying a high-frequency signal. A high-frequency signal is input to the gate,
A DC bias voltage is input to a second gate which is a source side gate of the dual gate FET, and the output power of the power amplifier circuit is controlled by the DC bias voltage.

A high-frequency circuit according to the present invention is a high-frequency circuit including a transmission circuit in a wireless communication device such as a portable telephone, and a power amplifier circuit having at least one dual-gate FET for amplifying a high-frequency signal to be transmitted. A transmitting and receiving unit that transmits a high-frequency signal amplified by the power amplifier circuit and receives an external high-frequency signal,
A power detection unit that detects the power of the signal received by the transmission / reception unit, converts the detected power into a DC voltage, and outputs the DC voltage. The power amplification circuit is a drain-side gate of a dual-gate FET. A high-frequency signal to be transmitted is input to the first gate, and a DC voltage output from the power detection unit is input to a second gate, which is a source-side gate in the dual-gate FET, and output power is controlled by the DC voltage. Is what you do.

A high-frequency circuit according to the present invention is a high-frequency circuit comprising a receiving circuit in a wireless communication device such as a mobile phone, comprising: a receiving section for receiving an external high-frequency signal; a high-frequency signal received by the receiving section; Amplifying, a power amplifier circuit having at least one dual gate FET, and detecting the power of the signal received by the receiving unit,
A power detection unit that converts the detected power into a DC voltage and outputs the DC voltage.
The high-frequency signal received by the receiving unit is input to a first gate, which is a drain-side gate at T, and a DC voltage output from the power detection unit is applied to a second gate, which is a source-side gate of a dual-gate FET. Is input, and the output power is controlled by the DC voltage.

In the high-frequency circuit according to the present invention, the electric power generated in accordance with a change in a DC bias voltage input to the second gate of the dual-gate FET according to any one of claims 6 to 8. An impedance adjusting circuit is further provided which cancels out and makes constant a change in impedance of each of the first gate of the dual-gate FET forming the input section of the amplifier circuit and the output section of the power amplifier circuit.

Further, in the high frequency circuit according to the present invention, the dual gate FET according to any one of claims 6 to 9, wherein the gate length of the gate electrode forming the second gate is equal to that of the gate electrode forming the first gate. It is formed to be shorter than the gate length.

In the high frequency circuit according to the present invention, the gate electrode of the first gate has a gate length of 0.7 μm to 1.5 μm, and the gate electrode of the second gate has a gate length of 0.7 μm to 1.5 μm. The length is from 0.2 μm to 0.6 μm.

Further, in the high frequency circuit according to the present invention, in any one of the sixth to ninth aspects, in the dual gate FET, a conductive layer is formed by dividing the concentration of electrons injected onto the semiconductor substrate into three or more types. The conductive layer is formed such that the lower part of the first gate electrode and the second gate electrode has the lowest electron concentration, the lower part of the drain electrode and the source electrode has the highest electron concentration, and the lower part of the second gate electrode. The region having the lowest electron concentration is formed adjacent to the region where the source electrode is formed and the region where the electron concentration is highest formed on the first gate electrode side.

In the high-frequency circuit according to the present invention, in the twelfth aspect, the conductive layer is formed such that a region having the lowest electron concentration formed under the first gate electrode is a region where a drain electrode is formed, and It is formed so as to be connected to a region where the second gate electrode is formed and a region having the highest electron concentration adjacent to the first gate electrode side via a region having an intermediate electron concentration.

Further, in the high frequency circuit according to the present invention, in any one of the sixth to ninth aspects, the dual gate FET may have a thickness of a conductive layer formed on a semiconductor substrate.
The region where the second gate electrode is formed is smaller than the region where the first gate electrode is formed.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a schematic circuit diagram illustrating an example of a high-frequency circuit according to Embodiment 1 of the present invention. FIG. 1 shows a power amplifier circuit used as a transmission circuit in a wireless communication device such as a mobile phone as an example.

In FIG. 1, a power amplifier circuit 1 includes two dual-gate field effect transistors (hereinafter, referred to as dual-gate FETs) 2 and 3, matching circuits 4 to 8 for matching impedances, and resistors 9 to 12. It is formed with. The drain of the dual gate FET 2 is a matching circuit 5
Is connected to the drain voltage input terminal D1 to which the drain voltage is input, and the source is grounded. The first gate electrode on the drain side of the dual gate FET 2
The gate is connected to an input terminal IN to which a high-frequency signal is input via a matching circuit 4, and the first terminal is connected via a resistor 9.
It is connected to a first gate input terminal G1 to which a gate signal to the gate is input. Also, dual gate FET2
The second gate, which is the gate electrode on the source side of
To the second gate input terminal G2 to which a gate voltage to the second gate is input.

The drain of the dual gate FET 2 is further connected to a first gate, which is the gate electrode on the drain side of the dual gate FET 3, via a matching circuit 6.
The drain of the dual gate FET 3 is connected via a matching circuit 7 to a drain voltage input terminal D to which a drain voltage is input.
2 and the source is grounded. The first gate of the dual gate FET 3 is further connected to the first gate via the resistor 11.
It is connected to the gate input terminal G1. The second gate, which is the source-side gate electrode of the dual-gate FET 3, is connected to the second gate input terminal G2 via the resistor 12. The drain of the dual gate FET 3 is further connected to the output terminal OUT via the matching circuit 8.

In the above-described configuration, a predetermined DC voltage is input to the first gate input terminal G1, and the voltage of the DC signal input to the second gate input terminal G2 is changed, so that the dual gate FETs 2 and 3 Change static characteristics. Further, a predetermined DC voltage Vd is input to the drain voltage input terminals D1 and D2, respectively. 2 and 3 are diagrams showing load lines when the dual gate FET 2 shown in FIG. 1 is operated at a high frequency. The characteristics of the dual-gate FET 3 are the same as those of the dual-gate FET 2
Therefore, the description is omitted.

FIG. 2 shows that the gate voltage Vg2 of the second gate is 0.5 V, and FIG. 3 shows that the gate voltage Vg2 of the second gate is -0.5 V.
5 shows the static characteristics of the dual-gate FET 2 when the voltage is 5 V, and shows the gate voltage V of the first gate.
g1, the relationship between the drain voltage Vd and the drain current Id, and the load curve are shown. 2 and 3
, The drain voltage of the dual gate FET 2 and a predetermined DC voltage inputted to the drain voltage input terminal D 1
The case where the voltage is the same is shown as an example.

FIG. 4 is a diagram showing an equivalent circuit of the dual gate FET 2, and it can be seen that the dual gate FET 2 is formed by the first FET 15 and the second FET 16. In FIG. 4, the source of the first FET 15 and the drain of the second FET 16 are connected, and the first FET 15
, The drain forms the drain of the dual-gate FET2, and the gate forms the first gate of the dual-gate FET2. In the second FET 16, the source forms the source of the dual-gate FET 2, and the gate forms the second gate of the dual-gate FET 2.

As described above, the second FET 16 is connected to the first FE
The source resistance Rs of T15 forms the source resistance Rs by changing the gate voltage Vg2 of the second gate, that is, the transconductance gm changes. When the transconductance gm changes, the dual gate F
The gain of ET2 changes, and the gain of power amplifier circuit 1 changes. Therefore, in the power amplifier circuit 1, the gate voltage V
By reducing g2, output power Pout can be reduced even if input power Pin is constant. FIG.
In FIG. 3 and FIG. 3, the gate voltage Vg2 is changed from 0.5 V to
When the voltage is set to 5 V, the size of the ellipse of the load curve decreases, but the deformation of the ellipse is small. For this reason, in the power amplifier circuit 1, even if the input power Pin is large, the distortion of the output power Pout is reduced.

Next, FIG. 5 is a schematic block diagram showing an example of a transmission circuit section in a wireless communication device such as a portable telephone using the power amplifying circuit 1 shown in FIG. Frequency Division Multiple Access (FDMA)
Multiple Access) and FDD. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here.

In FIG. 5, the input terminal IN of the power amplifier circuit 1 is connected to the IF circuit 21 and the first gate input terminal G
1 is grounded. Further, the output terminal OUT of the power amplification circuit 1 is connected to the signal distributor 22, and the antenna 23 is connected to the signal distributor 22. Further, the signal distributor 22 is connected to a receiving power amplifier circuit (not shown) via a power detector 24. The power detector 24 is connected to the input of the inverter circuit 25,
The output of 5 is connected to the second gate input terminal G2 of the power amplifier circuit 1. Note that the signal distributor 22 and the antenna 2
Reference numeral 3 denotes a transmission / reception unit, and the power detector 24 and the inverter circuit 25 form a power detection unit.

The IF circuit 21 is a circuit for frequency-converting a signal to be transmitted from an intermediate frequency to a high frequency.
The high-frequency transmission signal output from 1 is amplified by the power amplifier circuit 1 and then output to the signal distributor 22. The signal distributor 22 transmits the high-frequency transmission signal output from the output terminal OUT of the power amplification circuit 1 from the antenna 23, and outputs the signal received from the antenna 23 to the reception power amplification circuit. At this time, the signal distributor 22 receives a signal having a frequency different from the frequency of the transmission signal. For example, the reception frequency is 880 MHz, the transmission frequency is 940 MHz, and the signal output from the power amplification circuit 1 is output. The high frequency signal is not output to the receiving power amplifier circuit.

In the above configuration, the antenna 23
When the signal received at is transmitted from the signal distributor 22 to the receiving power amplifier circuit, the power detector 24 detects the power. The power detector 24 converts the detected power into a DC signal and outputs the DC signal to an input of an inverter circuit 25.
After the signal level is inverted by the inverter circuit 25, the signal is output to the second gate input terminal G2 of the power amplification circuit 1.

Since the power detector 24 outputs a DC signal of a higher voltage as the detected power is larger, when the power detector 24 outputs a voltage higher than the threshold value of the inverter circuit 25, The output voltage of the inverter circuit 25 decreases. Therefore, when the received signal is larger than the predetermined power, the second gate input terminal G2 of the power amplification circuit 1
The voltage input to is reduced. As described above, when the power of the received signal is large, since the wireless communication device is close to the base station, the base station transmits the transmission signal from the wireless communication device even if the power of the transmission signal from the wireless communication device is reduced. Can be received. Therefore, the power of the received signal is detected by the power detector 24, and the transmission power of the wireless communication device is controlled according to the detected power.

In the conventional radio communication device, the received power at the base station is received using the data of the signal transmitted from the base station, and the power of the input signal to the power amplifier circuit is reduced according to the data of the signal. And controlling the bias conditions. On the other hand, with the above, the power consumption of the power amplifier circuit 1 can be reduced, the power consumption of the wireless communication device can be reduced, and the configuration of the wireless communication device is simplified. be able to.

In the description of the first embodiment,
The power amplifying circuit 1 is configured to perform two-stage amplification by the dual gate FETs 2 and 3. However, this is an example, and the present invention is not limited to this. A configuration for performing one-stage amplification may be used. FIG. 6 shows a dual gate FET 2
FIG. 1 is a schematic block diagram showing an example of a receiving circuit unit in a wireless communication device such as a mobile phone using a power amplification circuit 1 configured to perform one-stage amplification according to FIG. The receiving circuit unit shown in FIG. 6 employs a frequency division multiple access system as in FIG.
The case where it is used for a wireless communication device of the DD system is shown as an example. In FIG. 6, the same components as those in FIGS. 1 and 5 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 6, the power amplifier circuit 31 includes a dual gate FET 2, matching circuits 4 to 6, and resistors 9 and 10.
And the output of the matching circuit 6 is
1 output terminal OUT. The signal distributor 22
The input terminal IN of the power amplification circuit 31 via the power detector 24
It is connected to the. The power detector 24 is connected to the input of the inverter circuit 25, and the output of the inverter circuit 25 is
It is connected to the second gate input terminal G2 of the power amplification circuit 31. The output terminal OUT of the power amplification circuit 31 is connected to an IF circuit (not shown). The IF circuit is a circuit that converts a received and amplified signal from a high frequency to an intermediate frequency. In this case, the signal distributor 22 and the antenna 23 form a receiving unit.

In the above configuration, when the wireless communication device is used near the base station, the power amplifying circuit 31 may be saturated because the wireless power from the base station is large. Therefore, when the signal received by the antenna 23 is sent from the signal distributor 22 to the power amplifying circuit 31, the power is detected by the power detector 24. Power detector 24
Converts the detected power into a DC signal and outputs it to the input of the inverter circuit 25, and the DC signal is
After the signal level is inverted at the second step, the second
Output to the gate input terminal G2.

As in the case of FIG. 5, the power detector 24
Since the higher the detected power, the higher the DC signal is output, if the power detector 24 outputs a voltage higher than the threshold value of the inverter circuit 25, the output voltage of the inverter circuit 25 decreases. Therefore, when the received signal is larger than the predetermined power, the voltage input to the second gate input terminal G2 of the power amplification circuit 31 decreases. As described above, when the wireless communication device is located near the base station, the power of the received signal is large and the power of the power amplification circuit 3 is increased.
1 may saturate. For this reason, the power of the received signal is detected by the power detector 24, and the gain of the power amplifier circuit 31 is controlled according to the detected power. Therefore, when the power of the received signal is higher than the desired power, the gain of the power amplifier circuit 31 is reduced, and the deterioration of the characteristics of the power amplifier circuit 31 due to the saturation of the power amplifier circuit 31 can be prevented.

In FIG. 6, the power detector 24 is provided on the input side of the power amplifier circuit 31. However, in the time series of the received signal, the power detector 24 first has a power detection signal before a signal necessary for communication. In this case, in order to prevent signal deterioration due to the power detector 24, the power detector 24
May be performed, and even in such a case, the same characteristics as those of the power amplifier circuit 31 shown in FIG. 6 can be obtained. In this case, the signal for power detection, that is, the signal output from the inverter circuit 25 is not a problem in performing wireless communication even if the signal is saturated and distorted.

As described above, the high-frequency circuit according to the first embodiment includes the power amplifying circuit for amplifying the power of the high-frequency signal, and the power amplifying circuit is connected to the first gate on the drain side of the high-frequency signal to be amplified. It was formed using a dual-gate FET that inputs a signal and a predetermined DC voltage and inputs a variable DC voltage to the second gate on the source side. Thus, the static characteristics of the dual gate FET can be changed according to the DC voltage input to the second gate, and the gain of the power amplifier circuit can be changed. Therefore, power consumption can be reduced without increasing distortion, and power efficiency can be improved.

Embodiment 2 In the first embodiment, the gate voltage V input to the second gate input terminal G2
g2 was changed to change the gain of the power amplifier circuit.
In this way, the input and output impedances of the dual gate FETs 2 and 3 change. The change causes a change in gain in the characteristics of the power amplifier circuit.
On the other hand, when the impedance of the power amplifier circuit changes, the impedance of a circuit connected before and after the power amplifier circuit shifts, so that signal reflection may occur.

This does not pose a problem in an amplifier used in a power amplifier circuit of a cellular phone or the like because the input / output matching range is widened, but in a power amplifier circuit used at a high frequency of 5 GHz or more, Since the input / output matching is narrow band matching to improve the performance of the power amplifying circuit, there may be a problem with the matching misalignment. For this reason, even when the gate voltage Vg2 of the second gate is changed, a configuration in which the input impedance and the output impedance of the power amplifier circuit do not change according to the second embodiment of the present invention is described.
And

FIG. 7 is a schematic circuit diagram showing an example of the high-frequency circuit according to the second embodiment. In FIG. 7,
1 shows an example of a power amplifying circuit used for a transmission circuit in a wireless communication device such as a mobile phone. The same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here. Only the differences will be described. FIG. 1 in FIG.
1 is that an impedance adjusting circuit 45 including single-gate FETs 41 to 43 and a resistor 44 is added to the power amplifying circuit 1 of FIG.
The power amplifier circuit 1 of FIG.

In FIG. 7, the power amplifier circuit 40 includes dual gate FETs 2 and 3, matching circuits 4 to 8 and resistors 9 to
12, an impedance adjustment circuit 45 including FETs 41 to 43 and a resistor 44 is formed. FET4
The gate of 1 is connected to the second gate input terminal G2, and the source of the FET 41 is grounded. FET41
Is connected to the gate of the FET 43 via a resistor 44, and is connected to the drain voltage input terminal D1 via the resistor 44. F
In ET42, the drain is dual gate FET2
, And the source is grounded. In the FET 43, the drain is a dual gate F
The source is connected to the drain of ET3, and the source is grounded.

In the above configuration, when the voltage input to the second gate input terminal G2 decreases, the FET 42
, And 43, and the on-resistance of FETs 42 and 43 decreases. On the other hand, if the voltage input to the second gate input terminal G2 is reduced to reduce the output power of the power amplifying circuit 40, the input impedance of the dual-gate FET 2 increases, but the on-resistance of the FET 42 decreases. The input impedance of the power amplification circuit 40 becomes constant. When the voltage input to the second gate input terminal G2 is reduced, the output impedance of the dual-gate FET 3 increases, but the on-resistance of the FET 43 decreases, so that the output impedance of the power amplifier circuit 40 becomes constant. .

As described above, the high-frequency circuit according to the second embodiment has the effect of changing the input / output impedance caused by changing the voltage input to the second gate input terminal G2 in addition to the effect of the first embodiment. It can be used for a power amplifier circuit used at a high frequency of 5 GHz or more, because it can be kept constant and a deviation of matching with a circuit connected to an input and an output can be eliminated.

Embodiment 3 In the dual gate FETs 2 and 3 used in the first and second embodiments, the gate lengths of the first gate and the second gate may be changed, and such a configuration is used in the third embodiment of the present invention. And A schematic circuit diagram showing an example of the high-frequency circuit according to the third embodiment is the same as FIG. 1 or FIG.

FIG. 8 is a schematic sectional view showing a structural example of a dual gate FET 2 used in a high frequency circuit according to the third embodiment of the present invention. In addition, dual gate FE
The structure of T3 is the same as that of the dual gate FET2, and the description thereof is omitted. 8, a drain electrode 53, a first gate electrode 54, a second gate electrode 55, and a source electrode 56 are formed on an n-layer 52 formed by implanting Si ions into a gallium arsenide substrate 51.

The gate length Lg2 of the second gate electrode 55 is
The gate electrode 54 is formed shorter than the gate length Lg1. Specifically, the gate length Lg1 of the first gate electrode 54 is set to 0.7 μm to 1.5 μm, and the gate length Lg2 of the second gate electrode 55 is set to 0.2 μm to 0.6 μm. The gate length Lg1 is set to 1 μm, and the gate length Lg2 of the second gate electrode 55 is set to 0.4 μm. This is F
This is because if the gate length of the ET is too short, the gain is greatly reduced. In the FET, when the gate length is shortened, the pinch-off voltage of the FET increases and the channel resistance under the gate decreases, so that the drain-source resistance decreases.

Here, the dual gate FET 2 is an FET
In order to operate as an amplifier, it is necessary to increase the drain breakdown voltage. Therefore, dual gate FET
2, the gate length Lg1 of the first gate electrode 54 is
The gate electrode 55 is formed to be longer than the gate length Lg2. For example, in the final stage of an amplifier circuit operating at a power supply voltage of 3 V, the drain withstand voltage needs to be at least twice the power supply voltage, and the gate length Lg1 needs to be 0.7 μm or more. Therefore, the gate length Lg1 is set to 1 μm. . On the other hand, the second gate in the dual-gate FET 2 does not need a drain breakdown voltage, so that the gate length Lg2 can be reduced.

As described above, in the high-frequency circuit according to the third embodiment of the present invention, in the dual-gate FETs 2 and 3, as shown in FIG.
Since the gate length Lg2 of the second gate electrode 55 is shorter than the gate length Lg1 of the first gate electrode 54, the variable range of the resistance value of the external source resistance is increased because the gate length Lg2 of the second gate electrode 55 functions as the source resistance Rs of the ET15. Thus, the variable width of the static characteristics of the dual gate FET that changes according to the DC voltage input to the second gate can be increased. That is, the size of the dual gate FET can be reduced, and the variable range of the gain in the power amplifier circuit can be increased.

Further, the drain of the second FET 16
The resistance between the first gate and the source in the dual gate FET 2 when the resistance between the sources is minimized is the first resistance.
The gate length of the gate electrode 54 and the second gate electrode 55 can be reduced as compared with the case where the gate lengths are the same.
That is, when the output power of the dual-gate FET 2 is the largest, the drain-source resistance of the second FET 16 is preferably as small as possible, so that the power efficiency of the power amplifier circuit can be increased.

Embodiment 4 As in the third embodiment, when a fine pattern in which the gate length Lg2 of the second gate electrode 55 is 0.4 μm cannot be formed, the concentration of Si ions implanted into the gallium arsenide substrate is changed as shown in FIG. A fourth embodiment of the present invention will be described in which characteristics similar to those of the dual gate FET 2 are obtained. A schematic circuit diagram showing an example of the high-frequency circuit according to the fourth embodiment is shown in FIG.
It is the same as FIG. 1 or FIG.

FIG. 9 is a schematic cross-sectional view showing a structural example of a dual gate FET 2 used for a high frequency circuit according to the fourth embodiment of the present invention. In addition, dual gate FE
The structure of T3 is the same as that of the dual gate FET2, and the description thereof is omitted. In FIG. 9, the concentration of Si ions implanted into the gallium arsenide substrate 61 is changed in three steps to obtain n ⁺
Layer, an n1 layer and an n layer. The n-layer has the lowest concentration of Si ions and is a channel layer for setting a pinch-off voltage of the dual-gate FET 2. A first gate electrode 62 and a second gate electrode 63 are formed on the n-layer. The n ⁺ layer has a high Si concentration so as to make ohmic contact with the drain electrode 64 and the source electrode 65.
The n1 layer is a layer having an Si ion concentration between the n ⁺ layer and the n layer.

The first gate electrode 62 is formed on the n-layer
A gate electrode 63 is formed on the n-layer 67, and a drain electrode 64 is formed on the n ⁺ layer 68 on the source electrode 6
5 is formed on the n ⁺ layer 69. n layer 67 and n ⁺ layer 6
9 is adjacent to the first gate electrode side of the n-layer 67.
⁺ Layer 70 is adjacent. An n1 layer 71 is formed between n layer 66 and n ⁺ layer 68, and n1 layer
The n1 layer 72 is formed so as to be sandwiched between the n ⁺ layer 6 and the n ⁺ layer 70. The n layers 66 and 67, the n ⁺ layers 68 to 70, and the n1 layers 71 and 72 form a conductive layer.

In the above configuration, when the gate electrode is brought into contact with the n ⁺ layer, the gate breakdown voltage is reduced, and the resistance between the ohmic contact electrode and the gate electrode is reduced. From this, in the second gate electrode 63, since the n ⁺ layers 69 and 70 are close to each other, the FET of the second gate electrode 63, that is, the second FE shown in FIG.
As the resistance between the drain and source of T16 decreases, the pinch-off voltage increases. On the other hand, the FET of the first gate electrode 62, that is, the first FET 15 shown in FIG.
Since it is necessary to increase the withstand voltage between the drain and the source in n, the n in which the first gate electrode 62 is formed
Layer 66 should not contact the heavily doped n ⁺ layer. Accordingly, between the n layer 66 and the n ⁺ layer 68 n1 layer 71 is formed, n1 layer 72 between the n layer 66 and the n ⁺ layer 70 is formed, the n ⁺ layer 68 and n ⁺ The layer 70 is prevented from approaching.

As described above, in the high-frequency circuit according to the fourth embodiment of the present invention, in the dual gate FETs 2 and 3, the concentration of Si ions implanted into the gallium arsenide substrate 61 is changed in three stages to form the n ⁺ layer and the n1 layer. and then n-layer to form structures respectively, into contact across the n layer 67 in which the second gate electrode 63 is formed, to form a high-concentration n ⁺ layer 69 and n ⁺ layer 70, respectively, the n ⁺ layer A source electrode 65 was formed on 69. Further, an n1 layer 71 is formed between the n layer 66 on which the first gate electrode 62 is formed and the n ⁺ layer 68 on which the drain electrode 64 is formed, and an n1 layer 71 is formed between the n layer 66 and the n ⁺ layer 70. An n1 layer 72 is formed, and an n ⁺ layer 68 and an n ⁺ layer 7 are formed.
0 is kept away. By doing so, the same effect as in the third embodiment can be obtained, and also in the case where a fine pattern for reducing the gate length to 0.4 μm or less cannot be formed, the same as in the third embodiment. The effect of can be obtained.

Embodiment 5 FIG. In the fourth embodiment, the same characteristics as those of the dual gate FET 2 shown in FIG. 8 are obtained by changing the concentration of Si ions implanted into the gallium arsenide substrate. By changing the depth of the portion where each electrode is formed in the n-layer formed on the gallium arsenide substrate, the same characteristics as the dual gate FET 2 shown in FIG. This is referred to as a fifth embodiment of the present invention. A schematic circuit diagram showing an example of the high-frequency circuit according to the fifth embodiment is the same as FIG. 1 or FIG.

FIG. 10 is a schematic cross-sectional view showing a structural example of a dual gate FET 2 used for a high frequency circuit according to the fifth embodiment of the present invention. The dual gate F
The structure of ET3 is the same as that of the dual-gate FET2, and the description thereof is omitted. In FIG. 10, an n layer 82 is formed on a gallium arsenide substrate 81 by implanting Si ions into the gallium arsenide substrate 81 or by epitaxial growth. The thickness of the n-layer 82 is not uniform.
The gate electrode 83 is formed at a portion where the n-layer 82 is dug by 1000 ° or more, and the second gate electrode 84 is formed at a portion where the dug-down amount of the n-layer 82 is 200 ° or less. In addition, the drain electrode 85 and the source electrode 86 are
Are formed in the portions that are not dug out. Note that the n layer 82 forms a conductive layer.

In the above-described configuration, when the depth of the n-layer 82 in the portion where the first gate electrode 83 is formed is increased, the FET of the first gate electrode 83, that is, the first FET 15 shown in FIG. , The channel resistance increases, but the withstand voltage between the drain and the source of the first FET 15 increases. On the contrary,
When the amount of digging of the n-layer 82 in the portion where the second gate electrode 84 is formed is reduced, the FE of the second gate electrode 84 is reduced.
T, that is, the channel resistance of the second FET 16 shown in FIG. 4 is reduced, and the withstand voltage between the drain and the source is also reduced.

As described above, in the high frequency circuit according to the fifth embodiment of the present invention, in the dual gate FETs 2 and 3, the portion of the n-layer formed on the gallium arsenide substrate 81 where the first gate electrode 83 is formed and The portions where the second gate electrodes 84 are formed are dug respectively,
The depth of the portion where the gate electrode 83 is formed is made larger than the depth of the portion where the second gate electrode 84 is formed. By doing so, the same effect as in the third embodiment can be obtained, and the gate length can be reduced to 0.3.
The same effect as in the third embodiment can be obtained even in a case where a fine pattern for reducing the thickness to 4 μm or less cannot be formed. In addition, F formed by ion implantation
The present invention can be used not only for ET but also for a power amplifier circuit using a high electron mobility transistor (HEMT) using an epitaxial gallium arsenide substrate.

[0082]

The dual gate FET according to claim 1
By making the gate length of the second gate electrode shorter than the gate length of the first gate electrode, the variable width of the static characteristics of the dual gate FET when a DC voltage is input to the second gate can be increased. In addition, the size of the dual gate FET can be reduced. That is, when such a dual gate FET is used in an amplifier circuit, the variable range of the gain in the amplifier circuit can be increased and the size can be reduced. Furthermore, since the resistance between the first gate and the source can be reduced, the power efficiency can be increased when used in a power amplifier circuit.

The dual gate FET according to claim 2 is
In claim 1, specifically, the gate length of the gate electrode forming the first gate is from 0.7 μm to 1.5 μm, and the gate length of the gate electrode forming the second gate is from 0.2 μm to 1.5 μm.
Since the thickness is 0.6 μm, the drain withstand voltage can be increased, and a significant decrease in gain due to an excessively short gate length can be prevented.

The dual gate FET according to claim 3 is
A structure in which a conductive layer is formed by changing the concentration of Si ions implanted into the semiconductor substrate in three stages, and in the conductive layer, a region having the lowest electron concentration formed under the second gate electrode is a source electrode. It is formed so as to be adjacent to the formed region having the highest electron concentration and the region having the highest electron concentration formed on the first gate electrode side. From this,
Even when a fine pattern for shortening the gate length cannot be formed, the variable width of the static characteristics of the dual-gate FET when a DC voltage is input to the second gate can be increased. That is, when such a dual-gate FET is used in an amplifier circuit, the variable range of the gain in the amplifier circuit can be increased.
Furthermore, since the resistance between the first gate and the source can be reduced, the power efficiency can be increased when used in a power amplifier circuit.

The dual gate FET according to claim 4 is
4. The conductive layer according to claim 3, wherein the region having the lowest electron concentration formed under the first gate electrode includes a region where the drain electrode is formed, a region where the second gate electrode is formed, and the first gate electrode. It is formed so as to be connected to the region having the highest electron concentration adjacent to the side through the region having the intermediate electron concentration. For this reason, the withstand voltage of the drain of the dual gate FET can be increased.

The dual gate FET according to claim 5 is
The thickness of the conductive layer formed on the semiconductor substrate is made smaller in the region where the second gate electrode is formed than in the region where the first gate electrode is formed. As a result, the drain withstand voltage can be increased, and the static characteristics of the dual-gate FET when a DC voltage is input to the second gate can be obtained even when a fine pattern for shortening the gate length cannot be formed. The variable width can be increased. That is, when such a dual-gate FET is used in an amplifier circuit, the variable range of the gain in the amplifier circuit can be increased. Also, the first
Since the resistance between the gate and the source can be reduced, power efficiency can be increased when used in a power amplifier circuit. Further, the present invention can be used not only for an FET formed by ion implantation but also for an amplifier circuit using a high electron mobility transistor using an epitaxial gallium arsenide substrate.

The high-frequency circuit according to claim 6 includes a power amplifier circuit for amplifying the power of the high-frequency signal, and the power amplifier circuit transmits a high-frequency signal for power amplification to a drain-side first gate and a predetermined DC voltage. Input and the second on the source side
Dual gate F for inputting variable DC voltage to gate
Formed using ET. Accordingly, in the power amplifier circuit, the static characteristics of the dual-gate FET can be changed according to the DC voltage input to the second gate, and the gain of the power amplifier circuit can be changed. In addition, cost can be reduced, power consumption can be reduced without increasing distortion, and power efficiency can be improved.

The high-frequency circuit according to claim 7 includes a power amplifier circuit having at least one dual-gate FET for amplifying a high-frequency signal to be transmitted, and the power amplifier circuit is a drain-side gate of the dual-gate FET. The high-frequency signal to be transmitted to the first gate is input, and the DC voltage output from the power detection unit after converting the power of the received signal is input to the second gate, which is the source-side gate of the dual-gate FET. The output power is controlled by the DC voltage. From this, in the power amplifier circuit, the static characteristics of the dual gate FET can be changed according to the DC voltage input to the second gate,
Since the gain of the power amplifying circuit can be changed, miniaturization and cost reduction can be achieved with a simple configuration, power consumption can be reduced without increasing distortion, and power efficiency is improved. be able to. Furthermore, when the power of the received signal is large, the base station can receive the transmitted signal even if the power of the transmitted signal is reduced because the received signal is near the base station. Thus, with a simple configuration, the transmission power can be changed according to the power of the received signal, and the power consumption can be reduced.

The high-frequency circuit according to claim 8 includes a power amplifier circuit having at least one dual-gate FET for amplifying a received high-frequency signal, and the power amplifier circuit is a drain-side gate of the dual-gate FET. The high-frequency signal to be transmitted to the first gate is input, and the DC voltage output from the power detection unit after converting the power of the received signal is input to the second gate, which is the source-side gate of the dual-gate FET. The output power is controlled by the DC voltage. From this, in the power amplifier circuit, the static characteristics of the dual gate FET can be changed according to the DC voltage input to the second gate,
Since the gain of the power amplifier circuit can be changed, miniaturization and cost reduction can be achieved with a simple configuration, low power consumption can be achieved without increasing distortion, and power efficiency can be improved. be able to. Further, when the power of the received signal is higher than the desired power, the gain of the power amplifier circuit decreases, and deterioration of the characteristics of the power amplifier circuit due to saturation of the power amplifier circuit can be prevented with a simple configuration.

The high-frequency circuit according to claim 9 is the dual-gate FET according to claims 6 to 8, which is generated as the DC bias voltage input to the second gate changes and forms the input section of the power amplifier circuit. And an impedance adjustment circuit for canceling and making constant changes in impedance at the first gate and at the output section of the power amplification circuit. From this, the DC input to the second gate
Since the change in input / output impedance caused by changing the voltage can be eliminated and the input / output impedance can be kept constant, and the matching with the circuits connected to the input and output can be eliminated, the power amplification used at a high frequency of 5 GHz or more can be achieved. It can also be used for circuits.

The high-frequency circuit according to claim 10 is the same as claim 6
To claim 9, wherein the dual gate FET comprises a second gate FET.
By making the gate length of the gate electrode shorter than the gate length of the first gate electrode, the variable width of the static characteristics of the dual gate FET when a DC voltage is input to the second gate can be increased. That is, the variable range of the gain in the power amplifier circuit can be increased and the size can be reduced. Furthermore, since the resistance between the first gate and the source can be reduced, the power efficiency of the power amplifier circuit can be increased.

The high-frequency circuit according to the eleventh aspect is the first aspect.
0, specifically, the gate length of the gate electrode forming the first gate in the dual gate FET is 0.7 μm.
m to 1.5 μm, and the gate length of the gate electrode forming the second gate is 0.2 μm to 0.6 μm.
The drain withstand voltage can be increased, and a significant decrease in gain in the power amplifier circuit due to an excessively short gate length can be prevented.

According to the twelfth aspect of the present invention, there is provided the high-frequency circuit according to the sixth aspect.
According to the ninth aspect, the dual gate FET has a structure in which a conductive layer is formed by changing the concentration of Si ions implanted into the semiconductor substrate in three stages, and is formed under the second gate electrode in the conductive layer. The region with the lowest electron concentration is formed adjacent to the region with the highest electron concentration where the source electrode is formed and the region with the highest electron concentration formed on the first gate electrode side. Accordingly, even when a fine pattern for shortening the gate length cannot be formed, the variable width of the static characteristics of the dual gate FET when a DC voltage is input to the second gate can be increased. That is, since the variable range of the gain in the power amplifier circuit can be increased and the resistance between the first gate and the source can be reduced, the power efficiency of the power amplifier circuit can be increased.

The high-frequency circuit according to claim 13 is based on claim 1
2, in the conductive layer, the region having the lowest electron concentration formed under the first gate electrode is the same as the region where the drain electrode is formed and the region where the second gate electrode is formed.
It is formed so as to be connected to the region having the highest electron concentration adjacent to the gate electrode side through the region having the intermediate electron concentration. For this reason, the withstand voltage of the drain of the dual gate FET can be increased.

The high-frequency circuit according to claim 14 is based on claim 6
According to the ninth aspect of the present invention, in the dual gate FET, the thickness of the conductive layer formed on the semiconductor substrate is smaller in the region where the second gate electrode is formed than in the region where the first gate electrode is formed. As a result, the drain withstand voltage can be increased and the static characteristics of the dual-gate FET when a DC voltage is input to the second gate can be obtained even when a fine pattern for shortening the gate length cannot be formed. The variable width can be increased. That is, the variable range of the gain in the power amplifier circuit can be increased. Further, since the resistance between the first gate and the source can be reduced, the power efficiency of the power amplifier circuit can be increased.
Further, the present invention can be used not only for an FET formed by ion implantation but also for a power amplifier circuit using a high electron mobility transistor using an epitaxial gallium arsenide substrate.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram illustrating an example of a high-frequency circuit according to a first embodiment of the present invention.

FIG. 2 shows a case where the gate voltage Vg2 is 0.5 when the dual-gate FET 2 shown in FIG.
FIG. 6 is a diagram showing a load curve when the load is set to V;

FIG. 3 shows the case where the dual gate FET 2 shown in FIG.
It is a figure showing a load curve at the time of 5V.

FIG. 4 is a diagram showing an equivalent circuit of the dual gate FET 2 shown in FIG.

FIG. 5 is a schematic block diagram illustrating an example of a transmission circuit unit using the power amplification circuit 1 illustrated in FIG.

FIG. 6 is a schematic block diagram illustrating an example of a receiving circuit unit using a power amplifier circuit 31 configured to perform single-stage amplification using a dual-gate FET 2.

FIG. 7 is a schematic circuit diagram illustrating an example of a high-frequency circuit according to a second embodiment of the present invention.

FIG. 8 is a schematic sectional view showing a structural example of a dual-gate FET 2 used in a high-frequency circuit according to a third embodiment of the present invention.

FIG. 9 is a schematic sectional view showing a structural example of a dual-gate FET 2 used for a high-frequency circuit according to a fourth embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view showing a structural example of a dual-gate FET 2 used in a high-frequency circuit according to a fifth embodiment of the present invention.

FIG. 11 is a schematic circuit diagram showing a conventional example of a high-frequency circuit.

12 is a diagram illustrating input / output characteristics of the power amplification unit 101 illustrated in FIG.

FIG. 13 is a diagram showing input / output characteristics of the power amplifying unit 101 when the voltage Vb is reduced.

FIG. 14 is a diagram illustrating a relationship between a voltage Vb and a current Ic in the power amplification unit 101.

FIG. 15 is a diagram illustrating a relationship between a voltage Va and a current Ic in the power amplification unit 101.

FIG. 16 is a diagram showing a load curve when the FET shown in FIG. 11 is operated at a high frequency.

17 is a diagram showing a load curve when the gate voltage Vg of the FET in FIG. 16 is changed from -0.5V to -0.8V.

FIG. 18 shows a drain voltage Vd of the FET shown in FIG.
FIG. 4 is a diagram showing a load curve when the voltage is changed from 3V to 1V.

[Description of Signs] 1,31,40 Power amplification circuit, 2,3 Dual gate FET, 4-8 matching circuit, 9-12 resistance,
15 first FET, 16 second FET, 22 signal distributor, 23 antenna, 24 power detector, 25
Inverter circuit, 45 impedance adjustment circuit,
51, 61, 81 Gallium arsenide substrate, 52, 6
6, 67, 82 n-layer, 53, 64, 85 drain electrode, 54, 62, 83 first gate electrode, 55, 6
3,84 second gate electrode, 56,65,86 source electrode, 68,69,70 n ⁺ layer, 71,72n1 layer

Claims (14)

[Claims] In a dual-gate FET for amplifying a high-frequency signal, the gate length of a gate electrode forming a second gate on the source side is equal to the gate length of a gate electrode forming a first gate on the drain side. A dual-gate FET formed to be shorter than the above. 2. The semiconductor device according to claim 1, wherein the gate length of the gate electrode forming the first gate is 0.7 μm to 1.5 μm, and the gate length of the gate electrode forming the second gate is 0.2 μm to 0.6 μm. The dual gate F according to claim 1, wherein
ET. 3. In a dual-gate FET for amplifying a high-frequency signal, a conductive layer is formed by dividing an electron concentration injected into a semiconductor substrate into three or more types, and the conductive layer is a gate electrode on the drain side. The lower part of the first gate electrode and the lower part of the second gate electrode, which is the electrode of the gate on the source side, is formed so as to have the lowest electron concentration, and the lower part of the drain electrode and the source electrode has the highest electron concentration. The dual region having the lowest electron concentration formed below is formed adjacent to the region where the source electrode is formed and the region where the electron concentration is highest formed on the first gate electrode side. Gate FET. 4. The conductive layer includes a region having a lowest electron concentration formed under the first gate electrode, a region where a drain electrode is formed, a region where a second gate electrode is formed, and a first gate. 4. The dual gate FET according to claim 3, wherein the dual gate FET is formed so as to be connected to a region having the highest electron concentration adjacent to the electrode side through a region having an intermediate electron concentration. 5. In a dual-gate FET for amplifying a high-frequency signal, the thickness of a conductive layer formed on a semiconductor substrate is set to be larger on a source side than on a region on which a first gate electrode which is a drain-side gate electrode is formed. A dual gate FET, wherein a region for forming a second gate electrode, which is an electrode, is formed to be thinner. 6. An at least one amplifier for amplifying a high-frequency signal.
In a high-frequency circuit having a power amplifier circuit using two dual-gate FETs, a high-frequency signal is input to a first gate, which is a drain-side gate of the dual-gate FET, and a source-side gate, which is a dual-gate FET, A high frequency circuit, wherein a DC bias voltage is input to two gates, and the output power of the power amplifier circuit is controlled by the DC bias voltage. 7. A high-frequency circuit including a transmission circuit in a wireless communication device such as a mobile phone, comprising: a power amplifier circuit having at least one dual-gate FET for amplifying a high-frequency signal to be transmitted; Transmitting and receiving a high-frequency signal from the outside and receiving a high-frequency signal from the outside, a power detecting unit for detecting the power of the signal received by the transmitting and receiving unit, converting the detected power to a DC voltage and outputting the DC voltage The power amplifying circuit comprises: a high-frequency signal to be transmitted to a first gate, which is a drain-side gate of the dual-gate FET; A DC voltage output from the detection unit is input, and the output power is controlled by the DC voltage; . 8. A high-frequency circuit comprising a receiving circuit in a wireless communication device such as a mobile phone, comprising: a receiving unit for receiving a high-frequency signal from outside; and at least one amplifying the high-frequency signal received by the receiving unit. A power amplification circuit having a dual-gate FET; and a power detection unit that detects the power of the signal received by the reception unit, converts the detected power to a DC voltage, and outputs the DC voltage. The high-frequency signal received by the receiving unit is input to a first gate on the drain side of the dual gate FET, and the dual gate FE
A high-frequency circuit, wherein a DC voltage output from the power detection unit is input to a second gate, which is a source-side gate in T, and output power is controlled by the DC voltage. 9. A dual gate F which forms an input section of the power amplifying circuit and is generated in accordance with a change in a DC bias voltage input to a second gate of the dual gate FET.
9. An impedance adjusting circuit according to claim 6, further comprising an impedance adjusting circuit for canceling and keeping constant the respective impedance changes at the first gate of the ET and the output section of the power amplifier circuit. High frequency circuit. 10. The dual gate FET according to claim 6, wherein the gate length of the gate electrode forming the second gate is shorter than the gate length of the gate electrode forming the first gate. A high-frequency circuit according to claim 9. 11. The gate length of the gate electrode forming the first gate is 0.7 μm to 1.5 μm, and the gate length of the gate electrode forming the second gate is 0.2 μm to 0.6 μm. The high-frequency circuit according to claim 10, wherein: 12. In the dual gate FET, a conductive layer is formed by dividing an electron concentration to be injected into a semiconductor substrate into three or more types, and the conductive layer is formed below a first gate electrode and a second gate electrode. The electron concentration is low, the lower portion of the drain electrode and the source electrode are formed so as to have the highest electron concentration, and the region having the lowest electron concentration formed below the second gate electrode is the region where the source electrode is formed. 10. The semiconductor device according to claim 6, wherein the second gate electrode is formed adjacent to a region having the highest electron concentration formed on the first gate electrode side.
The high-frequency circuit according to any one of the above. 13. The conductive layer includes a region having a lowest electron concentration formed under the first gate electrode, a region where a drain electrode is formed, a region where a second gate electrode is formed, and a first gate. The high-frequency circuit according to claim 12, wherein the high-frequency circuit is formed so as to be connected to a region having the highest electron concentration adjacent to the electrode side through a region having an intermediate electron concentration. 14. The dual gate FET is formed such that the thickness of a conductive layer formed on a semiconductor substrate is smaller in a region where a second gate electrode is formed than in a region where a first gate electrode is formed. The high-frequency circuit according to any one of claims 6 to 9, wherein: