JPH09246506A - Manufacture of soi substrate - Google Patents
Manufacture of soi substrateInfo
- Publication number
- JPH09246506A JPH09246506A JP7950996A JP7950996A JPH09246506A JP H09246506 A JPH09246506 A JP H09246506A JP 7950996 A JP7950996 A JP 7950996A JP 7950996 A JP7950996 A JP 7950996A JP H09246506 A JPH09246506 A JP H09246506A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- active layer
- substrate
- layer wafer
- soi substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 230000002093 peripheral effect Effects 0.000 claims description 28
- 238000005498 polishing Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 abstract description 100
- 229910052710 silicon Inorganic materials 0.000 abstract description 25
- 239000010703 silicon Substances 0.000 abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 23
- 239000000428 dust Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明はＳＯＩ（Ｓｉｌｉ
ｃｏｎ ｏｎ Ｉｎｓｕｌａｔｏｒ）基板の製造方法、
例えば周縁の面取り部に支持基板用ウェーハの酸化膜を
残したＳＯＩ基板の製造方法に関する。The present invention relates to SOI (Sili)
manufacturing method of a con on insulator) substrate,
For example, the present invention relates to a method for manufacturing an SOI substrate in which an oxide film of a wafer for a supporting substrate is left on a chamfered portion on the periphery.
【０００２】[0002]
【従来の技術】ＳＯＩ基板の作製方法としては、絶縁膜
を挟んでシリコンウェーハ同士を室温で重ね合わせ、活
性層用ウェーハ表面をエッチング・研磨する方法があ
る。このようなＳＯＩ基板の作製方法としては、従来よ
り、例えば特開平５−６２９５１号公報に記載された方
法が知られている。図４に示すように、この方法によれ
ば、活性層用シリコンウェーハを支持基板用シリコンウ
ェーハと室温で張り合わせ、熱処理する。そして、この
ＳＯＩ基板の活性層用ウェーハの周縁部を面取りし、こ
の面取り面をエッチングしていた。2. Description of the Related Art As a method for manufacturing an SOI substrate, there is a method in which silicon wafers are superposed on each other with an insulating film interposed therebetween at room temperature, and the surface of a wafer for active layer is etched and polished. As a method for manufacturing such an SOI substrate, a method described in, for example, Japanese Patent Laid-Open No. 5-62951 has been conventionally known. As shown in FIG. 4, according to this method, the silicon wafer for active layer is bonded to the silicon wafer for supporting substrate at room temperature and heat-treated. Then, the peripheral portion of the active layer wafer of this SOI substrate was chamfered, and the chamfered surface was etched.
【０００３】[0003]
【発明が解決しようとする課題】ところが、この張り合
わせ後の面取りは支持基板用ウェーハに対してまで行っ
ていたため、以下の不具合が生じていた。すなわち、こ
の支持基板側面取り面からの発塵を防ぐため、面取り面
にエッチングを施す必要があった。これらの結果、支持
基板用ウェーハの周縁部の形状が特殊な形状に変形され
ていた。この支持基板用ウェーハの面取り形状を自由に
形成することができなかった。However, since the chamfering after the bonding is performed up to the wafer for the supporting substrate, the following problems have occurred. That is, it was necessary to etch the chamfered surface in order to prevent dust generation from the chamfered surface of the supporting substrate. As a result, the shape of the peripheral portion of the supporting substrate wafer has been transformed into a special shape. It was not possible to freely form the chamfered shape of the supporting substrate wafer.
【０００４】[0004]
【発明の目的】そこで、この発明は、支持基板用ウェー
ハの面取り部の形状を変更することなくＳＯＩ基板を作
製することをその目的としている。また、この発明は、
ＳＯＩ基板の面取り面の形状を任意の形状に形成可能と
することを、その目的としている。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to manufacture an SOI substrate without changing the shape of the chamfered portion of the supporting substrate wafer. In addition, the present invention
The purpose is to be able to form the chamfered surface of the SOI substrate into an arbitrary shape.
【０００５】[0005]
【課題を解決するための手段】請求項１に記載の発明
は、支持基板用ウェーハと活性層用ウェーハとの間に絶
縁膜を介在させたＳＯＩ基板の製造方法において、活性
層用ウェーハと支持基板用ウェーハとを張り合わせた
後、活性層用ウェーハの周縁部を面取りしてこの周縁部
に所定厚さの活性層用ウェーハを残す工程と、この周縁
部に残った活性層用ウェーハをエッチングして絶縁膜を
露出させる工程と、活性層用ウェーハの表面部分を研削
する工程と、この研削面を研磨する工程とを含むＳＯＩ
基板の製造方法である。According to a first aspect of the present invention, there is provided a method for manufacturing an SOI substrate in which an insulating film is interposed between a supporting substrate wafer and an active layer wafer, and the active layer wafer and the supporting layer are supported. After bonding with the substrate wafer, a step of chamfering the peripheral edge of the active layer wafer to leave an active layer wafer of a predetermined thickness on this peripheral edge, and etching the active layer wafer remaining on this peripheral edge SOI including a step of exposing the insulating film by exposing the surface of the active layer wafer, and a step of polishing the ground surface.
It is a method of manufacturing a substrate.
【０００６】請求項２に記載の発明は、活性層用ウェー
ハの一方の面側の周縁部を面取りする工程と、この活性
層用ウェーハの一方の面を研磨する工程と、この研磨面
を支持基板用ウェーハの絶縁膜に重ね合わせることによ
り、支持基板用ウェーハと活性層用ウェーハとを張り合
わせる工程と、活性層用ウェーハの表面側部分を研削す
る工程と、この研削面を研磨する工程とを備えたＳＯＩ
基板の製造方法である。According to a second aspect of the present invention, a step of chamfering a peripheral portion of one side of the active layer wafer, a step of polishing one side of the active layer wafer, and a step of supporting the polished surface By superposing on the insulating film of the substrate wafer, the supporting substrate wafer and the active layer wafer are bonded together, the surface side portion of the active layer wafer is ground, and the ground surface is polished. With SOI
It is a method of manufacturing a substrate.
【０００７】請求項３に記載の発明は、活性層用ウェー
ハの一方の面側の周縁部を面取りする工程と、この活性
層用ウェーハの一方の面を研磨する工程と、この研磨面
を支持基板用ウェーハの絶縁膜に重ね合わせることによ
り、支持基板用ウェーハと活性層用ウェーハとを張り合
わせる工程と、張り合わせられた活性層用ウェーハの表
面側の周縁部を面取りする工程と、活性層用ウェーハの
表面側部分を研削する工程と、この研削面を研磨する工
程とを備えたＳＯＩ基板の製造方法である。According to a third aspect of the present invention, a step of chamfering a peripheral edge portion on one surface side of the active layer wafer, a step of polishing one surface of the active layer wafer, and a step of supporting the polished surface By laminating the supporting substrate wafer and the active layer wafer by superposing them on the insulating film of the substrate wafer, a step of chamfering the peripheral portion of the front surface side of the laminated active layer wafer, and the active layer wafer. It is a method for manufacturing an SOI substrate including a step of grinding a front surface side portion of a wafer and a step of polishing the ground surface.
【０００８】[0008]
【作用】請求項１に記載の発明によれば、支持基板用ウ
ェーハに活性層用ウェーハを張り合わせた後、活性層用
ウェーハの周縁部を面取りする。この場合、面取り量を
調節してシリコン層を所定厚さだけこの周縁部に残す。
そして、この周縁部に残ったシリコン層をエッチングに
より除去し、絶縁膜を露出させる。このエッチングでは
シリコンを選択的にエッチングするものとする。次に、
この活性層用ウェーハを所定厚さになるまで研削し、さ
らに、研磨する。この結果、所定厚さの活性層が支持基
板用ウェーハ上に絶縁膜を介して配設されたＳＯＩ基板
を得ることができる。According to the first aspect of the invention, after the wafer for active layer is bonded to the wafer for support substrate, the peripheral portion of the wafer for active layer is chamfered. In this case, the chamfering amount is adjusted so that the silicon layer is left on the peripheral portion by a predetermined thickness.
Then, the silicon layer remaining on the peripheral portion is removed by etching to expose the insulating film. In this etching, silicon is selectively etched. next,
The wafer for active layer is ground to a predetermined thickness and further polished. As a result, it is possible to obtain an SOI substrate in which an active layer having a predetermined thickness is provided on a supporting substrate wafer via an insulating film.
【０００９】請求項２に記載の発明によれば、まず、活
性層用ウェーハの一方の面側の周縁部を面取りする。次
に、この活性層用ウェーハの一方の面を研磨する。この
研磨面が重ね合わせ面となる。また、支持基板用ウェー
ハには絶縁膜を被着・形成しておく。そして、この研磨
面を支持基板用ウェーハの絶縁膜に重ね合わせ、所定の
熱処理を行うことにより、支持基板用ウェーハと活性層
用ウェーハとを張り合わせる。そして、この張り合わせ
基板にあって活性層用ウェーハの表面側部分を研削す
る。次に、この研削面を研磨することにより、所望のＳ
ＯＩ基板を得る。According to the second aspect of the present invention, first, the peripheral portion on one surface side of the active layer wafer is chamfered. Next, one surface of the active layer wafer is polished. This polishing surface serves as a superposition surface. An insulating film is deposited and formed on the supporting substrate wafer. Then, the polished surface is superposed on the insulating film of the support substrate wafer, and a predetermined heat treatment is performed to bond the support substrate wafer and the active layer wafer. Then, the front surface side portion of the active layer wafer on this bonded substrate is ground. Next, by polishing this ground surface, the desired S
Obtain an OI substrate.
【００１０】請求項３に記載の発明によれば、支持基板
用ウェーハと活性層用ウェーハとを張り合わせた後、こ
の張り合わせ基板の活性層用ウェーハの表面側部分の周
縁部を面取りする。そして、この表面側部分を研削す
る。この結果、研削時に活性層用ウェーハに割れや欠け
が生じることがない。さらに、この研削面を研磨してＳ
ＯＩ基板が作製される。なお、この場合の活性層厚さは
例えば１０μｍ程度とする。According to the third aspect of the present invention, after the wafer for support substrate and the wafer for active layer are bonded together, the peripheral portion of the surface side portion of the wafer for active layer of this bonded substrate is chamfered. Then, the surface side portion is ground. As a result, the active layer wafer is not cracked or chipped during grinding. Further, the ground surface is polished to S
An OI substrate is produced. The thickness of the active layer in this case is, eg, about 10 μm.
【００１１】[0011]
【発明の実施の形態】以下、この発明の一実施例を図面
を参照して説明する。図１はこの発明の一実施例を示し
ている。この実施例によれば、活性層用のシリコンウェ
ーハＡ（鏡面研磨ウェーハ）の表面に予め熱酸化膜Ｓｉ
Ｏ2を形成しておく。また、このシリコンウェーハＡと
同一口径の支持基板用のシリコンウェーハＢ（鏡面研磨
ウェーハ）を準備しておく。そして、これらのウェーハ
同士を室温で重ね合わせた後、所定の張り合わせ熱処理
を行う（例えば１１００℃，２時間）。この結果、支持
基板用ウェーハに活性層用ウェーハが酸化膜を介して張
り合わされることとなる。また、張り合わせ熱処理によ
り、この張り合わせ基板の支持基板側の表面にも酸化膜
が被着されることとなる。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. According to this embodiment, the thermal oxide film Si is previously formed on the surface of the silicon wafer A (mirror-polished wafer) for the active layer.
O 2 is formed. Further, a silicon wafer B (mirror-polished wafer) for a support substrate having the same diameter as this silicon wafer A is prepared. Then, after laminating these wafers at room temperature, a predetermined bonding heat treatment is performed (for example, 1100 ° C. for 2 hours). As a result, the wafer for active layer is bonded to the wafer for support substrate through the oxide film. Further, the heat treatment for laminating also deposits an oxide film on the surface of the laminated substrate on the side of the supporting substrate.
【００１２】ここで、この張り合わせ基板についてその
活性層用ウェーハの周縁部に所定の面取りを施す。この
場合、面取り量を調節して活性層用ウェーハのシリコン
層を所定厚さ（例えば５μｍ）だけこの周縁部に残す。
そして、この周縁部に残ったシリコン層をエッチング
し、この部分に絶縁膜を露出させる。このエッチャント
はシリコンのみを選択的にエッチングするもの（例えば
ＫＯＨ系のエッチング液）を使用する。次に、この活性
層用ウェーハを所定厚さになるまで研削し、さらに、研
磨する。この結果、所定厚さ（例えば１０μｍ）の活性
層が支持基板用ウェーハ上に絶縁膜を介して配設された
ＳＯＩ基板を得ることができる。Here, a predetermined chamfer is applied to the peripheral portion of the active layer wafer of this bonded substrate. In this case, the chamfering amount is adjusted to leave the silicon layer of the active layer wafer on the peripheral portion by a predetermined thickness (for example, 5 μm).
Then, the silicon layer remaining on this peripheral portion is etched to expose the insulating film at this portion. As this etchant, one that selectively etches only silicon (for example, a KOH-based etching solution) is used. Next, the wafer for active layer is ground to a predetermined thickness and further polished. As a result, it is possible to obtain an SOI substrate in which an active layer having a predetermined thickness (for example, 10 μm) is provided on a supporting substrate wafer via an insulating film.
【００１３】図２はこの発明の他の実施例を示してい
る。この実施例によれば、支持基板用のシリコンウェー
ハＢ（鏡面ウェーハ）に予め所定厚さの熱酸化膜ＳｉＯ
2を形成しておく。また、同一口径の活性層用のシリコ
ンウェーハＡ（鏡面ウェーハ）を準備しておく。そし
て、これらのウェーハ同士を室温で重ね合わせた後、１
１００℃，２時間のアニールを施す。この結果、支持基
板用ウェーハに活性層用ウェーハが酸化膜を介して張り
合わされる。また、張り合わせ熱処理により、張り合わ
せ基板の表面（活性層用ウェーハの表面）にも熱酸化膜
が被着される。FIG. 2 shows another embodiment of the present invention. According to this embodiment, a silicon wafer B (mirror surface wafer) for a supporting substrate is preliminarily provided with a thermal oxide film SiO having a predetermined thickness.
Form 2 . In addition, a silicon wafer A (mirror surface wafer) for the active layer having the same diameter is prepared. Then, after stacking these wafers at room temperature,
Anneal at 100 ° C. for 2 hours. As a result, the wafer for active layer is bonded to the wafer for support substrate through the oxide film. In addition, the heat treatment for bonding also deposits a thermal oxide film on the surface of the bonded substrate (the surface of the wafer for active layer).
【００１４】ここで、この張り合わせ基板についてその
活性層用ウェーハの周縁部に所定の面取りを施す。この
場合、面取り量を調節して活性層用ウェーハのシリコン
層を所定厚さ（例えば５μｍ）だけこの周縁部に残す。
そして、この周縁部に残ったシリコン層をエッチング
し、この部分に絶縁膜を露出させる。このエッチャント
としてはＫＯＨ系のエッチング液を使用する。次に、こ
の活性層用ウェーハを所定厚さになるまで研削し、さら
に、鏡面研磨する。この結果、所定厚さの活性層が支持
基板用ウェーハ上に絶縁膜を介して配設されたＳＯＩ基
板を得ることができる。なお、活性層用のシリコンウェ
ーハ、支持基板用のシリコンウェーハのいずれにも酸化
膜を形成しておき張り合わせることもできる。Here, a predetermined chamfer is applied to the peripheral portion of the active layer wafer of this bonded substrate. In this case, the chamfering amount is adjusted to leave the silicon layer of the active layer wafer on the peripheral portion by a predetermined thickness (for example, 5 μm).
Then, the silicon layer remaining on this peripheral portion is etched to expose the insulating film at this portion. A KOH-based etching solution is used as this etchant. Next, this active layer wafer is ground to a predetermined thickness, and then mirror-polished. As a result, it is possible to obtain an SOI substrate in which an active layer having a predetermined thickness is provided on a supporting substrate wafer via an insulating film. Note that an oxide film may be formed and bonded to both the silicon wafer for the active layer and the silicon wafer for the supporting substrate.
【００１５】図３には、この発明のさらに他の実施例を
示している。この実施例では、まず、エッチング後のシ
リコンウェーハを用い、この活性層用ウェーハＡの一方
の面側の周縁部を面取りする。例えば５０〜２００μｍ
の面取りを行い、シリコンウェーハＡの中央部側に所定
径の部分を残しておく。次に、この活性層用ウェーハＡ
の一方の面（面取りした側の面）を鏡面研磨する。この
研磨面が重ね合わせ面となる。また、同一口径の支持基
板用ウェーハＢには絶縁膜を被着・形成しておく。そし
て、この研磨面を支持基板用ウェーハＢの絶縁膜上に重
ね合わせ、上記所定の熱処理を行うことにより、支持基
板用ウェーハＢと活性層用ウェーハＡとを張り合わせ
る。次に、この張り合わせ基板にあって、その活性層用
ウェーハ側の周縁部に所定の面取りを施す。この面取り
はオーバーハング部分をなくして研削を容易に行うため
である。さらに、この張り合わせ基板にあって活性層用
ウェーハの表面側部分を研削する。また、この研削面を
研磨することにより、所望のＳＯＩ基板を得る。FIG. 3 shows still another embodiment of the present invention. In this embodiment, first, a silicon wafer after etching is used, and the peripheral edge portion on one surface side of the active layer wafer A is chamfered. For example, 50 to 200 μm
Chamfering is performed to leave a portion having a predetermined diameter on the central side of the silicon wafer A. Next, this active layer wafer A
One surface (the surface on the chamfered side) is mirror-polished. This polishing surface serves as a superposition surface. An insulating film is deposited and formed on the supporting substrate wafer B having the same diameter. Then, the polished surface is superposed on the insulating film of the support substrate wafer B, and the predetermined heat treatment is performed to bond the support substrate wafer B and the active layer wafer A together. Next, a predetermined chamfer is applied to the peripheral portion of the bonded substrate stack on the active layer wafer side. This chamfering is for facilitating grinding by eliminating the overhang portion. Further, the surface side portion of the active layer wafer on this bonded substrate is ground. Moreover, a desired SOI substrate is obtained by polishing the ground surface.
【００１６】[0016]
【発明の効果】この発明によれば、ＳＯＩ基板にあって
その支持基板側からの発塵をなくすことができる。ま
た、その支持基板側ウェーハの形状を変更する必要がな
い。また、支持基板側の面取り形状を任意の形状に形成
することができる。例えば支持基板用ウェーハ部分にＭ
ＯＳ用、バイポーラ用のウェーハを用いてＳＯＩ基板を
作製することができる。According to the present invention, it is possible to eliminate dust from the supporting substrate side of the SOI substrate. Further, it is not necessary to change the shape of the supporting substrate side wafer. Further, the chamfered shape on the supporting substrate side can be formed in any shape. For example, in the wafer portion for the supporting substrate, M
An SOI substrate can be manufactured using OS and bipolar wafers.
【図面の簡単な説明】[Brief description of drawings]
【図１】この発明の一実施例に係るＳＯＩ基板の製造方
法を示すフローチャートである。FIG. 1 is a flowchart showing a method for manufacturing an SOI substrate according to an embodiment of the present invention.
【図２】この発明の他の実施例に係るＳＯＩ基板の製造
方法を示すフローチャートである。FIG. 2 is a flowchart showing a method of manufacturing an SOI substrate according to another embodiment of the present invention.
【図３】この発明の他の実施例に係るＳＯＩ基板の製造
方法を示すフローチャートである。FIG. 3 is a flowchart showing a method of manufacturing an SOI substrate according to another embodiment of the present invention.
【図４】従来のＳＯＩ基板の製造方法を示すフローチャ
ートである。FIG. 4 is a flowchart showing a conventional method for manufacturing an SOI substrate.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小松 圭 東京都千代田区大手町１丁目５番１号 三 菱マテリアルシリコン株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kei Komatsu 1-5-1, Otemachi, Chiyoda-ku, Tokyo Sanryo Material Silicon Co., Ltd.
Claims (3)
との間に絶縁膜を介在させたＳＯＩ基板の製造方法にお
いて、 活性層用ウェーハと支持基板用ウェーハとを張り合わせ
た後、活性層用ウェーハの周縁部を面取りしてこの周縁
部に所定厚さの活性層用ウェーハを残す工程と、 この周縁部に残った活性層用ウェーハをエッチングして
絶縁膜を露出させる工程と、 活性層用ウェーハの表面部分を研削する工程と、 この研削面を研磨する工程とを含むＳＯＩ基板の製造方
法。1. A method for manufacturing an SOI substrate in which an insulating film is interposed between a supporting substrate wafer and an active layer wafer, the active layer wafer and the supporting substrate wafer are bonded together, and then the active layer wafer is bonded. A step of chamfering the peripheral edge of the active layer wafer with a predetermined thickness to leave a peripheral edge on the peripheral edge, a step of etching the active layer wafer remaining on the peripheral edge to expose the insulating film, and an active layer wafer A method of manufacturing an SOI substrate, comprising: a step of grinding a surface portion of the substrate; and a step of polishing the ground surface.
を面取りする工程と、 この活性層用ウェーハの一方の面を研磨する工程と、 この研磨面を支持基板用ウェーハの絶縁膜に重ね合わせ
ることにより、支持基板用ウェーハと活性層用ウェーハ
とを張り合わせる工程と、 活性層用ウェーハの表面側部分を研削する工程と、 この研削面を研磨する工程とを備えたＳＯＩ基板の製造
方法。2. A step of chamfering a peripheral portion of one side of an active layer wafer, a step of polishing one side of the active layer wafer, and the polishing surface used as an insulating film of a supporting substrate wafer. Manufacture of an SOI substrate including a step of laminating a support substrate wafer and an active layer wafer by stacking, a step of grinding a front surface side portion of the active layer wafer, and a step of polishing the ground surface Method.
を面取りする工程と、 この活性層用ウェーハの一方の面を研磨する工程と、 この研磨面を支持基板用ウェーハの絶縁膜に重ね合わせ
ることにより、支持基板用ウェーハと活性層用ウェーハ
とを張り合わせる工程と、 張り合わせられた活性層用ウェーハの表面側の周縁部を
面取りする工程と、 活性層用ウェーハの表面側部分を研削する工程と、 この研削面を研磨する工程とを備えたＳＯＩ基板の製造
方法。3. A step of chamfering a peripheral portion of one side of an active layer wafer, a step of polishing one side of the active layer wafer, and the polishing surface used as an insulating film of a supporting substrate wafer. By laminating them, the supporting substrate wafer and the active layer wafer are bonded together, the peripheral edge on the surface side of the bonded active layer wafer is chamfered, and the surface side part of the active layer wafer is ground. And a step of polishing the ground surface, a method of manufacturing an SOI substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07950996A JP3480480B2 (en) | 1996-03-06 | 1996-03-06 | Method for manufacturing SOI substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07950996A JP3480480B2 (en) | 1996-03-06 | 1996-03-06 | Method for manufacturing SOI substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09246506A true JPH09246506A (en) | 1997-09-19 |
| JP3480480B2 JP3480480B2 (en) | 2003-12-22 |
Family
ID=13691930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07950996A Expired - Fee Related JP3480480B2 (en) | 1996-03-06 | 1996-03-06 | Method for manufacturing SOI substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3480480B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1126336A (en) * | 1997-07-08 | 1999-01-29 | Sumitomo Metal Ind Ltd | Laminated semiconductor substrate and method of manufacturing the same |
| EP0964436A2 (en) * | 1998-06-04 | 1999-12-15 | Shin-Etsu Handotai Company Limited | Method for manufacturing SOI wafer and SOI wafer |
| JP2001345435A (en) * | 2000-03-29 | 2001-12-14 | Shin Etsu Handotai Co Ltd | Silicon wafer, manufacturing method of laminated wafer and laminated wafer thereof |
| US6844242B2 (en) | 2001-07-13 | 2005-01-18 | Renesas Technology Corp. | Method of manufacturing SOI wafer |
| KR100701342B1 (en) * | 1999-07-15 | 2007-03-29 | 신에쯔 한도타이 가부시키가이샤 | Manufacturing method of bonded wafer and bonded wafer |
| JP2010157670A (en) * | 2009-01-05 | 2010-07-15 | Nikon Corp | Manufacturing method of semiconductor device, and semiconductor manufacturing device |
| JP2015076549A (en) * | 2013-10-10 | 2015-04-20 | 株式会社デンソー | Semiconductor substrate and manufacturing method of the same |
| JP2018182144A (en) * | 2017-04-17 | 2018-11-15 | 株式会社Sumco | Manufacturing method of multilayer film soi wafer and multilayer film soi wafer |
| CN110060959A (en) * | 2018-01-18 | 2019-07-26 | 胜高股份有限公司 | The manufacturing method of bonded wafer |
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|---|---|---|---|---|
| CN101599451B (en) * | 2009-07-10 | 2013-08-07 | 上海新傲科技股份有限公司 | Method for implementing edge chamfer on semiconductor substrate with insulating buried layer |
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- 1996-03-06 JP JP07950996A patent/JP3480480B2/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1126336A (en) * | 1997-07-08 | 1999-01-29 | Sumitomo Metal Ind Ltd | Laminated semiconductor substrate and method of manufacturing the same |
| EP0964436A2 (en) * | 1998-06-04 | 1999-12-15 | Shin-Etsu Handotai Company Limited | Method for manufacturing SOI wafer and SOI wafer |
| EP0964436A3 (en) * | 1998-06-04 | 2000-10-18 | Shin-Etsu Handotai Company Limited | Method for manufacturing SOI wafer and SOI wafer |
| US6534384B2 (en) | 1998-06-04 | 2003-03-18 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing SOI wafer including heat treatment in an oxidizing atmosphere |
| KR100701342B1 (en) * | 1999-07-15 | 2007-03-29 | 신에쯔 한도타이 가부시키가이샤 | Manufacturing method of bonded wafer and bonded wafer |
| JP2001345435A (en) * | 2000-03-29 | 2001-12-14 | Shin Etsu Handotai Co Ltd | Silicon wafer, manufacturing method of laminated wafer and laminated wafer thereof |
| US6844242B2 (en) | 2001-07-13 | 2005-01-18 | Renesas Technology Corp. | Method of manufacturing SOI wafer |
| JP2010157670A (en) * | 2009-01-05 | 2010-07-15 | Nikon Corp | Manufacturing method of semiconductor device, and semiconductor manufacturing device |
| JP2015076549A (en) * | 2013-10-10 | 2015-04-20 | 株式会社デンソー | Semiconductor substrate and manufacturing method of the same |
| JP2018182144A (en) * | 2017-04-17 | 2018-11-15 | 株式会社Sumco | Manufacturing method of multilayer film soi wafer and multilayer film soi wafer |
| CN110060959A (en) * | 2018-01-18 | 2019-07-26 | 胜高股份有限公司 | The manufacturing method of bonded wafer |
| CN110060959B (en) * | 2018-01-18 | 2023-03-21 | 胜高股份有限公司 | Method for manufacturing bonded wafer |
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