JPH09244590A - Output circuit and drive circuit of liquid crystal display including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit having an offset compensating circuit having a high speed and high accuracy. SOLUTION: An output circuit is provided with a capacitor C and three switches SW1-SW3, offset voltage of an output amplifier is stored in this capacitor C. This storing method is as follows. Electric charges of the capacitor C are once reset by an output amplifier, after that, an error of the output amplifier is stored in the capacitor, an error existing in the output amplifier originally is canceled by adding stored electric charges to the output amplifier, and desired output is obtained. In this case, the capacitor C is made not to operate as a load of the preceding circuit by control of the switches SW1-SW3.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to improvements in drive circuits. Especially, the deviation (offset voltage) of each output of a large number of drive circuits such as a drive circuit of a liquid crystal display device.
The present invention relates to a drive circuit in which is suppressed.

[0002]

2. Description of the Related Art An example of a conventional amplifier having an offset voltage correction function will be described with reference to the drawings. FIG.
Shows an example of an amplifier introduced by Japanese Patent Publication No. 5-85085. In the figure, OP1 and OP2 are operational amplifiers (opamps) to which differential inputs + IN and -IN are applied to the positive phase (non-inverting) input terminal and the negative phase (inverting) input terminal, respectively, and C1 and C2 are capacitors, S1
S12 is a transistor switch. In such a configuration, the switches S1, S2, S8, S9, S10,
S11 forms a first switch group. The switches S3, S4, S5, S6, S7, S12 form a second switch group. First switch group and second
The switch groups are controlled so as to be alternately conducted.

The operation of this amplifier will be described. First, the first switch group is controlled to be in the off state and the second switch group is controlled to be in the on state. This case is shown in FIG.
Shown in In this state, the operational amplifier OP1 is in the data output mode and the operational amplifier OP2 is in the offset voltage storage mode. Since the switches S1, S2 and S11 are closed, the operational amplifier OP1 outputs the complementary differential signal supplied to the input terminal to the output terminal. On the other hand, the positive phase input terminal of the operational amplifier OP2 is grounded, and the offset voltage component is output to the output terminal. This offset voltage causes the capacitor C
2 is charged and holds the offset voltage.

Next, the first switch group is controlled to be on and the second switch group is controlled to be off.
This case is shown in FIG. In this state, the operational amplifier O
P1 is in the offset voltage storage mode, and operational amplifier OP2 is in the data output mode. In this data output mode,
The switches S6, S7, and S12 are closed, and the capacitor C2 is connected in series between the negative-phase input terminal and the negative-phase input terminal. It is applied to the negative phase input terminal. As a result, the offset voltage is canceled and corrected from the output of the operational amplifier OP2.

By repeating such alternate operation of the switch group, the offset voltage of the operational amplifier OP1 is similarly corrected. The corrected output voltages of the operational amplifiers OP1 and OP2 are alternately output to the output terminal. As an application of the output circuit (amplifier) whose offset voltage is corrected, for example, a drive circuit of a liquid crystal display, which requires a uniform image display, can be considered.

A configuration example of a conventional liquid crystal drive circuit will be described with reference to the drawings. FIG. 8 is a block diagram showing an example of a liquid crystal drive circuit 50 that drives a liquid crystal display panel. The liquid crystal drive circuit 50 includes a data control unit 51, a sampling register 52, a load register 53, and a D / A converter 5.
4, an output circuit 55. Data control unit 5
1 is composed of a shift register or the like, and has a signal STH.
L, STHR, R / L, clock signal CLK, etc. are used to instruct the sampling register 52 to take in a series of image data from the data buses D0 to D5 in synchronization with the data supply. The sampling register 52, for example, sequentially takes in image data corresponding to one line of the screen of the liquid crystal display from the data buses D0 to D5. The load register 53 latches all the image data corresponding to one line held in the sampling register 52 in response to an STB signal supplied from the outside. Each data output of the sampling register 52 is supplied to a D / A converter 54 including a number of digital / analog converters corresponding to the number of pixels forming one line. The D / A converter 54 is
A reference voltage V0 to V8 supplied from the outside is generated by a resistance voltage dividing circuit to generate, for example, 64 gradation levels corresponding to the 6-bit data signal D0 ... D5, and a level signal corresponding to the content of the data signal is output. To do. D / A converter 5
The respective level signals output by the reference numeral 5 are supplied to a plurality of data lines of a liquid crystal panel (not shown) via an output section 55 including an output circuit provided for the number of pixels of one line. The output circuit is composed of an operational amplifier as shown in FIG.

An offset may occur in the output voltage of the operational amplifier. The offset of the output of any of the many operational amplifiers affects the image quality such as streaks and color unevenness. Therefore, as described with reference to FIG. 10, there is provided an output circuit in which the capacitor C is connected to the input side of the operational amplifier and the offset voltage is held in the capacitor C to compensate the offset voltage component in the output voltage. , Will be needed.

[0008]

However, when the above-mentioned output circuit for compensating for the offset voltage is applied to the liquid crystal driving circuit, about 300 circuits are simultaneously operated in the liquid crystal driving circuit. At this time, the input capacitance of the output circuit seen from the output terminal of the D / A converter 54 is used for offset compensation because of the internal wiring structure in which the operational amplifier of each output section can be connected to the voltage output of each stage. The capacity is the capacity C (C1 or C2) × 300. In the case of the resistance voltage dividing type D / A converter, when the load capacitance is large, the RC time constant becomes large and the signal rise is delayed. Further, in the output circuit shown in FIG. 10, the potential at one end of the capacitor must be constantly switched from the ground potential to rise to the level of the input signal -IN, so that the amplitude fluctuation is large and high-speed operation becomes difficult. This is particularly remarkable in the operation in which the input voltage transits between the maximum output “H” level and the minimum output “L” level. Therefore, high driving capability is required for the transistor of the preceding circuit (D / A converter).

Therefore, according to the present invention, it is possible to reduce the effective capacitance component on the input side which becomes the load of the preceding circuit.
An object is to provide an output circuit having a high-speed and highly accurate offset correction circuit.

[0010]

In order to achieve the above object, in the output circuit of the present invention, the positive phase input terminal is the circuit input terminal (1
1) and an operational amplifier (12) having an output terminal connected to a circuit output terminal (13), and first and second switches connected in series between the positive phase input terminal and the output terminal. Means (SW2, SW1), a third switch means (SW3) connected between the negative phase input terminal and the output terminal of the operational amplifier (12), and one end of the first and second switches. A capacitor (C) having the other end connected to the negative phase input terminal of the operational amplifier (12) at the connection point, and a switch control means (14) for controlling conduction of the first to third switch means, In the output circuit including the switch circuit, the switch control means makes the first switch means (SW2) non-conductive during the first period (T2) and the second circuit
And the third switch means (SW1, 2) are made conductive, and during the second period (T3), the first switch means (SW2) and the third switch means (SW3) are made conductive and the second switch means (SW3) is made conductive. The switch means (SW1) is made non-conductive, and in the third period (T4), the first and the third
The switch means (SW2, 3) are turned off and the second switch means (SW1) is turned on.

An output circuit of another invention includes an operational amplifier (12) having a positive phase input terminal connected to the circuit input terminal (11) and an output terminal connected to the circuit output terminal (13), and the positive amplifier. First and second switch means (SW2, SW1) connected in series between the phase input terminal and the output terminal, one end of the first and second switch means being connected to each other, and the other end of which is An output circuit comprising a capacitor (C) connected to the negative phase input terminal of the operational amplifier (12) and a switch control means (14) for controlling conduction of the first to third switch means, The switch control means, during the first period (T2), the first switch means (SW2)
Is turned off and the second and third switch means (SW1, 3) are turned on, and the first switch means (SW2) is turned on and the second and third switch means (SW1, 3) are turned on during the second period (T3). Third switch means (SW1, 3)
Are rendered non-conductive, and in the third period (T4), the first and third switch means (SW2, 3) are rendered non-conductive and the second switch means (SW1) is rendered conductive. Characterize.

Further, the drive circuit of the liquid crystal display device of the present application is characterized by including the output circuit.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the output circuit of the present invention. An input signal VIN supplied from the outside, for example, from a D / A converter (not shown) is supplied to an operational amplifier 12 having a gain of 1 through an input terminal 11 of the output circuit. Is applied to the positive phase input terminal of. The output signal VOUT of the operational amplifier 12 is output to the outside through the output terminal 13VOUT of the output circuit.
Switches 2 and 3 operated by a control signal are connected in series between the positive-phase input terminal of the operational amplifier and the output terminal of the operational amplifier. A capacitor C is connected between the connection point between the switches 2 and 3 and the negative phase input terminal of the operational amplifier 12. Further, a switch 3 operated by a control signal is connected between the negative phase input terminal of the operational amplifier 12 and the output terminal of the operational amplifier 12. The switches 1 to 3 are configured as so-called transfer gate switches including, for example, NMOS transistors and PMOS transistors. The capacitor C and the switches 1 to 3 form an offset compensation circuit. The operations of the switches 1 to 3 are controlled by a switch control circuit 14 as a switch control means as shown in a timing chart described later. The switch control circuit 14 is composed of a logic circuit and a microprocessor.

Next, the operation of the output circuit will be described with reference to the timing chart of FIG. 2 and the connection state diagram of FIG.

First, in the period T1 which is the previous state, only the switch 1 is turned on and the other switches 2 and 3 are turned off (FIG. 3 (a)). As a result, the output terminal of the operational amplifier and the negative phase input terminal are connected via the capacitor C. In this state, the output signal VOUT
The first level of the previous output continues.

In the period T2, the switch 3 is turned on in addition to the switch 1 (FIG. 3 (b)). Further, the input voltage VIN is applied, the level of the input terminal 11 changes, and the output signal VOUT transits to the second level. As a result, the capacitor C is short-circuited, and both ends of the capacitor a,
b becomes the same potential in a short time. The second level output voltage VOUT of the operational amplifier 12 becomes VIN ± Voff including the positive or negative offset voltage ± Voff. When the switches 1 and 3 are turned on, both ends of the capacitor C are connected to the operational amplifier 12
Since it is connected to the output terminal of
Both potentials of VOUT (=
VIN ± Voff).

In the period T3, the switch 1 is turned off while the switch 3 is kept on, and then the switch 2 is turned on. As a result, one end a of the capacitor C is connected to the input end 1
1 (FIG. 3 (c)). One end a of the capacitor C
Is the voltage VOU due to the transistor in the preceding circuit (not shown).
Pulled from T to voltage VIN. Since the switch 3 is on, the other terminal b of the capacitor C is connected to the output voltage VOUT.
Remains. Therefore, the voltage applied to the capacitor is VOUT-VIN = VIN ± Voff-VIN = ± Voff, and the capacitor C is charged with the offset voltage Voff. In this operation, the voltage at the one end a of the capacitor C only changes from VOUT (that is, VIN ± Voff) to VIN, so that the load of the transistor for outputting VIN of the preceding stage circuit (not shown) is only the offset voltage ± Voff. It is a small burden. Therefore, the terminal a reaches the voltage VIN in a short time.

This is because, for example, a terminals of 300 capacitors of the output circuit of the liquid crystal drive circuit are simultaneously input voltage VIN.
That is, when changing up to, only the offset voltage Voff is required.

During the period T4, the switches 2 and 3 are turned off, and then the switch 1 is turned on ((FIG. 3).
(D))). By turning off the switches 2 and 3, the capacitor is directly connected between the negative phase input terminal and the output terminal of the operational amplifier, and the offset voltage Voff is applied to the capacitor C.
Is held. When the switch 1 is turned on, the offset voltage Voff is applied to the negative phase input terminal of the operational amplifier 12 with reference to the potential of the output terminal. As a result, the output voltage VOUT is VOUT = VIN ± Voff− (± Voff)
= VIN, and the offset voltage is canceled. The output voltage becomes the corrected third level.

The correction of the offset voltage can also be explained as follows. When the charge stored in the capacitor C in the period T3 is Q1, [VIN- (VIN ± Voff)]. C = Q1 (1) In the period T4, the charge stored in the capacitor C is Q.
If 2, then [VOUT- (VIN ± Voff)]. C = Q2 (2) holds. Here, according to the law of conservation of charge, Q1 = Q2
Therefore, VIN = VOUT, and the offset voltage Voff is corrected.

The advantage of the above-described embodiment is that the conventional amplifier described with reference to FIG. 10 applies the ground potential to the operational amplifier and holds the offset voltage output in the capacitor,
In the signal processing mode, the input signal is applied to the capacitor to compensate the offset voltage of the output of the operational amplifier, whereas in the signal processing mode of the present application (FIG. 3D), the capacitor is not present in the route of the input signal. Because
The driving capability of the transistor in the preceding circuit is small.

FIG. 4 shows another embodiment. In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description of such parts is omitted.

In this embodiment, both ends a of the capacitor C are arranged so that the switch 3 short-circuits the capacitor C.
It is connected between b. Other configurations are similar to those of the circuit of FIG.

Next, the operation of the output circuit will be described with reference to the timing chart of FIG. 5 and the connection diagram of FIG.

First, during the period T1 which is the previous state, only the switch 1 is turned on and the other switches 2 and 3 are turned off (FIG. 6 (a)). As a result, the output terminal of the operational amplifier and the negative phase input terminal are connected via the capacitor C. In this state, the level of the output signal VOUT continues to be the first level (not shown) of the previous output.

In the period T2, the switch 3 is turned on in addition to the switch 1 (FIG. 6 (b)). Further, the level of the input voltage VIN not shown changes. This allows
The capacitor C is short-circuited and the output of the operational amplifier 12 causes both ends a and b of the capacitor to have the same potential in a short time. The output voltage VOUT of the operational amplifier 12 becomes VIN ± Voff including the positive or negative offset voltage ± Voff. Since both ends of the capacitor C are connected to the output end of the operational amplifier 12 when the switches 1 and 3 are turned on, the potentials at both ends a and b of the capacitor C are both VOUT (= VIN ± Voff).

In the period T3, the switches 1 and 3 are turned off, and then the switch 2 is turned on. As a result, one end a of the capacitor C is connected to the input end 11 (FIG. 6 (c)). One end a of the capacitor C is pulled from the voltage VOUT to the voltage VIN. Since the switch 3 is off, the other terminal b of the capacitor C remains at the output voltage VOUT. Therefore, the voltage applied across the capacitor is VOUT-VIN = VIN ± Voff-VIN = ± Voff, and the capacitor C is charged (or discharged) with the offset voltage Voff. Even in this operation, the voltage at the one end a of the capacitor C only changes from VOUT (VIN ± Voff) to VIN by the offset voltage.
The terminal a reaches the voltage VIN in a short time. Therefore, even in this output circuit, the driving capability of the transistor of the preceding circuit for driving this output circuit is small, which is advantageous when a large number of output circuits need to be driven simultaneously.

In the period T4, the switches 1 to 3 are turned off, and then the switch 1 is turned on (see FIG. 6).
(D)). The offset voltage Voff is held in the capacitor C by turning off the switches 1 to 3. When the switch 1 is turned on, the offset voltage Voff is applied to the negative phase input terminal of the operational amplifier 12 with reference to the potential of the output terminal. As a result, the output voltage VOUT is VO
UT = VIN. +-. Voff-(. +-. Voff) = VIN, the offset voltage is canceled out, and the offset voltage component of the output voltage is corrected as in the first embodiment.

Also in this embodiment, in the signal processing mode in which the output circuit outputs the input signal (FIG. 6 (d)),
Since the capacitor does not exist on the route of the input signal to the operational amplifier, it is possible to avoid the configuration in which the capacitor is connected as the load of the transistor of the pre-stage circuit (not shown), and it is possible to relatively reduce the driving capability. Reserved.

FIG. 7 shows a case where the output circuit of the present application is used for the output section 55 of the drive circuit 50 of the liquid crystal display shown in FIG. Considering the operation timing of each switch of the compensation circuit for compensating the offset voltage of the output circuit, the offset correction capacitor should not be present in the route of the input signal in the signal processing mode (FIGS. 3D and 6D). By doing so, the influence of the capacitor component on the input side of the output circuit with respect to the drive circuit in the preceding stage (not shown) is minimized. Therefore, it is convenient to use the output circuit of the present application in a drive circuit of a liquid crystal display device that requires connection of a large number of output circuits (amplifiers) corresponding to the number of pixels in one line.

[0031]

As described above, according to the present invention,
Since the increase in the input side capacitance of the output circuit due to the capacitor of the offset voltage compensation circuit is small, the load on the pre-stage drive circuit can be reduced. Further, since the offset correction operation is quick, a high speed and highly accurate output circuit can be realized. Even when many output circuits are used, there is little variation in each output.
Therefore, an output circuit suitable for the liquid crystal drive circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of an output circuit of the present invention.

FIG. 2 is a timing chart explaining the operation of the output circuit of the present invention.

FIG. 3 is an explanatory diagram illustrating an operation of a compensation circuit of an output circuit.

FIG. 4 is a block circuit diagram showing another embodiment of the output circuit of the present invention.

FIG. 5 is a timing chart explaining the operation of another embodiment of the output circuit of the present invention.

FIG. 6 is an explanatory diagram illustrating an operation of a compensation circuit of an output circuit according to another embodiment.

FIG. 7 is a block diagram illustrating a configuration of an output unit in the liquid crystal drive circuit.

FIG. 8 is a block diagram showing an example of a conventional liquid crystal drive circuit.

FIG. 9 is a circuit diagram showing a configuration example of an output circuit of a conventional liquid crystal drive circuit.

FIG. 10 is a circuit diagram showing an example of a conventional output circuit having an offset voltage correction function.

11 is an operation circuit diagram for explaining a first operation mode of the output circuit shown in FIG.

12 is an operation circuit diagram for explaining a second operation mode of the output circuit shown in FIG.

[Explanation of symbols]

 11 Input Terminal 12, OP1, OP2 Operational Amplifier 13 Output Terminal 14 Switch Control Circuit SW1 to SW3 Switches

Claims (3)

[Claims] 1. An operational amplifier having a positive phase input terminal connected to a circuit input terminal and an output terminal connected to a circuit output terminal, and a first operational amplifier connected in series between the positive phase input terminal and the output terminal. And a second switch means, a third switch means connected between the negative-phase input terminal and the output terminal of the operational amplifier, one end at a connection point between the first and second switch means, and the other. An output circuit including a capacitor whose end is connected to the negative phase input terminal of the operational amplifier, and switch control means for controlling conduction of the first to third switch means, wherein the switch control means comprises: In the first period, the first switch means is made non-conductive and the second and third switch means are made conductive, and in the second period,
The first switch means and the third switch means are made conductive, the second switch means is made non-conductive, and the first and third switch means are made non-conductive in a third period, and An output circuit, characterized in that the second switch means is made conductive. 2. An operational amplifier having a positive-phase input terminal connected to a circuit input terminal and an output terminal connected to a circuit output terminal, and a first operational amplifier connected in series between the positive-phase input terminal and the output terminal. And a second switch means, one end of which is connected to the mutual connection point of the first and second switch means, and the other end of which is connected to the negative phase input terminal of the operational amplifier, and the first to third switches. And a switch control means for controlling conduction of the switch means, wherein the switch control means makes the first switch means non-conducting and the second and third switches in a first period. Conduct the switch means of, and during the second period,
The first switch means is turned on and the second and third switch means are turned off, and the first and third switch means are turned off and the second switch is turned off during a third period. An output circuit, characterized in that the switch means is made conductive. 3. A drive circuit for a liquid crystal display, including the output circuit according to claim 1 or 2.