JP3352876B2 - Output circuit and liquid crystal display driving circuit including the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a driving circuit. In particular, the output deviation (offset voltage) of each of a large number of driving circuits such as a driving circuit of a liquid crystal display device.
And to a drive circuit in which is suppressed.

[0002]

2. Description of the Related Art An example of a conventional amplifier having an offset voltage correcting function will be described with reference to the drawings. FIG.
Shows an example of an amplifier introduced in Japanese Patent Publication No. 5-85085. In the figure, OP1 and OP2 are operational amplifiers (op-amps) to which differential inputs + IN and -IN are applied to a positive-phase (non-inverting) input terminal and a negative-phase (inverting) input terminal, respectively, C1 and C2 are capacitors, S1
S12 are transistor switches. In such a configuration, the switches S1, S2, S8, S9, S10,
S11 forms a first switch group. Switches S3, S4, S5, S6, S7, and S12 form a second switch group. The first switch group and the second
Are controlled so as to be turned on alternately.

The operation of this amplifier will be described. First, the first switch group is controlled to be off, and the second switch group is controlled to be on. In this case, FIG.
Shown in In this state, the operational amplifier OP1 is in the data output mode, and the operational amplifier OP2 is in the offset voltage storage mode. Since the switches S1, S2 and S11 are closed, the operational amplifier OP1 outputs a complementary differential signal supplied to an input terminal to an output terminal. On the other hand, the positive-phase input terminal of the operational amplifier OP2 is grounded, and the output terminal outputs an offset voltage. This offset voltage causes the capacitor C
2 is charged and holds the offset voltage.

[0004] Next, the first switch group is controlled to be in an on state, and the second switch group is controlled to be in an off state.
This case is shown in FIG. In this state, the operational amplifier O
P1 is in the offset voltage storage mode, and the operational amplifier OP2 is in the data output mode. In this data output mode,
Since the switches S6, S7 and S12 are closed and the capacitor C2 is connected in series between the input terminal of the opposite phase and the input terminal of the opposite phase, the offset voltage of the opposite polarity is superimposed on the differential signal -IN to switch the operational amplifier OP2. Applied to the negative phase input terminal. As a result, the offset voltage is offset from the output of the operational amplifier OP2 and corrected.

[0005] By repeating such an alternate operation of the switch group, the offset voltage of the operational amplifier OP1 is similarly corrected. The corrected output voltages of the operational amplifiers OP1 and OP2 are alternately output to the output terminals. As an application of the output circuit (amplifier) in which the offset voltage is corrected, for example, a driving circuit of a liquid crystal display that requires a uniform image display can be considered.

A configuration example of a conventional liquid crystal drive circuit will be described with reference to the drawings. FIG. 8 is a block diagram illustrating an example of a liquid crystal drive circuit 50 that drives a liquid crystal display panel. The liquid crystal drive circuit 50 includes a data control unit 51, a sampling register 52, a load register 53, and a D / A converter 5.
4. It is composed of an output circuit 55. Data control unit 5
1 is constituted by a shift register or the like, and the signal STH
Using the L, STHR, R / L, clock signal CLK and the like, a series of image data from the data buses D0 to D5 is instructed to the sampling register 52 in synchronization with the data supply. The sampling register 52, for example, sequentially takes in image data corresponding to one line of the screen of the liquid crystal display from the data buses D0 to D5. The load register 53 latches all image data corresponding to one line held in the sampling register 52 in response to an externally supplied STB signal. Each data output of the sampling register 52 is supplied to a D / A converter 54 including a number of digital / analog converters corresponding to the number of pixels constituting one line. The D / A converter 54 is
A reference voltage V0 to V8 supplied from the outside is generated by a resistor voltage dividing circuit to generate, for example, 64 gradation levels corresponding to 6-bit data signals D0... D5 and output a level signal corresponding to the contents of the data signal. I do. D / A converter 5
Each level signal output by 5 is supplied to a plurality of data lines of a liquid crystal panel (not shown) via an output unit 55 composed of output circuits provided for the number of pixels of one line. The output circuit is configured by an operational amplifier as shown in FIG.

[0007] An offset can occur in the output voltage of the operational amplifier. The offset of any one of the outputs of a large number of operational amplifiers affects the image quality such as stripes and color unevenness. Therefore, as described with reference to FIG. 10, an output circuit in which a capacitor C is connected to the input side of the operational amplifier and which holds the offset voltage to compensate for the offset voltage in the output voltage is provided. , You need.

[0008]

However, when the output circuit for compensating for the offset voltage described above is applied to a liquid crystal drive circuit, about 300 circuits are simultaneously operated in the liquid crystal drive circuit. At this time, the input capacitance of the output circuit seen from the output terminal of the D / A converter 54 is used for offset compensation because of the internal wiring structure that allows the operational amplifier of each output unit to be connected to the voltage output of each stage. The capacity is a capacity C (C1 or C2) × 300. In the case of a resistive voltage dividing D / A converter, if the load capacity is large, the RC time constant becomes large and the rise of the signal is delayed. Further, in the output circuit shown in FIG. 10, since the potential at one end of the capacitor needs to be constantly switched from the ground potential and rise to the level of the input signal -IN, amplitude fluctuation is large and high-speed operation becomes difficult. This is particularly remarkable in the operation in which the input voltage transitions between the maximum output “H” level and the minimum output “L” level. Therefore, a high driving capability is required for the transistor of the preceding stage circuit (D / A converter).

Therefore, the present invention makes it possible to reduce the effective capacitance component on the input side, which is a load on the preceding circuit.
An object of the present invention is to provide an output circuit having a high-speed and high-accuracy offset correction circuit.

[0010]

In order to achieve the above object, an output circuit according to the present invention has a positive-phase input terminal connected to a circuit input terminal (1).
1), an operational amplifier (12) having an output terminal connected to a circuit output terminal (13), the in- phase input terminal and the output terminal.
Between the positive-phase input end and the output end
Column-connected first switch means (SW2) and second switch means
Switch means (SW1); third switch means (SW3) connected between the negative-phase input terminal and the output terminal of the operational amplifier (12); and one end connected to the first and second switches. A capacitor (C) having the other end connected to the negative-phase input terminal of the operational amplifier (12); and a switch control means (14) for controlling conduction of the first to third switch means. In the output circuit, the switch control means causes the first switch means (SW2) to be non-conductive and the second switch means to be non-conductive during the first period (T2).
And third switching means (SW1, 3) to conduct, in the second period (T3), said first switch means (SW2) and third when the conductive switch means (SW3) both the second The first switch means (SW1) is turned off and the first and third switch means (SW2, 3) are turned off and the second switch means (SW1) is turned off in the third period (T4). Are conducted.

An output circuit according to another aspect of the present invention includes an operational amplifier (12) having a positive- phase input terminal connected to the circuit input terminal (11) and an output terminal connected to the circuit output terminal (13). phase
Between the input terminal and the output terminal from the positive-phase input terminal side
The first switch means (S
W2) and the second switch means (SW1), and a capacitor having one end connected to the connection point between the first and second switch means and the other end connected to the opposite-phase input terminal of the operational amplifier (12). C) and the capacitor (C) connected in parallel.
Third switch means (SW3), and the first to third switches
Switch control means (1) for controlling conduction of the switch means
4) In the output circuit including the above, the switch control means makes the first switch means (SW2) non-conductive and the second and third switch means (in the first period (T2)). SW1, 3) are turned on, and in the second period (T3), the first switch means (SW3) is turned on.
2), the second and third switch means (SW1, 3) are turned off, and the third period (T4).
In the above, the first and third switch means (SW2, SW2)
3) is turned off, and the second switch means (SW1) is turned on.

Further, a driving circuit for a liquid crystal display according to the present invention includes the above-mentioned output circuit.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an output circuit according to the present invention.
The input signal VIN supplied from the / A converter is applied to the positive-phase input terminal of the operational amplifier 12 having a gain of 1 via the input terminal 11 of the output circuit. The output signal VOUT of the operational amplifier 12
Is output to the outside via the output terminal 13VOUT of the output circuit. A switch 2 operated by a control signal and a switch 2 are connected between the positive-phase input terminal of the operational amplifier and the output terminal of the operational amplifier.
And 1 are connected in series from the positive-phase input terminal side to the output terminal side . Connection point between switches 2 and 1 and operational amplifier 1
The capacitor C is connected between the two negative-phase input terminals.
Further, a switch 3 operated by a control signal is connected between an opposite-phase input terminal of the operational amplifier 12 and an output terminal of the operational amplifier 12. Switches 1 to 3 are, for example, NMOS
It is configured as a so-called transfer gate switch including a transistor and a PMOS transistor. The capacitor C and the switches 1 to 3 constitute an offset compensation circuit. The operation of the switches 1 to 3 is controlled by a switch control circuit 14 as a switch control means as shown in a timing chart described later. The switch control circuit 14 includes a logic circuit and a microprocessor.

Next, the operation of the output circuit will be described with reference to the timing chart of FIG. 2 and the connection state diagram of FIG.

First, in a period T1, which is the previous state, only the switch 1 is turned on and the other switches 2 and 3 are turned off (FIG. 3A). Thus, the output terminal of the operational amplifier and the negative-phase input terminal are connected via the capacitor C. In this state, the output signal VOUT
Is the same as the first level of the previous output.

In the period T2, the switch 3 is turned on in addition to the switch 1 (FIG. 3B). Further, the input voltage VIN is applied, the level of the input terminal 11 changes, and the output signal VOUT changes to the second level. As a result, the capacitor C is short-circuited, and both ends a,
b becomes the same potential in a short time. The output voltage VOUT at the second level of the operational amplifier 12 becomes VIN ± Voff including the positive or negative offset voltage ± Voff. When the switches 1 and 3 are turned on, both ends of the capacitor C are connected to the operational amplifier 12.
, The two ends a, b of the capacitor C
Are both VOUT (=
VIN ± Voff).

In the period T3, the switch 1 is turned off while the switch 3 is on, and then the switch 2 is turned on. As a result, one end a of the capacitor C is connected to the input terminal 1
1 (FIG. 3C). One end a of the capacitor C
Is a voltage VOU by a transistor of a preceding circuit (not shown).
Pulled from T to voltage VIN. Since the switch 3 is on, the other terminal b of the capacitor C is connected to the output voltage VOUT
Remains. Therefore, the voltage applied to the capacitor is VOUT-VIN = VIN ± Voff-VIN = ± Voff, and the capacitor C is charged with the offset voltage Voff. In this operation, the voltage at one end a of the capacitor C only changes from VOUT (that is, VIN ± Voff) to VIN, so that the load of the transistor that outputs VIN of the preceding circuit (not shown) is only the offset voltage ± Voff. , Less burden. Therefore, the terminal a reaches the voltage VIN in a short time.

This is because, for example, the terminals a of 300 capacitors of the output circuit of the liquid crystal drive circuit are simultaneously connected to the input voltage VIN.
This means that the change only needs to be made by the offset voltage Voff.

In the period T4, the switches 2 and 3 are turned off, and then the switch 1 is turned on (see FIG.
(D))). By turning off the switches 2 and 3, the capacitor is directly connected between the inverting input terminal and the output terminal of the operational amplifier, and the offset voltage Voff is applied to the capacitor C.
Is held. When the switch 1 is turned on, the offset voltage Voff is applied to the negative-phase input terminal of the operational amplifier 12 with reference to the potential of the output terminal. As a result, the output voltage VOUT is VOUT = VIN ± Voff− (± Voff)
= VIN, and the offset voltage is cancelled. The output voltage becomes the corrected third level.

The correction of the offset voltage can be explained as follows. Assuming that the charge stored in the capacitor C in the period T3 is Q1, [VIN− (VIN ± Voff)] · C = Q1 (1) The charge stored in the capacitor C in the period T4 is Q1
Assuming that 2, the following holds: [VOUT− (VIN ± Voff)] · C = Q2 (2) Here, according to the law of conservation of charge, Q1 = Q2
Holds, VIN = VOUT, and the offset voltage Voff is corrected.

An advantage of the above-described embodiment is that the conventional amplifier described with reference to FIG. 10 holds the offset voltage output by applying the ground potential to the operational amplifier to the capacitor,
In the signal processing mode, an input signal is applied to the capacitor to compensate for the offset voltage of the output of the operational amplifier, whereas in the signal processing mode of the present application (FIG. 3D), no capacitor is interposed in the route of the input signal. So that
The driving capability of the transistors in the preceding circuit can be reduced.

FIG. 4 shows another embodiment. In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description of such parts is omitted.

In this embodiment, both ends a and c of the capacitor C are connected so that the switch 3 short-circuits the capacitor C.
b. Other configurations are the same as those of the circuit of FIG.

Next, the operation of the output circuit will be described with reference to the timing chart of FIG. 5 and the connection diagram of FIG.

First, in the period T1, which is the previous state, only the switch 1 is turned on, and the other switches 2 and 3 are turned off (FIG. 6A). Thus, the output terminal of the operational amplifier and the negative-phase input terminal are connected via the capacitor C. In this state, the level of the output signal VOUT is maintained at the first level (not shown) of the previous output.

In the period T2, the switch 3 is turned on in addition to the switch 1 (FIG. 6B). Further, the level of the input voltage VIN (not shown) changes. This allows
The capacitor C is short-circuited, and both ends a and b of the capacitor become the same potential in a short time by the output of the operational amplifier 12. The output voltage VOUT of the operational amplifier 12 becomes VIN ± Voff including the positive or negative offset voltage ± Voff. When the switches 1 and 3 are turned on, both ends of the capacitor C are connected to the output terminal of the operational amplifier 12, so that the potentials of both ends a and b of the capacitor C become VOUT (= VIN ± Voff).

In the period T3, the switches 1 and 3 are turned off, and then the switch 2 is turned on. Thereby, one end a of the capacitor C is connected to the input terminal 11 (FIG. 6C). One end a of the capacitor C is pulled from the voltage VOUT to the voltage VIN. Since the switch 3 is off, the other terminal b of the capacitor C remains at the output voltage VOUT. Therefore, the voltage applied to both ends of the capacitor is VOUT-VIN = VIN ± Voff-VIN = ± Voff, and the capacitor C is charged (or discharged) with the offset voltage Voff. Also in this operation, the voltage at one end a of the capacitor C only changes from VOUT (VIN ± Voff) to VIN by the offset voltage.
The terminal a reaches the voltage VIN in a short time. Therefore, in this output circuit as well, the driving capability of the transistor in the preceding circuit that drives this output circuit may be small, which is advantageous when it is necessary to drive many output circuits simultaneously.

In the period T4, the switches 1 to 3 are turned off, and then the switch 1 is turned on (FIG. 6).
(D)). By turning off the switches 1 to 3, the capacitor C holds the offset voltage Voff. When the switch 1 is turned on, the offset voltage Voff is applied to the negative-phase input terminal of the operational amplifier 12 with reference to the potential of the output terminal. As a result, the output voltage VOUT becomes VO
UT = VIN ± Voff− (± Voff) = VIN, and the offset voltages are cancelled, and the offset voltage of the output voltage is corrected in the same manner as in the first embodiment.

Also in this embodiment, in the signal processing mode in which the output circuit outputs an input signal (FIG. 6D),
Since the capacitor is not interposed on the route of the input signal to the operational amplifier, it is possible to avoid a configuration in which a capacitor is connected as a load of a transistor of a preceding circuit (not shown), which has an advantage that the driving ability can be relatively reduced. Secured.

FIG. 7 shows a case where the output circuit of the present invention is used for the output section 55 of the drive circuit 50 of the liquid crystal display shown in FIG. In consideration of the operation timing of each switch of the compensation circuit for compensating the offset voltage of the output circuit, in the signal processing mode (FIGS. 3D and 6D), there is no offset correction capacitor in the route of the input signal. By doing so, the influence of the capacitor component on the input side of the output circuit on the drive circuit in the preceding stage (not shown) is minimized. For this reason, it is convenient to use the output circuit of the present invention for a drive circuit of a liquid crystal display that requires connection of a large number of output circuits (amplifiers) corresponding to the number of pixels in one line.

[0031]

As described above, according to the present invention,
Since the increase in the input-side capacitance of the output circuit due to the capacitor of the offset voltage compensating circuit is small, the burden on the preceding-stage drive circuit can be reduced. Further, since the operation of offset correction is quick, a high-speed and high-precision output circuit can be realized. Even when a large number of such output circuits are used, variations in the outputs are small.
Therefore, an output circuit suitable for a liquid crystal drive circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of an output circuit of the present invention.

FIG. 2 is a timing chart illustrating the operation of the output circuit of the present invention.

FIG. 3 is an explanatory diagram illustrating an operation of a compensation circuit of an output circuit.

FIG. 4 is a block circuit diagram showing another embodiment of the output circuit of the present invention.

FIG. 5 is a timing chart illustrating the operation of another embodiment of the output circuit of the present invention.

FIG. 6 is an explanatory diagram illustrating an operation of a compensation circuit of an output circuit according to another embodiment.

FIG. 7 is a block diagram illustrating a configuration of an output unit in the liquid crystal driving circuit.

FIG. 8 is a block diagram illustrating an example of a conventional liquid crystal drive circuit.

FIG. 9 is a circuit diagram showing a configuration example of an output circuit of a conventional liquid crystal drive circuit.

FIG. 10 is a circuit diagram showing an example of a conventional output circuit having an offset voltage correction function.

11 is an operation circuit diagram illustrating a first operation mode of the output circuit shown in FIG.

FIG. 12 is an operation circuit diagram illustrating a second operation mode of the output circuit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input terminal 12, OP1, OP2 Operational amplifier 13 Output terminal 14 Switch control circuit SW1-SW3 Switch

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-59-154808 (JP, A) JP-A-4-56888 (JP, A) JP-A-5-94159 (JP, A) JP-A-5-154 297830 (JP, A) JP-A-57-80811 (JP, A) JP-A-56-104509 (JP, A) JP-A-63-185313 (JP, U) JP-A-5-181435 (JP, U) U.S. Pat. No. 4,565,971 (US, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580 H03F 3/20-3/44

Claims (3)

(57) [Claims] An operational amplifier having a positive-phase input terminal connected to a circuit input terminal and an output terminal connected to a circuit output terminal ;
Between the input terminal and the output terminal from the positive-phase input terminal side.
First switch means and a second switch
2 switch means, a third switch means connected between the negative-phase input terminal and the output terminal of the operational amplifier, one end is connected to a connection point between the first and second switch means, and the other end is An output circuit comprising: a capacitor connected to a negative-phase input terminal of the operational amplifier; and switch control means for controlling conduction of the first to third switch means. In the period, the first switch is turned off and the second and third switches are turned on. In the second period,
When to conduct the first switching means and the third switching means is both the second switching means nonconductive,
An output circuit, wherein during a third period, the first and third switch means are turned off and the second switch means is turned on. 2. An operational amplifier having a positive-phase input terminal connected to a circuit input terminal and an output terminal connected to a circuit output terminal ;
Between the input terminal and the output terminal from the positive-phase input terminal side.
First switch means and a second switch
A second switch means, a capacitor having one end connected to the connection point of the first and second switch means and the other end connected to the negative-phase input terminal of the operational amplifier, and a capacitor connected in parallel with the capacitor.
An output circuit comprising: a third switch connected to the switch; and a switch controller configured to control conduction of the first to third switch, wherein the switch controller is configured to: The first switch means is turned off, and the second and third switch means are turned on. In the second period,
The first switch means is turned on and the second and third switch means are turned off. During a third period, the first and third switch means are turned off and the second switch means is turned off. An output circuit for turning on a switch means. 3. A driving circuit for a liquid crystal display including the output circuit according to claim 1.