JPH09232326A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH09232326A JPH09232326A JP3916296A JP3916296A JPH09232326A JP H09232326 A JPH09232326 A JP H09232326A JP 3916296 A JP3916296 A JP 3916296A JP 3916296 A JP3916296 A JP 3916296A JP H09232326 A JPH09232326 A JP H09232326A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- concentration
- substrate
- impurity profile
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Abstract
(57)【要約】
【課題】エピタキシャル成長の結晶基板の不純物プロフ
ィルと同様の不純物プロフィルを有する拡散基板で製作
した半導体装置を提供すること。
【解決手段】軽イオンをn- 基板1とn+ 層2の境界か
らn+ 層2内に照射し、そのときの照射量は境界6付近
の照射量を多く、境界6から離れるに従って照射量を少
なく照射し、その照射量の範囲はドナー化する最小量で
ある1×10 12cm-2から1×1015cm-2で行い、熱
処理温度は350℃から600℃の範囲で行うことで界
面6の不純物プロフィルをエピタキシャル成長させた結
晶基板とほぼ同一とする。
(57) [Summary]
An impurity profile of a crystal substrate for epitaxial growth
Made from a diffusion substrate with the same impurity profile as the
To provide a semiconductor device having the above structure.
SOLUTION: Light ions are n-Substrates 1 and n+Is it the boundary of layer 2?
N+Irradiate into layer 2 and the irradiation dose at that time is near boundary 6
The irradiation dose is higher and the irradiation dose decreases as the distance from the boundary 6 increases.
Without irradiation, and the irradiation range is the minimum amount that can be converted into a donor.
There is 1 × 10 12cm-2From 1 × 10Fifteencm-2Done with heat
The processing temperature should be within the range of 350 ℃ to 600 ℃.
Result of epitaxial growth of impurity profile on surface 6
Almost the same as the crystal substrate.
Description
【発明の属する技術分野】この発明は、高耐圧ダイオー
ドなどのパワーデバイスにFZ結晶を適用した半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an FZ crystal is applied to a power device such as a high breakdown voltage diode.
【従来の技術】図2は拡散基板を用いた従来の高耐圧ダ
イオードで、同図(a)に断面構造、同図(b)に不純
物プロフィルを示す。同図(a)において、n- 基板1
にn+層3を拡散し、他方にp+ 層5を拡散して、p+
n- n+ 構造(通称pin構造といわれている)の高耐
圧ダイオードが形成される。同図(b)において、n-
n+ の界面6接合付近のn+ 層3の不純物プロフィルは
拡散でn+ 層3が形成されるため、図示されるようにそ
の形状は傾斜状7となっている。ダイオードが逆回復す
る時点で、空乏層の伸びがn+ 層3で抑えられるが、こ
のn+ 層3が傾斜状7になっていると、濃度が低い領域
では空乏層は伸び、高い領域になるにつれて伸びは抑え
られる。そのため、ある程度n+ 層3の奥まで空乏層が
伸びるため、逆回復電流の減少が緩やかになり逆回復損
失が大きくなる。この不都合を解決する方策の一つが傾
斜状をステップ状に変えることである。図3はエピタキ
シャル成長させた結晶基板を用いた従来の高耐圧ダイオ
ードで、同図(a)に断面構造、同図(b)にステップ
状の不純物プロフィルを示す。このステップ状9の不純
物プロフィルはn- 基板1上にn+ 層4をエピタキシャ
ル成長で積層して得られ、この結晶基板を用いて製作し
た高耐圧ダイオードの逆回復損失は図2の高耐圧ダイオ
ードと比べて低減する。2. Description of the Related Art FIG. 2 shows a conventional high breakdown voltage diode using a diffusion substrate. FIG. 2A shows a sectional structure and FIG. 2B shows an impurity profile. In FIG. 1A, n − substrate 1
N + layer 3 to the other, p + layer 5 to the other, p +
A high breakdown voltage diode having an n − n + structure (commonly called a pin structure) is formed. In the figure (b), n −
For n + impurity profile of the n + layer 3 in the vicinity of the interface 6 junction of the n + layer 3 is formed by diffusion, the shape as shown has a slope shape 7. When the diode is reverse recovery, the elongation of the depletion layer is suppressed at the n + layer 3, when the n + layer 3 has the inclined 7, elongation depletion layer at a low concentration region, the high area The growth is suppressed as it becomes. Therefore, the depletion layer extends to the depth of the n + layer 3 to some extent, so that the reverse recovery current decreases gradually and the reverse recovery loss increases. One of the measures to solve this inconvenience is to change the slope shape into a step shape. 3A and 3B show a conventional high breakdown voltage diode using an epitaxially grown crystal substrate. FIG. 3A shows a sectional structure and FIG. 3B shows a step-like impurity profile. This step-like impurity profile 9 is obtained by epitaxially growing the n + layer 4 on the n − substrate 1, and the reverse recovery loss of the high breakdown voltage diode manufactured using this crystal substrate is the same as that of the high breakdown voltage diode of FIG. Compared to.
【発明が解決しようとする課題】しかし、エピタキシャ
ル成長の結晶基板は通常の拡散基板と比べ、コストが2
倍程度高いという不都合がある。この発明の目的は、エ
ピタキシャル成長の結晶基板の不純物プロフィルと同様
の不純物プロフィルを有する拡散基板で製作した半導体
装置を提供することにある。However, the cost of the epitaxially grown crystal substrate is 2 compared with the ordinary diffusion substrate.
There is the inconvenience of being about twice as expensive. An object of the present invention is to provide a semiconductor device made of a diffusion substrate having an impurity profile similar to that of an epitaxially grown crystal substrate.
【課題を解決するための手段】前記の目的を達成するた
めに、低濃度の第一導電形の半導体基板の一主面から高
濃度の第一導電形の不純物原子を拡散して第一導電形の
高濃度拡散層を形成し、該高濃度拡散層の先端から高濃
度拡散層内に所定量の軽イオンを照射し、その後所定温
度で熱処理することで、軽イオンが照射された領域の格
子欠陥をドナー化し、高濃度拡散層の先端近傍の濃度プ
ロフィルがステップ状に形成される構成とする。この軽
イオンがプロトンもしくはヘリウムイオンであるとよ
い。また軽イオンの照射量を1×1012cm-2ないし1
×1015cm-2とし、且つ、軽イオンを照射した後の熱
処理温度を350℃ないし600℃とすることで軽イオ
ンで形成された格子欠陥をドナー化する。In order to achieve the above-mentioned object, a high-concentration first-conductivity-type impurity atom is diffused from one main surface of a low-concentration first-conductivity-type semiconductor substrate. -Shaped high concentration diffusion layer is formed, a predetermined amount of light ions are irradiated from the tip of the high concentration diffusion layer into the high concentration diffusion layer, and then heat treatment is performed at a predetermined temperature, so that The lattice defect is converted to a donor, and the concentration profile near the tip of the high concentration diffusion layer is formed in a step shape. The light ions are preferably protons or helium ions. In addition, the irradiation dose of light ions is 1 × 10 12 cm -2 to 1
The lattice defects formed by light ions are made into donors by setting the temperature to × 10 15 cm −2 and setting the heat treatment temperature after irradiation with light ions to 350 ° C. to 600 ° C.
【発明の実施の形態】図1はこの発明の実施例で、同図
(a)は軽イオンを照射している状態であり、同図
(b)はドナー化前後の不純物プロフィルを示す。軽イ
オンであるプロトンまたはヘリウムイオンをn- 基板1
とn+ 層2の境界からn+ 層2内に照射する。そのとき
の照射量は界面6付近の照射量を多く、界面6から離れ
るに従って照射量を少なく照射する。また照射量の範囲
はドナー化する最小量である1×1012cm-2から実用
上の最大値である1×1015cm-2で行う。また熱処理
温度はドナー化する最低温度の350℃からドナー化が
弱まる600℃までの範囲で行う。このような処理を行
うことで同図(b)のドナー化後の不純物プロフィルが
得られ、エピタキシャル成長させた結晶基板とほぼ同一
の不純物プロフィルが得られた。つまりn+ 層2の界面
近傍はステップ状7となっている。その結果、高耐圧ダ
イオードの逆回復損失がエピタキシャル成長の結晶基板
を用いたものと同一となった。この発明の実施例として
高耐圧ダイオードを示したが、IGBTなどのMOSゲ
ート構造デバイスのn+ バッファ層を軽イオンを照射し
たn+ 層2として利用しても勿論よく、またこの他の半
導体装置に軽イオンを照射した結晶基板を適用してもよ
い。この拡散基板に軽イオンを照射した結晶基板はエピ
タキシャル成長基板と比べてコストが3から4割程度安
価となり、この基板を用いて製作した半導体装置の製造
コストも大幅に低減させることができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, in which FIG. 1 (a) shows a state in which light ions are irradiated, and FIG. 1 (b) shows impurity profiles before and after donor formation. Proton or helium ion, which is a light ion, is added to n − substrate 1
Irradiate into the n + layer 2 from the boundary between the n + layer 2 and the n + layer 2. The irradiation amount at that time is large near the interface 6, and the irradiation amount is small as the distance from the interface 6 increases. The range of the irradiation amount is from 1 × 10 12 cm −2, which is the minimum dose for making a donor, to 1 × 10 15 cm −2 , which is the practical maximum value. The heat treatment temperature is in the range of 350 ° C., which is the lowest temperature at which donors are formed, to 600 ° C., at which donor formation is weakened. By carrying out such a treatment, the impurity profile after the donor formation shown in FIG. 6B was obtained, and the impurity profile almost the same as that of the epitaxially grown crystal substrate was obtained. That is, the step 7 is formed in the vicinity of the interface of the n + layer 2. As a result, the reverse recovery loss of the high breakdown voltage diode became the same as that using the epitaxially grown crystal substrate. Although the high breakdown voltage diode is shown as an embodiment of the present invention, the n + buffer layer of a MOS gate structure device such as an IGBT may of course be used as the n + layer 2 irradiated with light ions, and other semiconductor devices. Alternatively, a crystal substrate irradiated with light ions may be applied. The cost of the crystal substrate obtained by irradiating the diffusion substrate with light ions is about 30 to 40% lower than that of the epitaxial growth substrate, and the manufacturing cost of the semiconductor device manufactured using this substrate can be significantly reduced.
【発明の効果】この発明によると、n形の拡散基板の高
濃度領域にプロトンやヘリウムイオンの軽イオンを1×
1012cm-2以上照射し、熱処理を350℃以上で行う
ことで、エピタキシャル成長の結晶基板とほぼ同一の不
純物プロフィルの結晶基板を得て、この結晶基板を用い
ることで逆回復損失が小さく、製造コストが低い半導体
装置を得ることができる。According to the present invention, light ions such as protons and helium ions are added to the high concentration region of the n-type diffusion substrate at 1 ×.
By irradiating 10 12 cm -2 or more and performing heat treatment at 350 ° C. or more, a crystal substrate having an impurity profile almost the same as that of the epitaxially grown crystal substrate is obtained. By using this crystal substrate, reverse recovery loss is small and A semiconductor device with low cost can be obtained.
【図1】この発明の実施例で、(a)は軽イオンを照射
している図、(b)はドナー化前後の不純物プロフィル
を示す図FIG. 1A is a diagram showing irradiation of light ions, and FIG. 1B is a diagram showing impurity profiles before and after conversion into a donor in an embodiment of the present invention.
【図2】拡散基板を用いた従来の高耐圧ダイオードで、
(a)は断面構造図、(b)は不純物プロフィルを示す
図FIG. 2 is a conventional high breakdown voltage diode using a diffusion substrate,
(A) is a cross-sectional structure diagram, (b) is a diagram showing an impurity profile
【図3】エピタキシャル成長させた結晶基板を用いた従
来の高耐圧ダイオードで、(a)は断面構造図、(b)
はステップ状の不純物プロフィルを示す図3A and 3B are conventional high breakdown voltage diodes using an epitaxially grown crystal substrate, in which FIG. 3A is a sectional structural view, and FIG.
Shows a step-like impurity profile
1 n- 基板 2 n+ 層 3 n+ 層 4 n+ 層 5 p+ 層 6 界面 7 ステップ状 8 傾斜状 9 ステップ状1 n - Substrate 2 n + Layer 3 n + Layer 4 n + Layer 5 p + Layer 6 Interface 7 Steps 8 Gradient 9 Steps
Claims (3)
から高濃度の第一導電形の不純物原子を拡散して第一導
電形の高濃度拡散層を形成し、該高濃度拡散層の先端か
ら高濃度拡散層内に所定量の軽イオンを照射し、その後
所定温度で熱処理することで、軽イオンが照射された領
域の格子欠陥をドナー化し、高濃度拡散層の先端近傍の
濃度プロフィルをステップ状に形成することを特徴とす
る半導体装置の製造方法。1. A high-concentration diffusion layer of the first conductivity type is formed by diffusing high-concentration impurity atoms of the first conductivity type from one main surface of a low-concentration semiconductor substrate of the first conductivity type. By irradiating a certain amount of light ions into the high-concentration diffusion layer from the tip of the diffusion layer, and then performing heat treatment at a predetermined temperature, the lattice defects in the region irradiated with the light ions are made into donors, and the vicinity of the tip of the high-concentration diffusion layer A method for manufacturing a semiconductor device, characterized in that the concentration profile of is formed stepwise.
ンであることを特徴とする請求項1記載の半導体装置の
製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the light ions are protons or helium ions.
し1×1015cm-2とし、且つ、軽イオンを照射した後
の熱処理温度を350℃ないし600℃とすることを特
徴とする請求項1記載の半導体装置の製造方法。3. The light ion irradiation dose is 1 × 10 12 cm −2 to 1 × 10 15 cm −2 , and the heat treatment temperature after the light ion irradiation is 350 ° C. to 600 ° C. The method for manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03916296A JP3427609B2 (en) | 1996-02-27 | 1996-02-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03916296A JP3427609B2 (en) | 1996-02-27 | 1996-02-27 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09232326A true JPH09232326A (en) | 1997-09-05 |
JP3427609B2 JP3427609B2 (en) | 2003-07-22 |
Family
ID=12545436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP03916296A Expired - Lifetime JP3427609B2 (en) | 1996-02-27 | 1996-02-27 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3427609B2 (en) |
Cited By (8)
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---|---|---|---|---|
JP2001156299A (en) * | 1999-11-26 | 2001-06-08 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method thereof |
US6610572B1 (en) | 1999-11-26 | 2003-08-26 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2003533047A (en) * | 2000-05-05 | 2003-11-05 | インターナショナル・レクチファイヤー・コーポレーション | Method for implanting hydrogen into buffer region of punch-through non-epitaxial IGBT |
JP2007266233A (en) * | 2006-03-28 | 2007-10-11 | Toyota Central Res & Dev Lab Inc | Power semiconductor device and manufacturing method thereof |
JP2011054618A (en) * | 2009-08-31 | 2011-03-17 | Fuji Electric Systems Co Ltd | Method of manufacturing semiconductor device, and the semiconductor device |
JP2012142330A (en) * | 2010-12-28 | 2012-07-26 | Rohm Co Ltd | Semiconductor device and manufacturing method of the same |
JP2014165306A (en) * | 2013-02-25 | 2014-09-08 | Fuji Electric Co Ltd | Method of manufacturing superjunction semiconductor device |
JP2018206916A (en) * | 2017-06-02 | 2018-12-27 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
-
1996
- 1996-02-27 JP JP03916296A patent/JP3427609B2/en not_active Expired - Lifetime
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001156299A (en) * | 1999-11-26 | 2001-06-08 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method thereof |
US6610572B1 (en) | 1999-11-26 | 2003-08-26 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6759301B2 (en) | 1999-11-26 | 2004-07-06 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6762097B2 (en) | 1999-11-26 | 2004-07-13 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2003533047A (en) * | 2000-05-05 | 2003-11-05 | インターナショナル・レクチファイヤー・コーポレーション | Method for implanting hydrogen into buffer region of punch-through non-epitaxial IGBT |
JP2007266233A (en) * | 2006-03-28 | 2007-10-11 | Toyota Central Res & Dev Lab Inc | Power semiconductor device and manufacturing method thereof |
JP2011054618A (en) * | 2009-08-31 | 2011-03-17 | Fuji Electric Systems Co Ltd | Method of manufacturing semiconductor device, and the semiconductor device |
JP2012142330A (en) * | 2010-12-28 | 2012-07-26 | Rohm Co Ltd | Semiconductor device and manufacturing method of the same |
US9087857B2 (en) | 2010-12-28 | 2015-07-21 | Rohm Co., Ltd. | Semiconductor device, method of manufacturing the same, and power module |
US9184231B2 (en) | 2010-12-28 | 2015-11-10 | Rohm Co., Ltd. | Semiconductor device, method of manufacturing the same, and power module |
US9306000B2 (en) | 2010-12-28 | 2016-04-05 | Rohm Co., Ltd. | Semiconductor device, method of manufacturing the same, and power module |
US9536948B2 (en) | 2010-12-28 | 2017-01-03 | Rohm Co., Ltd. | Semiconductor device, method of manufacturing the same, and power module |
JP2014165306A (en) * | 2013-02-25 | 2014-09-08 | Fuji Electric Co Ltd | Method of manufacturing superjunction semiconductor device |
JP2018206916A (en) * | 2017-06-02 | 2018-12-27 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
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