JPH09214321A - Transistor and method for regulating threshold voltage for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a leak current at the time of off mode by controlling the threshold voltage of an inverter through bias control for both an inverter source voltage and a substrate voltage. SOLUTION: When a low input is impressed to an input 38, transistors 30 and 32 are respectively turned off and turned on, and an output 40 is pulled to an inverter source voltage Vsup. When a high input is impressed, on the other hand, the output 40 is pulled to the low side of a ground Vss 36. A threshold voltage VT of an NMOS transistor 30 can be changed by regulating the value of a substrate bias voltage VSUB1 of a terminal 42 and/or loading bias to the source by changing the voltage of any one of or both of the terminal 34 and the ground Vss 36. Thus, while the transistor is on standby or at the time of off mode, the leak current is minimized by controlling the voltage VT while utilizing the effects of the voltages VSUB and VSUP upon the voltage VT and when the transistor is turned on, a high driving current is waited.

Description

Detailed Description of the Invention

[0001]

[Relationship with Related Applications] This application is filed on February 18, 1994 and is pending US patent application serial number 08/1.
98,731 (applicant's copy number TI-17763), the contents of which are hereby cited.

[0002]

BACKGROUND OF THE INVENTION This invention relates to a multimode CMOS.
Inverters, and more particularly, to such inverters whose operating mode can be determined by the value of the source and substrate bias voltages.

[0003]

BACKGROUND OF THE INVENTION Since the birth of integrated circuits, reducing the size of its components and increasing their packing density has been a constant challenge. This has led to the existence of highly complex circuits used in many devices, some of which are portable, such as computers, telephones and watches. As the dimensions of devices that utilize such complex circuits have become smaller, power supplies, typically batteries, have become a major contributor to device volume and weight. Over the years, this problem has been dealt with in one or another of several ways. In it, install batteries with smaller dimensions (which resulted in shorter device uptime until the batteries were discharged),
It includes improvements in batteries that power for longer periods of time, and the manufacture of integrated circuits that can operate with ever lower power requirements to extend battery life. However, there continues to be a challenge to increase the circuit complexity for a given device size and / or reduce the device size for a given circuit complexity.

Many complex circuits currently utilized in portable electronic devices include CMOS components. Generally, such devices require a supply voltage of at least 3 volts. This means that at least two standard battery cells are needed, in addition to the other components forming the device in question. Batteries still represent a large portion of the weight and volume of the device in which they are utilized. To further reduce the size and / or weight of such devices, integrated circuits can be made to operate at lower voltages and / or require less power than is currently required. Obviously, the size of the battery can be further reduced if this is possible. For example, in a circuit that can operate at a lower voltage, such as about 1 volt, a single cell at 1.5 volts will allow much more battery power even after the cell has died due to long-term use. It could cover the entire power needs of the equipment that needs it today.

It has also been found that power consumption is proportional to the square of the supply voltage. This means that the power requirements of CMOS circuits are significantly reduced at lower voltage requirements, thus extending battery life when the circuits are battery operated. However, another problem is how to obtain adequate performance of CMOS circuits when the supply voltage is low, especially in the range of about 1 volt.

In the field of power savings, there have been attempts to operate integrated circuits in small hand-held devices at very low voltages, eg, ground-to-source voltage (V _SUP ) range of 1 V or less. Unfortunately, such very low power consumption circuits lack sufficient switching performance and drive capability for many applications. As such, the design engineer trades the benefits of low power with the need for high performance.

One conventional attempt to achieve high drive capability in very low power devices is to design the device with a very low threshold voltage (V _T ) with respect to the supply voltage (V _SUP ). It was While these devices have high gate drive capability, they typically have very high leakage current when off. The gate drive is defined as V _GS -V _T or V _SUP -V _T. Large leakage currents are undesirable as they drain the power supply, especially in battery operated devices. Another conventional attempt has been to create a circuit with a higher V _T with respect to the supply voltage. V _T high device is very small leakage current when off, to preserve the energy of the order power. However, a device having a high V _T has a poor driving capability and a slow switching response at turn-on.

As an alternative to this, there have been attempts to design circuits with moderate levels of V _T with improved drive capability and lower power consumption. This is just a compromise of the other schemes mentioned above, and some applications of low power circuits have been incompatible with the power consumption and / or drive capability of devices with moderate levels of V _T. This approach also requires a choice between a small leakage current when the device is off and a high drive capability when the device is on.

In such a conventional circuit, an ordinary CMOS inverter manufactured with a constant threshold voltage (V _T ) has low leakage and low performance characteristics, or high leakage and high performance characteristics. It was either.

[0010]

SUMMARY OF THE INVENTION The present invention substantially reduces the drawbacks and problems associated with low power transistors and inverters that have been conventionally developed, while at the same time providing low leakage and high performance. An improved multimode CMOS inverter is provided.

In simple terms, this is the source,
This is achieved by using different combinations of reference and substrate biases and thus providing many different modes of operation. The inverter of the present invention, depending on its operating mode, has V _T of one or both transistors of the inverter.
Achieves high performance and low power requirements by dynamically controlling. When the inverter is in standby mode (within duty cycle, ready for rapid change to on mode) In suspend mode (long wait and time to return to on mode) The value of V _T is close to or equal to V _GS , so that leakage current is minimized or eliminated when in off mode (device is turned off) or in off mode (device is turned off). , V _SUB and V _GS combinations.

The control of V _{T in} the inverter of the present invention is performed by controlling the source voltage (V _SUP ) of the inverter during the operation of the circuit.
And by controlling the bias of both the substrate voltage (V _SUB ). Therefore, in order to operate the inverter in the low power mode in which the inverter is in a standby or suspending operation, both V _GS and V _SUB are set so that V _T increases. Of course, by cutting off V _SUP , the temporary removal of V _GS guarantees that there is no leakage when in off mode. By dynamically modifying V _GS , the reference potential and V _SUB to give the inverter a different operating mode, the inverter can generate a high drive current when on and at the same time when in the standby or suspend mode. Leakage current can be reduced.

For a more complete understanding of the invention and its advantages, reference is now made to the drawings. In the drawings, like reference numbers represent like features.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows the IV characteristics of an ideal switch and two metal-oxide-semiconductor field effect transistors (MOSFETs), which operate with, for example, a 1 volt power supply (V _SUP ). . In FIG. 1, the X-axis represents the gate-source voltage (V _GS ) of the MOSFET in volts and the Y-axis represents the MOSFET drain current I _D in amps. The Y axis is a logarithmic scale.

Curve 10 is the IV characteristic of a theoretically ideal switch supplied with, for example, 1 volt. Curve 1
As shown by the example of 0, the ideal switch has no leakage current, has a low threshold voltage (0.2V) with respect to the supply voltage (1V), turns on momentarily, It has a high drive current (eg about 10 ^-2 amps) for (zero). The goal is to provide the device as close to curve 10 as possible. In this case, the current in the "off" state is small to minimize battery drain, and the current in the "on" state is as high as possible to be fast.

As the value of V _GS increases, the transistor operates in the subthreshold region, increasing I _D at a rate of about 60 mv / decade.

Curve 12 of FIG. 1 shows the typical IV characteristic of a MOSFET having a V _T of about 0.6 V, while the MOSFET represented by curve 14 has a V _T of about 0.2.
It is a bolt. Both MOSFETs shown in FIG. 1 have several operating regions. The off region 16 of the MOSFET represented by curve 12 has a small constant leakage current (eg, about 10 ^-12 amps). Once V
_{When GS} reaches a predetermined level of the device represented by curve 12 (eg 0.2 volts), it enters subthreshold region 18. The sub-threshold region of the MOSFET is a portion of the V _GS scale where the MOSFET is in a transition state between an off state and an on state. M represented by curve 12
Region 20 of the OSFET is the V _GS region (eg, about 0.6 volts) where the MOSFET saturates and turns on. M
The demarcation of V _GS between the sub-threshold region and the ON region of the OSFET is the V _T of the MOSFET. For the transistor represented by curve 12, V _T is 0.6V.

As can be seen in curve 12, V of about 0.6V
MOSFETs with _T have very low leakage or drain current while in the off region 16. Unfortunately, the subthreshold region 1 of the device represented by curve 12
8 is very long compared to the available V _GS range (eg 1 volt). Furthermore, the drive current of the ON region 20 (for example, 1
Approximately 10 ⁻⁴ amps in volts) is significantly less than the drive current available in an ideal switch (eg, approximately 10 ⁻² amps). Therefore, the MOS represented by curve 12
The FET is a low power device with low leakage current in the standby or off region 16. But the same MOSFET
Turning on requires a larger portion of the available V _GS range (0.6 volts), which slows the switching response of the transistor. Further, the MOSFET represented by curve 12 has a relatively low drive current (about 10 ^-4 amps) once turned on. Therefore, the device represented by curve 12 cannot provide acceptable performance.

MOSFET represented by curve 14
Is about 0.2 V_THas an ideal switch
It is the same as in Ji. Curve 14 is left compared to curve 12
Is shifted to, the transistor it represents is
Off, as indicated by point 22 where curve 14 intersects the Y axis.
When (V_GS= 0V leakage current is large (eg about 10V)
^-9Ampere). MOSFE represented by curve 14
Very small V for T _GSIs applied, it becomes curve 1
The area 24 below the threshold value of 4 is entered. Represented by curve 14
MOSFET has a short subthreshold region 24,
V_GSIs V of 0.2V_TEqual to
Like, turn on. M represented by curve 14
OSFET is a MOSFET represented by curve 12.
Drive current much closer to an ideal switch compared to T
(10^-2Ampere). Therefore, according to curve 14,
MOSFETs represented by high performance (high drive current and
Fast switching time), but leaks in standby mode
The disadvantage is that the current is large. Therefore, according to curve 14,
MOSFETs are not low power devices,
May be incompatible in a device with limited power.

The CMOS inverter of the present invention is
Depending on the working mode, V of the inverter _TDynamically
Achieving both low power and high performance by controlling
You. If the inverter is in standby mode, V_TTurn on
Set it higher than when in mode to maximize leakage current.
Try to keep it to a minimum. This is curve 12 in Figure 1.
This is represented by the area 16. The inverter is on
Then V_TIs set low to minimize the area below the threshold.
And the drive current is optimized for the transistor.
This is indicated by the area 26 of curve 14 in FIG.
You. Thus, when the inverter is in standby mode,
High current when the current is small and the inverter is turned on
Indicates drive capacity. When the inverter is in suspend mode, V
_TIs set higher than in standby mode,
Further reduce the magnitude of the current. In off mode, V
_SUPTurn off and thus make sure there are no leaks
(However, as an alternative, the off state is V_TThe value of
Can be set higher than when in disconnect mode
).

Control of V _{T in} the inverter of the present invention is accomplished by controlling the biasing action of both the source and substrate of the inverter. Generally, the value of V _T changes about 1/3 to 1/5 of the change in the voltage between the substrate and the source.

FIG. 2 shows the protocol required according to the invention.
R-V_TTypical CMOS Inverter that can change
Data 28 is shown. The inverter 28 is a PMOS transistor
Including a transistor 32 and an NMOS transistor 30,
The transistor of the inverter is V_T
Operated by control. Drain of transistor 30
The in is coupled to the drain of transistor 32
The gate of transistor 30 is coupled to the gate of transistor 32
Is done. The source of the transistor 32 is V_SUPCombined with 34
The source of the transistor 30 is grounded (V_SS) 36
Is combined with The input 38 of the inverter circuit 28 has both
Output 40 is coupled to the gate of the transistor
Coupled to the drain of the transistor. In addition, the substrate via
Voltage V _SUB1Also shown is a terminal 42 for changing. Furthermore,
Substrate bias voltage V for transistor 32_SUB2Change
Also shown is a removable terminal 44, which may be used alone or
It can be used with terminal 42 in the same way as terminal 42.
Wear. It can be used alone or with terminal 42
Yes, but not covered in the following discussion. here
Is the V of the transistor 32 for simplicity._TDescribed here
Assumed unchanged to operate in different modes
I do.

The operation of the inverter circuit 28 of FIG. 2 is as follows. Applying a low input to input 38 turns transistor 30 off and transistor 32 on, pulling output 40 to V _SUP 34. Conversely, applying a high input to input 38 turns transistor 30 on and transistor 32 off. This pulls output 40 low to ground (V _SS ) 36. The V _{T of the} NMOS transistor 30 is the V of the terminal 42.
_It can be changed by adjusting the value of _SUB1 and / or by biasing the source by changing the voltage at one or both of the V _SUP terminal 34 and the reference or ground terminal (V _SS ) 36. .

In order to dynamically control V _T of the NMOS transistor 30 in the circuit 28, the substrate voltage (V _SUB1 )
Are controlled dynamically and / or the bias of the source of the transistor 32 is controlled dynamically.
Referring to FIG. 2, various modes of operation are obtained as follows.

[0025]

[Table 1] In this table, the voltages are in volts, V _SUP is the voltage applied to the source of transistor 32, V _SS is the voltage applied to reference terminal 36, and V _SUB1 is applied to the substrate at terminal 42. Voltage. The operating modes described above are
Other than those exemplified above, this can be achieved by other combinations of V _SUP , V _SS and V _SUB1 . It is only necessary to achieve the appropriate value of V _T for the desired mode of operation.

What has been stated above is the NMOS or N char.
It relates to a tunnel transistor. N channel
In the type MOSFET, V_SSAgainst V_SUB1Is more negative
The higher the voltage, the V of the transistor_TIs further increased.
Similarly, a PMOS transistor such as transistor 32
Then V_SUPAgainst the V of that transistor_SUB2More
The more positive, the more V_TWill increase. Which tiger
Even if it is a register, its V _TIs related V_SUBIn the opposite direction
It can be reduced by changing to.

FIG. 3 shows an inverter which is an embodiment of the circuit shown in FIG.
3 is a cross-sectional view of the data circuit 46. FIG. Inverter 46 is NMO
Includes S-transistor 48 and PMOS transistor 50
No. The inverter 46 is formed on the P-type substrate 52.
You. The transistor 48 is an N + type formed on the substrate 52.
A source contact 54 is included. Transistor 48 on substrate 52
It also includes a formed N + type drain contact 56. drain
Contact 56 is drain voltage (V_D1) 58, and sauce
The contact 54 is the source voltage (V_S1) 60 for transistor 48
To supply. Source contact, outward from the surface of substrate 52
54 and drain contact 56, overlapping transistor 4
There are eight gates 62. The gate 62 is the surface of the substrate 52.
Oxide layer 64 formed outward from the gate and gate oxidation
N + type poly gate 6 formed outward from the material layer 64
Including 6. Polysilicon gate 66 is a transistor
48 to the gate voltage (V_G1) 68 is supplied. Transis
Is a P + type V formed on the substrate 52._SUB1Contact 69
Including. V_SUB170 is V _SUB1Substrate 5 by contact 69
2 is applied.

The PMOS transistor 5 of the inverter 46
0 is formed in the N-type well 72 formed in the substrate 52. Transistor 50 includes P-type drain contact 74 and P-type source contact 76 formed in well 72.
Drain contact 74 supplies V _D2 78 to transistor 50 and source contact 76 supplies V _S2 80 to transistor 50.
To supply. Outwardly from the surface of the well 72, there is a gate 81, overlying the drain contact 74 and the source contact 76. The gate 81 has a drain contact 74 and a source contact 7
6 to include an oxide layer 82 formed outward from the surface of the well 72. An N + type poly gate 84 is formed outward from the oxide layer 82. Polysilicon gate 84 provides V _G2 86 to transistor 50. For transistor 50, the N + type V _SUB2 contact 88 formed in well 72 is also shown. V _SUB2
Contact 88 provides V _SUB2 90 to transistor 50.

The inverter 46 of FIG. 3 is formed by a well-known semiconductor processing technique.

In an N-channel MOSFET, the more negative V _SUB1 with respect to V _SS , the more V _{T of} the transistor. Similarly, in the PMOS transistor, the more positive V _{SUB2 is} with respect to V _S , the more
Further, V _T increases. The V _T of the transistor can also be reduced by changing V _SUP .

This invention _applies V _SUB and V _SUP to V _T
Is used to dynamically control the V _T of the transistor so that the transistor leakage current is minimized when the transistor is in standby or suspend mode, but when it is on, high drive current is used. To have By dynamically controlling V _T by biasing the substrate and supply voltage during transistor operation,
The technical advantages of low power and high drive capability are achieved.

In the example continuing from FIGS. 1 and 2, N channels
Shape device V_TFrom the on-region of high drive current to low-power standby
To change to machine domain, that is, V_T0.2V to 0.6V
In order to change to_SUB1To
The desired V_T3 to 5 times the change in
You. Therefore, V_TTo change from 0.2V to 0.6V
Is V_SUB1Need to change about 1.2 to 2V
You. Standby transistor V _TFigure by increasing
1 as shown and discussed for the off state,
Force operation mode can be set. This process is NMOS
Alternatively, any of the PMOS transistors works. NMOS
For the transistor, V_SSAgainst V_SUB1Is further negative
By V_TWill increase. With PMOS transistor
V_TTo increase V_SUPAgainst V_SUB2To be more positive
I do. Thus, high performance when the transistor is on
, So that the power is low when it is off.
V _TCan be set dynamically.

In FIG. 5 of the above-referenced US patent application, N
A circuit diagram of an embodiment of a V _T control circuit for a MOS transistor is shown, which can be used here as well. Similar but complementary circuits can be constructed to control the V _T of the PMOS transistor.

While this invention has been described in terms of certain preferred embodiments, various modifications will be readily apparent to those skilled in the art. Therefore, it is to be understood that the appended claims should be construed as broadly as possible in light of the prior art so as to encompass all such modifications.

Further, the following items will be disclosed.

(1) In a method of adjusting the threshold voltage of a transistor online, a transistor having a channel provided in a semiconductor material having a predetermined conductivity type is prepared and the threshold voltage of the transistor is adjusted. And, online adjusting at least one of the voltage of the semiconductor material and the voltage across the transistor.

(2) The method of claim 1 wherein both the voltage of the semiconductor material and the voltage across the transistor are adjusted simultaneously.

(3) The method of claim 1, wherein the transistor is an NMOS transistor.

(4) The method according to claim 1, wherein the transistor is a PMOS transistor.

(5) The method of claim 2, wherein the transistor is an NMOS transistor.

(6) The method according to claim 2, wherein the transistor is a PMOS transistor.

(7) In the method according to the first aspect, a high drive current and a high leakage current are provided in the ON state, and a leakage current smaller in the OFF state than that in the ON state. The threshold voltage is adjusted so that

(8) In the method according to the second aspect, the leakage current is high in the ON state and smaller than the leakage current in the ON state when the drive current and the leakage current are high. The threshold voltage is adjusted so that

(9) In the method according to the third aspect of the present invention, a high drive current and a high leakage current are provided in the on state, and a leakage current smaller than that in the on state is provided in the off state. A method in which the threshold voltage is adjusted so that it becomes a current.

(10) The method according to claim 4, wherein the leakage current is high in the ON state and small in the OFF state as compared with the leakage current in the ON state. The threshold voltage is adjusted so that

(11) In the method according to claim 5, a high drive current and a high leakage current are provided in the ON state, and a high drive current and a high leakage current are provided in the OFF state as compared with the leakage current in the ON state. The threshold voltage is adjusted so that the leakage current is small.

(12) In the method according to claim 6, a high drive current and a high leakage current are provided in the on state, and a high drive current and a high leakage current are provided in the off state as compared with the leakage current in the on state. The threshold voltage is adjusted so that the leakage current is small.

(13) A transistor having a channel provided in a semiconductor material having a predetermined conductivity type, and a voltage of the semiconductor material and a voltage across the transistor in order to adjust a threshold voltage of the transistor. A transistor having means for online adjustment of at least one of the.

(14) The transistor according to claim 13, wherein the voltage of the semiconductor material and the voltage across the transistor are simultaneously adjusted.

(15) The transistor according to claim 13, wherein the transistor is an NMOS transistor.

(16) The transistor according to claim 13, wherein the transistor is a PMOS transistor.

(17) The transistor according to claim 14, wherein the transistor is an NMOS transistor.

(18) The transistor according to claim 14, wherein the transistor is a PMOS transistor.

(19) In the transistor according to claim 13, the means for adjusting online adjusts the threshold voltage so as to have a high drive current and a high leakage current when in an on state, and an off state. A transistor that allows a leakage current to be smaller when compared to the leakage current when in the ON state.

(20) In the transistor according to the fourteenth aspect, the means for adjusting online adjusts the threshold voltage so as to have a high drive current and a high leakage current when in the on state, and the off state. A transistor that allows a leakage current to be smaller when compared to the leakage current when in the ON state.

(21) In the transistor according to the fifteenth aspect, the means for adjusting online adjusts the threshold voltage so as to have a high drive current and a high leakage current when in an on state, and an off state. A transistor that allows a leakage current to be smaller when compared to the leakage current when in the ON state.

(22) In the transistor according to claim 16, the means for adjusting online adjusts the threshold voltage to have a high drive current and a high leakage current when in an on state, and an off state. A transistor that allows a leakage current to be smaller when compared to the leakage current when in the ON state.

(23) The transistor according to claim 17, wherein the means for adjusting online adjusts the threshold voltage so as to have a high drive current and a high leakage current when in an on state, and an off state. A transistor that allows a leakage current to be smaller when compared to the leakage current when in the ON state.

(24) The transistor according to claim 18, wherein the means for adjusting online adjusts the threshold voltage so as to have a high drive current and a high leakage current when in an on state, and an off state. A transistor that allows a leakage current to be smaller when compared to the leakage current when in the ON state.

(25) In a method of adjusting the threshold voltage of an integrated circuit inverter online, a first transistor having a channel provided in a semiconductor material having a predetermined conductivity type is prepared, and the predetermined conductivity is set. Second having a channel provided in a semiconductor material of opposite conductivity type to the second type
Of the semiconductor material having the predetermined conductivity type or the voltage of the semiconductor material having a conductivity type opposite to the predetermined conductivity type, and at least one end of at least one of the transistors provided in the semiconductor material. Adjusting at least one of the voltages of
A method comprising adjusting the threshold voltage of two transistors.

(26) In the method according to claim 25,
Further, the other voltage of the semiconductor material having the predetermined conductivity type or the semiconductor material having a conductivity type opposite to the predetermined conductivity type, and the semiconductor material having the predetermined conductivity type or the predetermined conductivity type. A method comprising online regulating a voltage across a transistor provided in the other of the semiconductor materials of opposite conductivity type.

(27) The method according to claim 25,
A method wherein both the voltage of the semiconductor material as well as the voltage across the transistor are adjusted simultaneously.

(28) In the method according to claim 26,
A method wherein both the voltage of the semiconductor material and the voltage across the transistor are adjusted simultaneously.

(29) In an integrated circuit inverter whose threshold voltage can be adjusted online, a first transistor having a channel provided in a semiconductor material having a predetermined conductivity type and the predetermined conductivity. A second transistor having a channel provided in a semiconductor material having a conductivity type opposite to the type; and a semiconductor material having the predetermined conductivity type or a semiconductor material having a conductivity type opposite to the predetermined conductivity type. And at least one of the voltages across at least one transistor provided in the semiconductor material is adjusted online to adjust the threshold voltage of the at least one transistor. .

(30) The integrated circuit inverter as set forth in claim 29, further comprising: a semiconductor material having the predetermined conductivity type or a semiconductor material having a conductivity type opposite to the predetermined conductivity type. Integrated with means for on-line adjusting the voltage and the voltage across the transistor provided on the other of the semiconductor material having the predetermined conductivity type or the semiconductor material having a conductivity type opposite to the predetermined conductivity type Circuit inverter.

(31) The integrated circuit inverter according to claim 29, wherein both the voltage of the semiconductor material and the voltage across the transistor are adjusted simultaneously.

(32) The integrated circuit inverter according to claim 30, wherein both the voltage of the semiconductor material and the voltage across the transistor are simultaneously adjusted.

(33) Substantially eliminates the drawbacks and problems associated with previously developed low power transistors and inverters by creating many different modes of operation using different combinations of source, reference and substrate biases. Provided is an improved multi-mode CNOS inverter which results in a circuit that can be both highly efficient with small leakage. The inverter achieves low power requirements with high performance by dynamically controlling the V _T of one or both transistors of the inverter depending on its mode of operation. When the inverter is in standby, suspend or off mode, the combination of V _SUB and V _GS is adjusted so that the value of V _T is closer to or equal to V _GS to minimize leakage current. Try to be suppressed or eliminated. Controlling the V _T of the inverter is achieved by controlling the bias of both the source voltage (V _{SU P} ) and the substrate voltage (V _SUB ) of the inverter during circuit operation. Therefore, both V _GS and V _SUB are set so that V _T increases in order to operate the inverter in the low power mode when the inverter is in standby or suspend operation. By cutting off V _SUP ,
Temporarily removing V _GS guarantees that no leaks will occur when in off mode. By dynamically modifying V _GS , the reference potential and V _SUB to give the inverter different operating modes, the inverter has a high drive current when it is on and a small amount when it is in standby or suspend mode. It becomes possible to have a leakage current.

[Brief description of drawings]

FIG. 1 is a graph showing current-voltage (IV) characteristics of an ideal switch and two MOSFETs having different V _T.

FIG. 2 is a diagram showing different operation modes of the inverter according to the present invention.

FIG. 3 is a cross-sectional view of a typical inverter embodiment that may utilize the present invention.

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[Procedure amendment]

[Submission date] April 26, 1996

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H03K 19/0948 H03K 19/094 B 19/20

Claims (2)

[Claims] 1. A method of adjusting a threshold voltage of a transistor online, wherein a transistor having a channel provided in a semiconductor material having a predetermined conductivity type is prepared,
A method comprising adjusting the voltage of the semiconductor material as well as at least one of the voltages across the transistor online to adjust the threshold voltage of the transistor. 2. A transistor having a channel provided in a semiconductor material having a predetermined conductivity type, and a voltage of the semiconductor material and a voltage across the transistor for adjusting a threshold voltage of the transistor. A transistor having means for online regulation of at least one.