JP3184265B2 - Semiconductor integrated circuit device and control method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption type semiconductor integrated circuit, and more particularly to an information processing apparatus such as a microprocessor which operates on a battery and uses a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, as an example of a semiconductor circuit to which a substrate bias is applied, a super-high-speed MOS device published by Baifukan on Feb. 10, 1987, pp. 259 to 26
There is one described on page 1 (supervised by Takuo Sugano).

[0003] The conventional general application of a substrate bias is intended to increase the speed by reducing the pn junction capacitance as in the conventional example. On the other hand, when a substrate bias is applied, the threshold value of the n-channel MOSFET is designed to rise to a practical value of about 0.6 to 1.0 V. According to this example, as the value of the substrate bias is higher, the depletion layer of the drain is expanded, and the capacity of the pn junction is reduced, so that the speed can be increased.

On the other hand, Japanese Patent Application Laid-Open No. Sho 56-56 discloses an example of a countermeasure against low power consumption of a processor using a CMOS type circuit.
As described in Japanese Patent Publication No. 42827, there is a method in which a clock instruction to a CPU portion and a circuit that does not operate is stopped by a program instruction to enter a standby mode to reduce power consumption. In a CMOS type circuit, if the clock is stopped and all switching is stopped, the power consumption will be MOS
Since only the leakage current due to the sub-threshold current of the transistor occurs, the current consumption in the standby mode can be reduced by three digits or more compared with the operation.

[0005]

The present threshold value (0.5)
A microprocessor using a MOS transistor (about V) can be operated at high speed by using a power supply voltage of 5 V, and can be operated at high speed by reducing the pn junction capacitance by applying a substrate bias as in the conventional case. there were.
However, from the viewpoint of low power consumption, since power consumption is proportional to the square of the power supply voltage, it is necessary to reduce the power supply voltage to 5 V or less. In particular, in the case of battery operation, it is necessary to lower the voltage to about 1V. In addition, as the MOS transistor becomes finer, the withstand voltage of the element also decreases. Therefore, it is necessary to lower the power supply voltage.

On the other hand, the delay time of the CMOS circuit is the time for charging and discharging the charge of the load capacitance with the drain current, and is proportional to the power supply voltage / (power supply voltage-threshold) square. Therefore, the delay time is inversely proportional to the power supply voltage at a high power supply voltage at which the threshold value can be ignored, but at a low voltage at which the threshold value cannot be ignored, the delay time sharply increases as the power supply voltage decreases. At the time of such a low-voltage operation, when the substrate bias is applied, the threshold value increases, so that there is a problem that the operation speed is rather reduced. Therefore, at the time of low-voltage operation, basically, no substrate bias is applied, and the threshold value of the MOS transistor must be kept low.

On the other hand, lowering the threshold voltage requires
Another problem occurs that the leakage current increases due to the subthreshold current of the MOS transistor. This leak current increases exponentially to about 47 times each time the threshold voltage is lowered by 0.1 V at room temperature. For example, when the threshold value is lowered from 0.5 V to 0.3 V, the leak current becomes about 2200 times. In the case of a microprocessor having a scale of several hundred thousand elements, the leakage current is 10% or less as compared with the current during operation, and the power consumption does not increase much.
However, the current consumption in the standby mode in which only the clock is stopped as in the conventional example is exactly due to this leak current. Therefore, when the threshold value is lowered from 0.5 V to 0.3 V, the leak current directly increases by 2200 times. . Therefore, when the threshold voltage is lowered, merely stopping the clock does not sufficiently reduce the current consumption, causing a problem that the battery backup time in the standby mode is significantly reduced.

The present invention has been made on the basis of the results of the study by the present inventors as described above. The purpose of the present invention is to enable high-speed operation even with a low power supply voltage during operation, and to provide a standby mode. An object of the present invention is to provide an information processing device that consumes less power due to leakage current.

[0009]

The above-mentioned problem is caused by the fact that the threshold value of the MOS transistor is low even in the standby mode in which the switching operation is not performed.

Therefore, if the threshold value is lowered during operation to enable high-speed operation even at a low power supply voltage, and if the leakage current can be reduced by increasing the threshold value in the standby mode, high-speed operation at the time of operation at a low power supply voltage is possible. And low power consumption in the standby mode. Therefore, the threshold value of the MOS transistor itself is set low, and the threshold value is raised by applying a substrate bias in the standby mode.

It is needless to say that the substrate bias at this time needs to be set so that the amount of reduction of the leak current due to the rise of the threshold value is larger than the current consumption of the substrate bias circuit.

[0012]

In operation, since the threshold value is low, high-speed operation is possible even at a low voltage. On the other hand, in the standby mode, the threshold voltage is high, so that the leak current can be greatly reduced. As described above, since the leakage current cannot be stopped simply by stopping the clock when the circuit is on standby, the threshold value is increased by controlling the substrate bias to reduce the power consumption, and the leakage current is reduced. Conversely, when the threshold value is changed, the operation speed of the transistor is changed. Therefore, a malfunction may occur unless the operation clock is controlled.
According to the present invention, a high-speed operation, low power consumption, and high reliability of a semiconductor integrated circuit device can be provided by controlling the substrate bias and the operation clock in conjunction with each other. As a specific example, the substrate bias and the operation clock are controlled by a common control signal, or the substrate bias is controlled based on the operation clock frequency.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a typical embodiment of the present invention, and its basic concept will be described. First, in order to maintain high-speed operation at a low power supply voltage, MOS transistors (MN, MP)
Is set low. On the other hand, when there is no keyboard input for a certain period of time or when the state of the lowest power consumption continues for a certain period of time, the standby mode is entered by a program command or an external control signal.

In the standby mode, the clock control circuit 3 stops the clock Ckm supplied to the MPU (microprocessor unit) 1 and simultaneously operates the operation mode switching signal A
To operate the substrate bias circuits 2-1 and 2-2,
A negative substrate bias V _Bn is applied to the NMOS transistor (MN), and a positive substrate bias V _Bp than the power supply is applied to the PMOS transistor (MP). By applying the substrate bias, the threshold value of the MOS transistor increases,
The leak current decreases as an exponential function of the threshold rise. That is, when a substrate bias is applied, the sub-threshold characteristic is improved and the leak current is reduced. The more the microprocessor has a larger number of elements, the greater the amount of reduction in the leak current, which is equal to or greater than the current consumption of the substrate bias circuits 2-1 and 2-2. With the above operation, an information processing device that can operate at high speed at a low voltage and consumes low power in the standby mode can be realized.

Next, the embodiment of FIG. 1 will be described in detail with reference to the drawings. As shown in FIG. 1, a microprocessor is configured by integrating the MPU 1, the substrate bias circuits 2-1 and 2-2, the clock control circuit 3, and the like on one chip. The MPU 1 includes an instruction fetch unit, an instruction decoder, an instruction execution unit, and the like, as is well known to those skilled in the art. The MPU 1 is composed of a CMOS circuit and has an NMO
The threshold value of the S transistor is set to 0.3 V, the threshold value of the PMOS transistor is set to -0.3 V, and the power supply voltage Vc
High-speed operation is possible even when c is as low as 1 V.
A supply terminal of the power supply voltage Vcc of the microprocessor chip is connected to a battery (not shown).
cc is supplied from the battery. In addition, terminals are provided on each of the NMOS and PMOS substrates (or well regions) of the MPU 1 to apply a substrate bias.

An operation mode switching signal A in response to a program command or an external signal is applied to NMOS and PMOS substrate bias circuits 2-1 and 2-2 to control the levels of substrate biases V _Bp and V _Bn . The mode can be switched under the conditions such as the presence or absence of an input from the keyboard and the magnitude of current consumption. By controlling the clock control circuit 3 with the operation mode switching signal A and the frequency switching signal B, M
The on / off and frequency of the clock supplied to PU1 are controlled.

FIG. 2 shows changes in the clock and the substrate bias in each of the normal operation mode, the low power consumption mode, and the standby mode.

In the normal operation mode, a high-speed clock of 16 MHz is supplied, and no substrate bias is applied. Accordingly, since the absolute value of the threshold value of each of the N and P channel MOS transistors remains at 0.3 V, the low power supply voltage V of 1 V
High speed operation is possible with cc. On the other hand, since the threshold value is low, a steady leakage current due to the subthreshold current flows. However, in the case of a 100,000 gate microprocessor, the consumption current due to the steady leakage current is 1/10 of the consumption current due to the switching operation. Since it is below, the current consumption during the operation does not change much.

In the low power consumption mode, the clock control circuit 3 responds to the frequency switching signal B in response to the frequency switching signal B so that the clock frequency is divided by 2 to 8 MHz.
z. NMOS substrate bias V _Bn of -0.5 V and +1.5 V by substrate bias circuits 2-1 and 2-2
_Is applied to raise the threshold value of the MOS transistor to about 0.5 V in absolute value. Since the operation speed is low, there is no problem in operation even if the threshold value is increased. By this low power consumption mode, the switching current can be reduced to 1/2 and the leakage current can be reduced to about 1/2200.

Since no operation is performed in the standby mode, the clock is stopped. When the clock is stopped, the switching operation stops at all. Further, in order to obtain a threshold value increased in absolute value, substrate biases V _Bn and V _Bp are similarly applied. Therefore, the current consumption of the CMOS circuit is only a leak current due to an extremely small subthreshold current corresponding to a high threshold value. Since the absolute value of the threshold is increased to about 0.5 V by the application of the substrate bias, the leak current can be suppressed to about 1/2200 of the operation.

Next, an embodiment of the substrate bias circuits 2-1 and 2-2 is shown in FIG. When the operation mode switching signal becomes 1, a clock signal is supplied to the substrate bias circuit, and the operation starts. A charge pumping circuit is used to generate a negative voltage for NMOS and a voltage higher than a power supply voltage for PMOS. When power supply voltage Vcc is 1V, for NMOS-
Bias voltages V _Bn and V _{Bp of} about 0.5 V and about +1.5 V for PMOS can be generated. This clock signal is a clock,
Since a basic clock that always operates for a microprocessor or the like is used, a new oscillation circuit is unnecessary,
The current consumption for applying the substrate bias is about 100 μA. In this embodiment, the substrate bias circuit is provided on the basis of a single power supply. However, in the case of battery operation, a battery dedicated to the substrate bias may be provided.

Next, an embodiment of the clock control circuit 3 is shown in FIG.
Shown in The basic clock signal is such that the operation mode switching signal A is 0
The clock output CK through the clock control circuit 3
m is supplied to the MPU 1. In the standby mode, the operation mode switching signal becomes 1, and the clock output is not supplied to MPU1. One of the clock inputs enters a frequency dividing circuit by a T flip-flop, and the other passes through to a clock frequency switching circuit. When the clock frequency switching signal B is 1, the high-speed clock is supplied to the MPU 1 as it is, and when the clock frequency switching signal B is 0, the low-speed clock for the low power consumption mode, which is divided by half, is supplied.

FIG. 5 shows an embodiment of an element structure for applying a substrate bias to a CMOS transistor. Normal C
Although it is possible to apply a bias to the MOS structure without grounding the substrate, the packaging becomes complicated,
There is a problem that noise is easily picked up. In order to apply substrate biases V _Bn and V _Bp to the N-channel and P-channel MOS transistors with the P-type semiconductor substrate 1 grounded, an N-channel M
The OS substrate p-well 3 is insulated from the substrate 1 by a P-channel MOS substrate n epitaxial layer 2. A negative voltage is applied to the p-well 3 as the NMOS substrate bias V _Bn through the substrate bias terminal 5-1 and a positive voltage is applied to the n-epitaxial layer 2 as the PMOS substrate bias V _Bp through the substrate bias terminal 5-2. , All the bias relations are reverse biases of the pn junction and are insulated from each other.

Since the substrate bias voltage that can be generated with a low power supply voltage is low, the device structure is devised. P-type high concentration region 7 and P just below the gate electrode of N-channel MOS
The n-type high-concentration regions 8 immediately below the gate electrode of the channel MOS are provided at positions deeper than the thickness of the surface depletion layer when the channel inversion layer is formed. Therefore, when no substrate bias is applied, the threshold is not affected. When a substrate bias is applied, the depletion layer spreads to high concentration regions 7 and 8,
Since the effective substrate concentration is high, the threshold value greatly changes depending on the substrate bias. FIG. 6 shows changes in the substrate bias and the threshold value. The surface concentration of the p-type well 3 is 5 × 10 ¹⁶ /
The density of the cm ³ , p-type high concentration region 7 is set to 3 × 10 ¹⁷ / cm ³ . When the p-type high-concentration region 7 is not provided, the change in the threshold value is small even when the substrate bias is applied because the substrate constant is small, and the control width of the threshold value is too small at a low power supply voltage.
By providing the p-type high-concentration region 7, the substrate constant becomes twice or more and the threshold value can be largely controlled.
By applying a substrate bias of 0.5 V, the threshold is reduced to about 0.5.
2V can be increased.

Next, as another embodiment of the present invention, FIG. 7 shows a basic configuration for automatically switching the substrate bias according to the clock frequency. A change in the frequency of the clock signal is detected by the substrate bias control circuit 2-0, and the substrate bias circuit 2-
The values of the substrate biases V _Bn and V _Bp generated from 1 and 2-2 are switched. As a result, the normal mode, the low power consumption mode, and the standby mode of the substrate bias can be switched only by the clock signal.

FIG. 8 shows an embodiment of the substrate bias control circuit 2-0. The voltage Vc is generated by the charge pump circuit from the clock signal. The value of Vc is proportional to the frequency of the clock, and can be adjusted by the coupling capacitance _Cc and the load resistance _Rb . Vc when the clock frequency is high
Is high, and the signal at point a goes low through the passage of the MOS transistor MN1, so that the ring oscillator does not oscillate and the substrate biases V _Bn and V _Bp are not applied. Next, when the clock frequency is low, the Vc value is low and MN1 does not pass through, so the point a goes high, the ring oscillator oscillates, and the substrate biases V _Bn and V _Bp are applied.
Of course, when the clock signal stops, the point a becomes high and the substrate biases V _Bn and V _Bp are applied. In this embodiment, since the ring oscillator is oscillated to generate the substrate bias, the power consumption in the standby mode is as large as about 300 μA, but the effect is large because the amount of reduction of the leak current is large. Further, since the substrate biases V _Bn and V _Bp automatically change according to the clock frequency, there is no need to provide a specific command or control signal.

FIG. 9 shows a change in drain current characteristic of a MOS transistor depending on a threshold value. The leak current is a drain current when the gate voltage is 0V. Threshold
When the voltage is increased from 0.3 V to 0.5 V, the leakage current becomes 44
It decreases from nA to about 1/200. Considering that a microprocessor is composed of MOS transistors having a threshold voltage of 0.3 V and a leakage current of 44 nA, when the number of gates of the microprocessor is about 100,000, the leakage current is 4. 4mA
Reach When a substrate bias of 0.5 V is applied, the threshold value rises to 0.5 V, and the leakage current decreases to about 20 pA, which is almost the same as that of a transistor whose original threshold value is 0.5 V. On the other hand, the current consumption of the substrate bias circuit is 1
Since there is about 00 μA, the current consumption is 102 μA in total. FIG. 10 summarizes a comparison between the conventional example and the present embodiment in which the threshold values are 0.5 V and 0.3 V with respect to the maximum operating frequency and the current consumption of the microprocessor.

[0029]

According to the present invention, since the threshold voltage can be set low, high-speed operation can be performed even at a low power supply voltage. In a low-speed operation or a standby mode, the threshold voltage is increased by applying a substrate bias. Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 shows a block diagram of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 shows waveform changes of respective portions in each mode of the semiconductor integrated circuit of FIG.

FIG. 3 shows an embodiment of a substrate bias circuit of the semiconductor integrated circuit of FIG. 1;

FIG. 4 shows an embodiment of a clock control circuit of the semiconductor integrated circuit of FIG.

FIG. 5 is a sectional view of a CMOS structure of the semiconductor integrated circuit of FIG. 1;

FIG. 6 shows a relationship between a substrate bias and a threshold voltage of a MOS transistor.

FIG. 7 shows a block diagram of a semiconductor integrated circuit according to another embodiment of the present invention.

8 shows an embodiment of the substrate bias control circuit and the substrate bias circuit of FIG.

FIG. 9 shows a relationship between an N-channel MOS transistor, a threshold voltage, and a leak current.

FIG. 10 shows a comparison between the conventional technology and the present invention with respect to the maximum operating frequency and the current consumption of the microprocessor.

[Explanation of symbols]

V _Bn ... N-channel MOS substrate bias, V _Bp ... P-channel MOS substrate bias, CKm ... clock signal for the microprocessor, CKb ... substrate bias generating clock signals.

Continuing from the front page (72) Inventor Makoto Hanawa 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory, Ltd. (56) reference Patent Sho 61-52723 (JP, a) JP Akira 56-85128 (JP, a) JP flat 3-82151 (JP, a) (58 ) investigated the field (Int.Cl. ⁷ , DB name) G06F 1/04 H01L 27/06

Claims (13)

(57) [Claims] 1. A logic circuit comprising a MOS transistor, a substrate bias circuit for changing a substrate potential of the MOS transistor, and a clock control circuit for controlling a frequency of a clock signal supplied to the logic circuit. , The two states of the normal operation mode and the standby mode are reduced
Controlling the substrate bias circuit and the clock control circuit on the basis of the control signal also provided in the standby mode.
The absolute value of the threshold value is equal to the M in the normal operation mode.
Becomes larger than the absolute value of the threshold value of the OS transistor
Control the substrate bias circuit so that
When the frequency of the clock signal is zero,
Control the clock control circuit so that supply stops
Semiconductor integrated circuit device. 2. The logic circuit includes a PMOS transistor and an NMOS transistor connected in series with the PMOS transistor. The substrate bias circuit includes a first substrate bias circuit for controlling a substrate potential of the PMOS transistor; N above
2. The semiconductor integrated circuit device according to claim 1, further comprising a second substrate bias circuit for controlling a substrate potential of the MOS transistor. 3. A method for controlling a semiconductor circuit to which a clock signal is supplied, wherein the semiconductor circuit includes a MOS transistor, and includes a first mode and a second mode as modes of the semiconductor circuit. A threshold value of the MOS transistor and a frequency of the clock signal are controlled based on a control signal for controlling switching between the first mode and the second mode. In the first mode, the clock signal is supplied. In the second mode, the supply of the clock signal is stopped, and the absolute value of the threshold value of the MOS transistor becomes larger than the absolute value of the threshold value of the MOS transistor in the first mode. Control method for a semiconductor circuit controlled as described above. 4. The method according to claim 3, wherein said semiconductor circuit is a microprocessor. 5. A semiconductor circuit comprising a MOS transistor, clock supply means for supplying a clock signal to the semiconductor circuit, and potential control for controlling a substrate potential of the MOS transistor between first and second potentials. The clock supply means has a function of switching the frequency of the clock signal; the potential control means has a function of switching the substrate potential; and the timing of switching the frequency by the clock supply means and The switching timing of the substrate potential by the potential control means is synchronized. In the first state, the clock supply means supplies a clock signal of a first frequency to the semiconductor circuit. Controlling the substrate potential of the transistor to the first potential; and supplying the clock in the second state. Stage stops the supply of the semiconductor circuit supplies a second clock signal having a frequency lower than the first frequency or the clock signal to the semiconductor circuit, said potential control means the MOS
Semiconductor wherein the substrate potential of the transistor is controlled to the second potential to make the absolute value of the threshold value of the MOS transistor larger than the absolute value of the threshold value of the MOS transistor in the first state. Integrated circuit device. 6. The semiconductor integrated circuit device according to claim 5, wherein the switching timing of the frequency and the switching timing of the substrate potential are controlled by a signal formed based on the same control signal. 7. A microprocessor including a MOS transistor, a clock control circuit for controlling a frequency of a clock signal supplied to the microprocessor, and a substrate bias circuit for controlling a substrate potential of the MOS transistor. A clock control circuit that controls a frequency of a clock signal supplied to the microprocessor based on a program command or an external control signal; a substrate bias circuit that controls a substrate potential of the MOS transistor; In the above, the clock control circuit supplies a clock signal of a first frequency to the microprocessor, the substrate bias circuit controls the substrate potential of the MOS transistor to a first potential, and in the second state, The clock control circuit is A clock signal having a second frequency lower than the first frequency or a supply of the clock signal to the microprocessor is stopped, and the substrate bias circuit changes the substrate potential of the MOS transistor to a second potential. Wherein the absolute value of the threshold value of the MOS transistor in the first state is made larger than the absolute value of the threshold value of the MOS transistor in the first state. 8. The substrate bias circuit changes a substrate potential of the MOS transistor according to a first control signal formed based on the program command or the external control signal, thereby changing a threshold voltage of the MOS transistor. 8. The semiconductor integrated circuit device according to claim 7, wherein the clock control circuit controls the frequency of the clock signal by a second control signal formed based on the program command or the external control signal. 9. A logic circuit including a MOS transistor, a clock control circuit for controlling a frequency of a clock signal supplied to the logic circuit, and a substrate bias circuit for controlling a substrate potential of the MOS transistor, The clock control circuit supplies a clock signal of a first frequency to the logic circuit in a first state, and supplies a clock signal of a second frequency lower than the first frequency to the logic circuit in a second state. And the supply of the clock signal to the logic circuit can be stopped.
A semiconductor integrated circuit device capable of controlling the substrate voltage of the MOS transistor so that the absolute value of the threshold voltage of the OS transistor is higher than the absolute value of the threshold voltage of the MOS transistor in the first state. 10. The drain current flowing when the gate voltage of the MOS transistor is 0V in the second state, wherein the gate voltage of the MOS transistor is 0V in the first state.
A semiconductor integrated circuit device smaller than a drain current flowing at the time of (1). 11. The logic circuit according to claim 9, wherein the logic circuit includes a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type connected in series with the first MOS transistor. The circuit includes a first substrate bias control circuit for controlling the substrate potential of the first MOS transistor and a second substrate bias control circuit for controlling the substrate potential of the second MOS transistor. . 12. The device according to claim 11, wherein the first MOS transistor is a PMOS transistor,
The second MOS transistor is an NMOS transistor, wherein the first substrate bias control circuit sets the substrate potential of the first MOS transistor higher than the source potential of the first MOS transistor in the second state. 2 is a semiconductor integrated circuit device, wherein in the second state, the substrate potential of the second MOS transistor can be lower than the source potential of the second MOS transistor. 13. The semiconductor integrated circuit device according to claim 9, wherein said logic circuit is a microprocessor.