JPH09205205A - Method of manufacturing MOS semiconductor device and MOS semiconductor device - Google Patents

Abstract

Kind Code: A1 A semiconductor device in which a low-concentration impurity diffusion layer (offset) is provided between a channel part of a MOS transistor and a source and a drain, and the offset can be set to an arbitrary value. And make it uniform. At the same time as the formation of a gate electrode 304, a conductive film 305 is formed by photolithography in a region (cover region) which covers portions to be a source and a drain later, and a low concentration diffusion layer 306 is formed. An insulating film 307 is deposited and the insulating film 307 is gradually removed from the top using a chemical mechanical polishing (CMP) technique to expose the top of the conductive film 305. As a result, the insulating film 307 remains between the gate electrode 304 and the conductive film 305, and ion implantation is performed using this as a spacer to form the source / drain regions 310. Since the offset length is determined by one-time photolithography, the electrical characteristics are uniform, and the degree of freedom in setting the breakdown voltage between the source and drain can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a low-concentration impurity diffusion layer (hereinafter referred to as a MOS-type transistor) between a channel portion and a source and a drain made of a high-concentration impurity diffusion layer. This is tentatively called an offset, and Lightly Doped Drain.
(Often abbreviated as LDD)), a high breakdown voltage semiconductor device (hereinafter, abbreviated as a semiconductor device having an offset) in which an electric field relaxation effect is obtained to improve a breakdown voltage between a source and a drain. It relates to a manufacturing method.

[0002]

2. Description of the Related Art Conventionally, there are the following two types of methods for manufacturing a semiconductor device having an offset. One is a so-called sidewall method in which an offset is provided by providing a sidewall spacer on the side wall of the gate electrode, and the other is a so-called mask offset method in which an offset is formed by covering the gate electrode with a photoresist.

First, a so-called sidewall method will be described with reference to FIG.

A gate insulating film 102 is formed on a semiconductor substrate 101.
And then the gate electrode 103 is formed. Ion implantation 104 is performed using the gate electrode 103 as a mask to form a low-concentration impurity diffusion layer 105 in the semiconductor substrate 101 (FIG. 1A). Next, an insulating film 106 is deposited (FIG. 2b),
This insulating film 106 is removed by anisotropic etching. After etching, sidewall spacers 107 remain on the sidewalls of the gate electrode (FIG. 1c). Ion implantation 108 is performed using the sidewall spacer 107 and the gate electrode 103 as a mask to form a high-concentration impurity diffusion layer 109. Subsequently, an interlayer insulating film is formed, a connection hole is opened in the interlayer insulating film, and a metal wiring is formed to complete the semiconductor device.

Next, the so-called mask offset method is shown in FIG.
This will be described with reference to FIG.

A gate insulating film 202 is formed on a semiconductor substrate 201.
And then the gate electrode 203 is formed. Ion implantation is performed using the gate electrode 203 as a mask, and the semiconductor substrate 2
In FIG. 2, a low-concentration impurity diffusion layer 204 is formed (FIG.
a). Next, a photoresist 205 is formed so as to cover the gate electrode 203, and using this as a mask, ion implantation 206 is performed.
By doing so, a high-concentration impurity diffusion layer 207 is formed (FIG. 2B). Then, after removing the photoresist 205, a semiconductor device is completed in the same manner as the sidewall method described above.

In both the sidewall method and the mask offset method, a low-concentration impurity diffusion layer (offset) is provided between the channel and the high-concentration impurity diffusion layer to mitigate the electric field in the horizontal direction so that the source-drain of the transistor is The breakdown voltage of is improved. Further, by providing the offset, injection of hot carriers into the gate insulating film is suppressed, and there is also an effect of suppressing characteristic variation of the semiconductor device.

[0008]

However, in the sidewall method, the magnitude of the offset, that is, the distance in the horizontal direction (direction connecting the channel and drain) of the low-concentration impurity diffusion layer is small, and a sufficient breakdown voltage cannot be obtained. There was a problem that sometimes. That is, the size of the offset is determined by the length of the sidewall in the horizontal direction (direction connecting the source and drain), and even if the horizontal length of the sidewall is large, it is about the thickness of the gate electrode. Even if I tried to increase the offset, there was a limit.

Further, in the mask offset method, although it is possible to provide an offset of an arbitrary size to improve the breakdown voltage, an ion implantation mask for forming a high-concentration impurity diffusion layer (see the photo of FIG. 2). Since the resist 205) is formed by photolithography, there is a problem in that misalignment occurs during exposure and the magnitude of offset changes, resulting in non-uniform electrical characteristics.

[0010]

According to the method of manufacturing a semiconductor device of the present invention, at least a step of forming a gate insulating film on a semiconductor layer and a portion of the semiconductor layer to be an impurity diffusion layer of a source and a drain later are performed. A step of forming a region to be covered and a gate electrode by one-time photolithography; a step of depositing an insulating film; and an insulating film so that the top of the region is exposed and the insulating film between the region and the gate electrode remains. And removing the region leaving the gate electrode and the insulating film, and implanting impurity ions into the semiconductor layer below the removed region. An object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device having a high withstand voltage and excellent electrical property uniformity.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of a method for manufacturing a semiconductor device of the present invention will be described in detail with reference to FIGS.

3 and 4 are process sectional views showing a method of manufacturing a semiconductor device according to the present invention. First, the first insulating film 302 is formed over the semiconductor layer 301, and then the first insulating film 30 is formed.
A first conductive film 303 was deposited on 2 (FIG. 3a). In this embodiment, the semiconductor layer 301 is single crystal silicon (Si), and the first insulating film 302 is silicon oxide (SiO ₂ ) obtained by thermally oxidizing the surface of single crystal silicon. The first insulating film 302 is a gate insulating film of a MOS transistor.
Polycrystalline silicon was used for the first conductive film 303.

Next, the first conductive film 303 is processed and formed by one-time photolithography, and the first conductive film region 3 is formed.
04 and the second conductive film region 305 were simultaneously formed. First
Conductive film region 304 is a gate electrode of a MOS transistor, and the second conductive film region 305 is a high-concentration impurity diffusion layer (source and drain of a MOS transistor) later.
This is a region that covers the portion where is formed (hereinafter, abbreviated as a cover layer). Further, ion implantation is performed from above the first conductive film region 304 and the second conductive film region 305 to form the semiconductor layer 30.
A low-concentration impurity diffusion layer 306 was formed in FIG.
b).

As conditions for ion implantation when forming a low-concentration impurity diffusion layer, the implantation amount is preferably 10 ¹⁰ to 1
0 ¹⁴ (1 / cm ² ), more preferably 10 ¹² to 10 ¹³ (1
/ Cm ² ). The implantation energy is preferably 10-
It is 150 keV, more preferably 30 to 100 keV.
The ion species are B ⁺ , BF ₂ ⁺ , P ⁺ and As ⁺ ,
There is no particular limitation as long as it is a substance that can function as a donor or an acceptor on the semiconductor substrate. These ion implantation conditions are an example, and generally required M
It is determined by the breakdown voltage and capability of the OS transistor.

For example, when the ion species is BF ₂ ⁺ , the implantation amount is preferably 10 ¹⁰ to 10 ¹⁴ (1 / cm ² ), more preferably 10 ¹² to 10 ¹³ (1 / cm ² ), and further preferably. It is 4 * 10 < ¹² > -10 < ¹³ > (1 / cm < ² >). 10
^If it is less than ¹⁰ (1 / cm ² ), the resistance of the diffusion layer becomes too large and the ability as a MOS transistor becomes insufficient.
In addition, the desired conductivity type may not be obtained in some cases. This is because if it is larger than 10 ¹⁴ (1 / cm ² ), the electric field relaxation effect becomes small and a sufficient breakdown voltage cannot be secured in many cases. The implantation energy is not particularly limited, but is preferably 20 to 60 keV, more preferably 30 to 50 keV, and further preferably 40 ± 5 keV. This is because if it is less than 20 keV, impurities may not penetrate the gate insulating film.
This is because if it is higher than 60 keV, the mask layer for ion implantation may penetrate. Of course, if such an inconvenience does not occur, the implantation energy can be freely set in accordance with the required characteristics of the MOS transistor, and even in the case of another ion species or another ion implantation step, Are the same.

When the ion species is B ⁺ , the dose is preferably 10 ¹⁰ to 10 ¹⁴ (1 / cm ² ), more preferably 10
¹² to 10 ¹³ (1 / cm ² ), more preferably 4 × 10
^{It is 12} to 10 ¹³ (1 / cm ² ). The implantation energy is not particularly limited, but is preferably 10 to 40 keV, more preferably 20 to 30 keV.

When the ionic species is P ⁺ , the dose is preferably 10 ¹⁰ to 10 ¹⁴ (1 / cm ² ), more preferably 5 ×.
10 ^{12 to} 5 × 10 ¹³ (1 / cm ² ), more preferably 1
It is 0 ¹³ to 4 × 10 ¹³ (1 / cm ² ). The implantation energy is not particularly limited, but preferably 40 to 80 keV,
More preferably 50 to 70 keV, even more preferably 60
± 5 keV.

When the ion species is As ⁺ , the implantation amount is preferably 10 ¹⁰ to 10 ¹⁴ (1 / cm ² ), more preferably 5
× 10 ^{12 to} 5 × 10 ¹³ (1 / cm ² ). The implantation energy is not particularly limited, but preferably 40 to 80 ke
V, more preferably 50 to 70 keV.

Next, a second insulating film 307 was deposited (FIG. 3c). The second insulating film 307 is a so-called spacer insulating film, a part of which will later serve as a spacer for offset formation. The second insulating film 307 is silicon oxide deposited by vapor deposition. After that, the second insulating film 307 was gradually removed from the top using a chemical mechanical polishing (CMP) technique to expose the top of the second conductive film region 305. At this time, a part of the second insulating film 307 remains between the first conductive film region 304 and the second conductive film region 305,
This is a spacer 308 for separating the first conductive film region 304 and a high-concentration impurity diffusion layer to be formed later (forming an offset) (FIG. 3d).

Next, a photoresist 309 is formed so as to cover the first conductive film region 304 and expose the second conductive film region 305, and then the second conductive film region 3 is formed.
05 was removed (Fig. 3e). Ions were implanted into a portion of the semiconductor layer 301 not covered with the first conductive film region 304 and the spacer 308 to form a high-concentration impurity diffusion layer 310 (FIG. 4A).

As an ion implantation condition for forming a high-concentration impurity diffusion layer, the implantation amount is preferably 10 ¹⁴ -1.
0 ¹⁷ (1 / cm ² ), more preferably 10 ¹⁵ to 10 ¹⁶ (1
/ Cm ² ). The implantation energy is preferably 10-
It is 150 keV, more preferably 30 to 100 keV.
The ion species are B ⁺ , BF ₂ ⁺ , P ⁺ and As ⁺ ,
There is no particular limitation as long as it is a substance that can function as a donor or an acceptor on the semiconductor substrate. These ion implantation conditions are merely examples, and are determined by generally required breakdown voltage, capability, and the like.

For example, when the ion species is BF ₂ ⁺ , the implantation amount is preferably 10 ¹⁴ to 10 ¹⁷ (1 / cm ² ), more preferably 10 ¹⁵ to 10 ¹⁶ (1 / cm ² ), and further preferably. It is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ (1 / cm ² ). 10 ¹⁴
This is because if it is less than (1 / cm ² ), the resistance of the diffusion layer (parasitic resistance of the source and drain) increases and the performance of the transistor may be hindered. Also, 10 ¹⁷ (1 / c
If it is larger than m ² ), it becomes difficult to recover the crystal defects due to the ion implantation in the subsequent step, and the characteristics of the transistor may be hindered due to junction leakage or the like. The implantation energy is not particularly limited, but is preferably 20 to 60 keV, more preferably 30 to 50 keV,
More preferably, it is 40 ± 5 keV. This is because if it is less than 20 keV, impurities may not penetrate the gate insulating film. Also, if it is higher than 60 keV, it may penetrate to the mask layer for ion implantation.

When the ion species is B ⁺ , the implantation amount is preferably 10 ¹⁴ to 10 ¹⁷ (1 / cm ² ), more preferably 10
¹⁵ to 10 ¹⁶ (1 / cm ² ), more preferably 1 × 10 ¹⁵
It is up to 8 × 10 ¹⁵ (1 / cm ² ). The injection energy is
Although not particularly limited, it is preferably 20 to 60 keV, more preferably 30 to 50 keV, further preferably 40 ± 5 kV.
eV.

When the ionic species is P ⁺ , the injection amount is preferably 10 ¹⁴ to 10 ¹⁷ (1 / cm ² ), more preferably 10
¹⁵ to 10 ¹⁶ (1 / cm ² ), more preferably 1 × 10 ¹⁵
It is up to 8 × 10 ¹⁵ (1 / cm ² ). The injection energy is
Although not particularly limited, it is preferably 50 to 90 keV, more preferably 60 to 80 keV, further preferably 70 ± 5 kV.
eV.

When the ionic species is As ⁺ , the implantation amount is preferably 10 ¹⁴ to 10 ¹⁷ (1 / cm ² ), more preferably 1
0 ¹⁵ to 10 ¹⁶ (1 / cm ² ), more preferably 1 × 10
^{It is 15} to 8 × 10 ¹⁵ (1 / cm ² ). The injection energy is
Although not particularly limited, it is preferably 30 to 70 keV, more preferably 40 to 60 keV, further preferably 50 ±.
It is 5 keV.

After that, an interlayer insulating film 311 is deposited, a heat treatment for activating impurities is performed, a connection hole is opened, and a metal wiring 312 is formed to complete a semiconductor device (FIG. 4).
b).

In this embodiment, the semiconductor layer 301 is made of single crystal silicon. However, in the case of manufacturing a polycrystalline silicon thin film transistor, for example, the semiconductor layer 301 is made of polycrystalline silicon formed on a glass or quartz glass substrate. Alternatively, in the case of manufacturing an amorphous silicon thin film transistor, the semiconductor layer 301 may be amorphous silicon formed on a glass or quartz glass substrate.

In addition, the single crystal silicon of the semiconductor layer 301 can be used as an SOI (Silic
on on Insulator) and SOS (Sili)
The effect obtained by the method of the present invention does not change even with single crystal silicon grown on a con on Saphire).

However, when actually manufacturing a semiconductor device by the method of the present invention using a single crystal silicon substrate, a method for element isolation must be taken into consideration. This causes a step other than the portion included in the drawing shown in the present embodiment, that is, the element isolation region, and particularly chemical mechanical polishing (C
This is because the first conductive layer region 304 on the element isolation insulating film becomes thin when using (MP) and cannot be used for wiring in the element isolation region. Using a single crystal silicon substrate, LOCOS (Local Oxidation)
The case where the element isolation is performed by (n Of Silicon) will be described later as another embodiment.

Further, although chemical mechanical polishing (CMP) is used to remove the second insulating film 307 in this embodiment, the top of the second conductive film region 305 is exposed and the spacer 308 is used.
Other techniques may be used as long as the remaining second insulating film 307 having a film thickness that can serve as a mask for preventing ion implantation is left. For example, as shown in FIG. 3C, with the second insulating film 307 deposited, a photoresist is applied on the entire surface under the condition that the etching rate of the photoresist and that of the second insulating film 307 are almost the same. The so-called resist etch back method of etching also serves the purpose of the present invention.

Furthermore, in this embodiment, the first conductive layer 3 is used.
Polycrystalline silicon was used for 03, but this has a silicide of a refractory metal such as molybdenum (Mo), tungsten (W), titanium (Ti), or a laminated structure of these and polycrystalline silicon. There are things.

In the semiconductor device manufacturing method of this embodiment, the positional relationship between the gate electrode and the source / drain, that is, MO
The offset lengths of the source and the drain in the S-type transistor are determined by one-time photolithography for processing and shaping the first conductive film 303 to form the first conductive film region 304 and the second conductive film region 305. . Therefore, the distance (offset length) between the gate electrode and the source / drain is
Unlike the conventional mask offset method, the semiconductor device can be always maintained constant regardless of the alignment accuracy of the exposure apparatus, and thus a semiconductor device having uniform electric characteristics can be manufactured.
Moreover, unlike the conventional sidewall method, it is possible to arbitrarily determine the magnitude of the offset, and it is possible to easily obtain a source-drain breakdown voltage according to need.

A second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described below in the order of manufacturing steps with reference to FIG. The second embodiment is an example in which a silicon oxide film for element isolation is formed on a single crystal silicon substrate by the LOCOS method and then the manufacturing method of the present invention is applied. This is because when the method of the first embodiment described above is applied to the manufacture of a semiconductor device using a single crystal silicon substrate in which a silicon oxide film for element isolation must be formed so as to rise from the substrate, Since the wiring portion extending from the gate electrode in the same layer as the electrode is on the silicon oxide film for element isolation (not shown in FIGS. 3 and 4 described in the first embodiment), a planarization technique is used. This wiring portion is an example of a manufacturing method that solves this problem because the wiring portion may become thin or disappear when used.

After forming a thin silicon oxide film on the single crystal silicon substrate 501, the exposed silicon portion is thermally oxidized by using the silicon nitride film as a mask, and then the silicon nitride film is removed by a so-called LOCOS method, which is a so-called LOCOS method. , A gate insulating film 503 is formed on a portion other than the element isolation insulating film 502, and a first conductive film 504 made of polycrystalline silicon is deposited (FIG. 5a).

The first conductive film 504 was processed and formed by one-time photolithography to form the first conductive film region 505 and the second conductive film region 506 at the same time. The first conductive film region 505 is a gate electrode of a MOS transistor, and the second conductive film region 506 covers a portion where a high-concentration impurity diffusion layer (source and drain of a MOS transistor) will be formed later. . Further, ion implantation is performed from above the first conductive film region 505 and the second conductive film region 506 to form a low-concentration impurity diffusion layer 507 in the single crystal silicon substrate 501 and to form the second insulating film 508. It was deposited (Fig. 5b).

Next, the first conductive film region 505 and the second conductive film region 50 are formed by using a chemical mechanical polishing (CMP) technique.
508 was removed until the top of 6 was exposed (Fig. 5c).

Next, the first wiring 50 is formed so as to cover the first conductive film region 505 and expose the second conductive film region 506.
9 was formed, and the second conductive film region 506 was removed using the first wiring 509 as a mask. Then, the second conductive film region 50
A high-concentration impurity diffusion layer 510 was formed by ion implantation in the portion of the single crystal silicon 501 located under 6 (FIG. 5).
d). Ion implantation conditions for forming the low-concentration and high-concentration impurity diffusion layers are in accordance with the first embodiment.

After that, the interlayer insulating film 511, the connection hole 512,
The metal wiring 513 is formed to complete the semiconductor device (see FIG. 5).
e).

The material and technique used for each portion in the second embodiment are basically the same as the corresponding portions in the first embodiment except for the single crystal silicon substrate 501, and the change in material and technique is also the first. According to the example of. First required only for the second embodiment
The wiring 509 was made of polycrystalline silicon. First wiring 50
Since 9 is polycrystalline silicon and the first conductive film 504 is also polycrystalline silicon, in this embodiment, the first wiring 509 is used.
It was possible to remove up to the second conductive film region 506 by etching for processing. However, another material may be used for the first wiring 509 as long as it is a material that can be electrically connected to the first conductive film region 505.

The semiconductor device manufactured by the method of the second embodiment has good uniformity of electrical characteristics for the same reason as in the case of the first embodiment, and the semiconductor device according to the distance between the gate electrode and the source / drain. We were able to obtain the required breakdown voltage.

Although the single crystal silicon substrate is used in the second embodiment, for example, in the case of manufacturing a polycrystalline silicon thin film transistor, even if the semiconductor layer is polycrystalline silicon formed on a glass or quartz glass substrate. In the case of manufacturing an amorphous silicon thin film transistor, the semiconductor layer may be amorphous silicon formed on a glass or quartz glass substrate.

Furthermore, the single crystal silicon of the semiconductor layer is made of SOI (Silicon on Insulator).
r) and SOS (Silicon on Saphir)
e) Even with the single-crystal silicon grown on it, there is no change in the effect that a semiconductor device with high uniformity and high breakdown voltage can be obtained by manufacturing by the method of this embodiment.

Moreover, unlike the first embodiment, the second embodiment uses the LOCOS method for element isolation when a semiconductor device is manufactured by the method of the present invention using a single crystal silicon substrate. Even when the insulating film is formed and a step is formed in the element isolation region, the first wiring 509 is formed, so that the wiring in the element isolation region can be secured.

In the two embodiments described above, the drawings are drawn symmetrically with the center of the gate electrode as a boundary. However, this is asymmetrical as required, and the offset on the source side and the drain side. It is also possible to easily use the source side and the drain side by changing the offset length of.

Another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described below as a third embodiment with reference to FIG. In the third embodiment, after a silicon oxide film for element isolation is formed on a single crystal silicon substrate by the LOCOS method,
It is an example to which the manufacturing method of the present invention is applied. This is because when the method of the first embodiment described above is applied to the manufacture of a semiconductor device using a single crystal silicon substrate in which a silicon oxide film for element isolation must be formed so as to rise from the substrate, Since the wiring portion in the same layer as the gate electrode and extending from the gate electrode is on the step of the silicon oxide film for element isolation, this wiring portion may become thin or disappear when using the planarization technique. Therefore, it is an example different from the second embodiment of the manufacturing method which solves this problem.

After a thin silicon oxide film is formed on the single crystal silicon substrate 601, the exposed silicon portion is thermally oxidized by using the silicon nitride film as a mask, and then the silicon nitride film is removed by a so-called LOCOS method, which is a so-called LOCOS method. , A gate insulating film 603 is formed on a portion other than the element isolation insulating film 602, and a first conductive film 604 made of polycrystalline silicon is deposited (FIG. 6a).

The first conductive film 604 was processed and formed by one-time photolithography to form the first conductive film region 605 and the second conductive film region 606 at the same time.

Here, in the case where a structure having a wiring portion on the silicon oxide film for element isolation is used, the first conductive film 604 is processed and formed by using photolithography, and the above-mentioned first conductive film is formed. Region 605 and second conductive film region 60
In addition to 6, the conductive film region may be formed over the element isolation insulating film 602. The first conductive film region 605 is a gate electrode of a MOS type transistor, and the second conductive film region 606 covers a portion where a high-concentration impurity diffusion layer (source and drain of a MOS transistor) will be formed later. . Further, ion implantation is performed from above the first conductive film region 605 and the second conductive film region 606 to form a low-concentration impurity diffusion layer 607 in the single crystal silicon substrate 601.
An insulating film 608 was deposited (FIG. 6b).

Next, a photoresist 609 is formed by photolithography, and using this as a mask, the second insulating film 608 on the second conductive film region 606 is exposed at the top of the second conductive film region 606. And the second insulating film 6
08 was partially removed from the top so that 08 remained (FIG. 6).
c). The lower portion of the second insulating film 608 to be left needs to have a thickness such that ions implanted by ion implantation for forming a later high concentration impurity do not reach the lower single crystal silicon substrate 601.

Further, the second conductive film region 606 is removed,
A high-concentration impurity diffusion layer 610 was formed by ion implantation in the portion of the single crystal silicon substrate 601 under the formed void (FIG. 6d). Ion implantation conditions for forming the low-concentration and high-concentration impurity diffusion layers are in accordance with the first embodiment.

After that, the interlayer insulating film 611, the connection hole 612,
The metal wiring 613 is formed to complete the semiconductor device (see FIG. 6).
e).

The material and technique used for each portion in the third embodiment are basically the same as the corresponding portions in the first embodiment except for the single crystal silicon substrate 601, and the change in material and technique is also the first. According to the example of.

Also in the semiconductor device manufactured by the method of the third embodiment, the electrical characteristics are good and the gate electrode and the source are The required breakdown voltage could be obtained according to the distance between the drains.

In the manufacturing method of the third embodiment, it is not necessary to form a new wiring (first wiring 509) as compared with the second embodiment, and the first conductive film region 605 can be used as it is as a wiring. There is an advantage.

Also, in the third embodiment, the drawing is drawn symmetrically with the center of the gate electrode as a boundary. However, like the other embodiments, the drawing is made asymmetrical to the left and right as necessary, and the offset on the source side is set. It is possible to easily change the length of the offset on the drain side and selectively use the source side and the drain side.

In the MOS type transistor manufactured by the method for manufacturing a semiconductor device of the present invention as described above, the offset length is not affected by the misalignment of the exposure apparatus as in the mask offset method, so that the electrical characteristics are uniform. It is possible to provide an offset having a good property and having a size larger than that of the sidewall method. In addition to such effects, in the MOS type transistor manufactured by using the semiconductor manufacturing method of the present invention, it is possible to reduce the nonuniformity of electrical characteristics due to the nonuniformity of the gate length.

The nonuniformity of the gate length can be cited as another factor of the nonuniformity of the electrical characteristics of the MOS transistor. The nonuniformity of the gate length is mainly due to the nonuniformity of the photolithography for forming the gate electrode, and partly due to the nonuniformity of the subsequent etching process. Gate length is MO
It is a large factor that determines the electrical characteristics of the S-type transistor, and even a slight change in the gate length directly appears as a change in the electrical characteristics. However, in the MOS transistor manufactured by the method for manufacturing a semiconductor device of the present invention, as will be described below as a fourth embodiment, a portion between the impurity diffusion layer of the source and drain and the channel (impurity of low concentration is We call it diffusion layer or offset)
Of the electric resistance per unit length in the channel length direction, when a prescribed voltage is applied to the gate and the drain, for example, a rated voltage, the electric resistance per unit length of the channel is approximately 2
In the MOS transistor which is reduced to one half, it is possible to reduce the non-uniformity of the electrical characteristics due to the non-uniformity of the gate length.

The fourth embodiment will be described below with reference to FIG.

FIG. 7 is a sectional view of the MOS type transistor of the second invention manufactured by the manufacturing method of the second embodiment. The left-right direction in the figure is the channel length direction of the MOS transistor, that is, the gate length direction.

The resistance per unit length of the low-concentration impurity diffusion layer 701 (offset) in the channel length direction is Ro. In addition, when the source terminal 702 is set to 0 V and a specified voltage is applied to the gate terminal 703 and the drain terminal 704, the average resistance value from the end to the end of the channel 705 in the conductive state (hereinafter referred to as the ON state) is expressed by the gate length. The resistance per unit length obtained by dividing is Rc. In the MOS type transistor of this embodiment, Ro is set to be approximately one half of Rc. R
A desired value of o was obtained by adjusting the amount of implanted ions in the ion implantation for forming the low-concentration impurity diffusion layer.

Let us now consider a case where the dimensions of the gate electrode 706 have changed. If the lateral width of the gate electrode 706 in FIG. 7, that is, the gate length changes by dL, the channel length also changes by dL. The variation of the offset length at this time is -2 dL for both the source side and the drain side. Since the MOS type transistor of FIG. 7 is manufactured by the method described in the second embodiment, the size of the first conductive film region 505 to be the gate electrode of the MOS type transistor and the second type as shown in FIG. If the dimensions of the conductive film region 506 are the same and the dimension of the first conductive film region 505 changes by dL, the dimension of the second conductive film region 506 formed at the same time also changes by dL, and the first conductive film This is because the distance between the region 505 and the second conductive film region 506, that is, the offset on one side, varies by -dL. When the channel length fluctuates in this way, dL is sufficiently smaller than the gate length.
If L is less than 10% of the gate length, the variation in the total resistance of the channel in the ON state is approximately equal to Rc multiplied by dL. On the other hand, since the variation in the offset dimension is −2 dL for both the source side and the drain side, the variation in the offset resistance is −2 dL multiplied by Ro. In the MOS transistor of this embodiment, Ro is approximately one half of Rc, so that the fluctuation of the channel resistance in the ON state is almost canceled by the fluctuation of the offset resistance. That is, in the MOS transistor of the fourth embodiment, the change in electrical characteristics due to the change in gate length can be reduced.

The MOS type transistor of the fourth embodiment is
Although it is manufactured by the manufacturing method of the second embodiment, the present invention is not limited to this, and the same effect can be obtained when manufactured by the manufacturing method of another embodiment of the present invention.

In the MOS type transistor of the fourth embodiment, the offset (low concentration impurity diffusion layer 701) does not necessarily have the first purpose of improving the breakdown voltage by relaxing the electric field at the drain end. This is because when the impurity concentration of the offset has to be determined in order to make Ro approximately 1/2 of Rc, the electric field relaxation effect of the offset may not be sufficiently obtained at the determined concentration. However, if the semiconductor device manufacturing method of the present invention is used, and the effect of reducing the nonuniformity of electrical characteristics due to the nonuniformity of the gate length while adding the electric field relaxation effect to the offset of the MOS type transistor, Note that this is one of the effects of the present invention.

[0064]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the size of the offset of the MOS type transistor can be made uniform and arbitrary. Therefore, when a semiconductor device having an offset is manufactured by the method for manufacturing a semiconductor device according to the present invention, it is possible to obtain a semiconductor device having uniform electric characteristics and a high degree of freedom in setting the breakdown voltage between the source and drain. There is.
This is an effect obtained in any of the embodiments of the method for manufacturing a semiconductor device of the present invention.

The electrical resistance per unit length in the channel length direction of the so-called offset portion between the high concentration impurity diffusion layers of the source and drain and the channel manufactured by the method for manufacturing a semiconductor device of the present invention is determined by the gate resistance. In the MOS transistor of the present invention, which is approximately one-half of the electric resistance per unit length of the channel when a specified voltage is applied to the electrode and the drain, the gate length variation due to the nonuniformity of photolithography causes It is possible to reduce the non-uniformity of the electrical characteristics that occurs.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a process of a so-called sidewall method in a conventional method of manufacturing a semiconductor device having an offset.

FIG. 2 is a process sectional view showing a process of a so-called mask offset method in the conventional method of manufacturing a semiconductor device having an offset.

FIG. 3 is a process cross-sectional view illustrating the first embodiment of the method of manufacturing a semiconductor device of the present invention. The steps from the beginning to the steps in the middle are shown, and the subsequent steps are shown in FIG.

FIG. 4 is a process sectional view explaining the first embodiment of the method for manufacturing a semiconductor device of the present invention. 4 shows the subsequent steps from FIG.

FIG. 5 is a process cross-sectional view illustrating a second embodiment of the method of manufacturing a semiconductor device of the present invention.

FIG. 6 is a process cross-sectional view illustrating a third embodiment of the method of manufacturing a semiconductor device of the present invention.

FIG. 7 is a sectional view illustrating a MOS transistor according to a fourth embodiment of the present invention.

[Explanation of symbols]

101, 201 ... Semiconductor substrate 102, 202, 503, 603 ... Gate insulating film 103, 203, 706 ... Gate electrode 104, 108, 206 ... Ion implantation 105, 204, 306, 507, 607 , 701 ...
-Low-concentration impurity diffusion layer 106 ... Insulating film 107 ... Sidewall spacers 109, 207, 310, 510, 610 ... High-concentration impurity diffusion layer 205, 309, 609 ... Photoresist 301 ... ..Semiconductor layer 302 ... First insulating film 303, 504, 604 ... First conductive film 304, 505, 605 ... First conductive film region 305, 506, 606 ... Second Conductive film regions 307, 508, 608 ... Second insulating film 308 ... Spacers 311, 511, 611 ... Interlayer insulating films 312, 513, 613 ... Metal wiring 501, 601 ... Single Crystal silicon substrate 502, 602 ... Element isolation insulating film 509 ... First wiring 512, 612 ... Connection hole 702 ... Source terminal 703 ... Gate terminal 7 4 ... drain terminal 705 ... channel

Claims (7)

[Claims] 1. A method of manufacturing a MOS semiconductor device, comprising:
At least a step of forming a gate insulating film on a semiconductor layer, a step of forming a cover layer and a gate electrode by one-time photolithography, a step of forming a spacer between the cover layer and the gate electrode, M including a step of removing the cover layer and a step of implanting impurity ions into the semiconductor layer below the removed cover layer.
A method for manufacturing an OS type semiconductor device. 2. A method for manufacturing a MOS type semiconductor device, comprising:
At least a step of forming a gate insulating film on the semiconductor layer, a step of forming the cover layer and the gate electrode by a single photolithography, a step of depositing a spacer insulating film, the top of the cover layer is exposed, And forming a spacer by removing the spacer insulating film from the upper portion so that the lower portion of the spacer insulating film remains, a step of removing the cover layer leaving the gate electrode and the spacer, and the removed cover A method of manufacturing a MOS type semiconductor device, comprising the step of implanting impurity ions into a semiconductor layer below the layer. 3. A method of manufacturing a MOS semiconductor device, comprising:
At least a step of forming an element isolation insulating film on a single crystal silicon substrate, a step of forming a gate insulating film, and a step of forming the cover layer and the gate electrode using the same material by a single photolithography process, A step of depositing a spacer insulating film, and a step of removing the spacer insulating film from the upper part so as to expose the top part of the cover layer and the top part of the gate electrode and leave the lower part of the spacer insulating film, thereby forming a spacer A step of forming a first wiring so as to cover at least the gate electrode and not the cover layer; a step of removing the cover layer; and a step of removing the cover layer in the single crystal silicon substrate below the removed cover layer. A method of manufacturing a MOS type semiconductor device, which comprises the step of implanting impurity ions. 4. The method of manufacturing a semiconductor device according to claim 2, wherein in the step of removing the spacer insulating film from the upper portion so that the lower portion of the spacer insulating film remains, the spacer insulating film is formed. Is removed by chemical mechanical polishing. 5. The method of manufacturing a semiconductor device according to claim 2, wherein in the step of removing the spacer insulating film from above so that the lower portion of the spacer insulating film remains,
A method of manufacturing a MOS type semiconductor device, characterized in that the spacer insulating film is removed by using an etch back method. 6. A method of manufacturing a MOS type semiconductor device, comprising:
At least a step of forming an element isolation insulating film on the single crystal silicon substrate, a step of forming a gate insulating film, a step of forming the cover layer and the gate electrode with the same material by one-time photolithography, A step of forming a spacer insulating film, a step of forming an etching mask by photolithography on the spacer insulating film other than the cover layer, and a step of forming the spacer insulating film in a portion without the etching mask. A step of removing the upper part by etching so that the cover layer is exposed and a lower part of the spacer insulating film remains, a step of removing the cover layer, and a single crystal silicon substrate under the removed cover layer. M comprising the step of implanting impurity ions
A method for manufacturing an OS type semiconductor device. 7. A MOS type semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1, wherein a unit between a source and drain impurity diffusion layers and a channel is a unit in a channel length direction. A MOS type semiconductor device characterized in that an electric resistance per length is approximately one half of an electric resistance per unit length of a channel when a prescribed voltage is applied to a gate electrode and a drain.