JPH09197439A - Active matrix type liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an opening rate by forming capacitors of gate lines and pixel electrodes via insulating layers having specific dielectric constant higher than the specific dielectric constant of second interlayer insulating films composed of anodically oxidized films and/or first interlayer insulating films. SOLUTION: Storage capacitors 104 are formed by utilizing the gate lines 101 and the pixel electrodes 103. When the gate line forming the storage capacitor of the certain pixel is the N-th piece from above, the pixel electrode forming this storage capacitor is impressed with voltage by the pixel TFT controlled by the (N+1)st gate line. The areas which constitute the storage capacitors 104 are selectively etched before the films of the pixel electrodes 103 are formed. The storage capacitors 104 are constructed by having the laminated films of the anodically oxidized films and the first interlayer insulating films or only the anodically oxidized films between the gate lines 101 and the pixel electrodes 103. A material having the highest possible specific dielectric constant is used for the first interlayer insulating films. As the specific dielectric constant is higher, the higher capacity of the storage capacitors 104 is obtd. As a result, the gate lines 101 are usable as a substitute with the capacitor lines.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a structure of an active matrix type liquid crystal display device controlled by a semiconductor device using crystalline silicon. In particular, it relates to the configuration of the pixel area.

[0002]

2. Description of the Related Art Recently, a technique for producing a thin film transistor (TFT) on an inexpensive glass substrate has been rapidly developed. The reason is that the demand for active matrix liquid crystal display devices has increased.

An active matrix type liquid crystal display device is
A TFT is arranged in each of the millions of pixels arranged in a matrix, and the electric charge that flows in and out of each pixel electrode is T
It is controlled by the switching function of the FT.

A liquid crystal is sandwiched between each pixel electrode and the counter electrode to form a kind of capacitor. Therefore, it is possible to display an image by changing the electro-optical characteristics of the liquid crystal by controlling the entrance and exit of charges to and from the capacitor by the TFT and controlling the light passing through the liquid crystal panel.

FIG. 5 shows a block diagram of a pixel area in a conventional active matrix type liquid crystal display device. As shown in FIG. 5A, the gate line 501 and the capacitor line 502 formed in parallel with the gate line 501 intersect with the data line 503 in a grid pattern. In the area surrounded by them, the pixel electrode 504
Is arranged. The capacitance line 502 and the pixel electrode 504 three-dimensionally overlap with each other through the first and second interlayer insulating films to form a storage capacitance.

Reference numeral 505 denotes a semiconductor film forming an active layer of the TFT, 506 a contact portion with a data line, and 507 a contact portion with a pixel electrode. The equivalent circuit at this time is as shown in FIG.

By the way, as shown in FIG. 5A, the area surrounded by the gate line 501 and the data line 503 and the pixel electrode 504 have not been three-dimensionally overlapped. This is because if the pixel electrode has a structure in which the pixel electrode and the data line and the gate line are three-dimensionally overlapped via the interlayer insulating film, a parasitic capacitance is generated between them and the operation speed of the liquid crystal display is reduced.

However, with the above structure, a gap portion 508 as shown in FIG. 5A is formed between the data line or gate line and the pixel electrode. Since the gap portion 508 hits the edge portion of the pixel electrode, the electric field is disturbed and the image display is blurred. In addition, the light leaked from the clearance portion 508 causes the clear image display to be blurred.

Further, when the semiconductor film 505 forming the active layer of the TFT is irradiated with light, there arises a problem that a photoexcitation phenomenon occurs and a leak current increases.

Therefore, as shown in FIG. 5B, the black matrix 509 is generally used to shield light from areas other than necessary areas for image display, such as gaps and locations where TFTs are installed, so as not to enter the field of view. Is. Black matrix 5
Chromium (Cr), titanium (Ti), etc. are often used as 09.

In this structure, since the black matrix 509 is provided, the image displayable area 10 is fitted inside. That is, the region surrounded by the gate line 501 and the data line 503 cannot be used effectively to the maximum extent. Further, since the capacitor line 502 is formed of the same material as the gate line 501, it has a light-shielding property in most cases.

Therefore, by providing the capacitance line 502 and the black matrix 509, an image displayable area 510 is provided.
Becomes narrower than necessary, which is a major obstacle to increasing the aperture ratio.

[0013]

The invention disclosed in the present specification provides a technique for solving the above-mentioned conventional problems. That is, it is an object of the present invention to provide a technique for realizing a high aperture ratio without using a capacitor line or a black matrix that is an obstacle to increasing the aperture ratio of a liquid crystal panel.

[0014]

Means for Solving the Problems First disclosed in the present specification
According to another aspect of the present invention, there is provided a first interlayer insulating film formed to cover a gate electrode and a gate line extending from the gate electrode, a wiring electrode formed on the first interlayer insulating film, and the wiring electrode. Line extending from the wiring layer, the wiring electrode and a second interlayer insulating film formed to cover the data line extending from the wiring electrode, and a transparent conductive film formed on the second interlayer insulating film. And a pixel electrode formed of, and at least a part of the gate line and the pixel electrode forms a capacitor that can function as a storage capacitor only through the first interlayer insulating film.

According to a second aspect of the invention, the first interlayer insulating film is formed to cover the gate electrode and the gate line extending from the gate electrode, and is formed on the first interlayer insulating film. A wiring electrode and a data line extending from the wiring electrode; a second interlayer insulating film formed to cover the wiring electrode and the data line extending from the wiring electrode;
A pixel electrode made of a transparent conductive film formed on the interlayer insulating film, and at least a part of the pixel electrode includes a gate line extending from the gate electrode and a data line extending from the wiring electrode. It is characterized by being shielded from light.

The outline of the present invention having the above structure will be described with reference to the schematic view of FIG. In FIG. 1, 101 is a gate line extending from the gate electrode, and 102 is a TFT.
Is a data line extending from a wiring electrode connected to the source region of. A thick line 103 indicates a pixel electrode made of a transparent conductive film such as ITO.

The gist of the first invention is to form the storage capacitor 104 by utilizing the gate line 101 and the pixel electrode 103. However, when attention is paid to a certain pixel, when the gate line forming the storage capacitor of the pixel is the Nth gate line from the top, the pixel electrode forming the storage capacitor is N
A voltage is applied by the pixel TFT controlled by the + 1st gate line.

With the above structure, when the data is written in the storage capacitor, the scanning of the gate line forming the storage capacitor is completed, so that the voltage level of the storage capacitor falls due to the change in the gate voltage. Can be prevented.

Originally, the gate line 101 and the pixel electrode 10
The first and second interlayer insulating films exist between the first and second interlayer insulating films. However, in the present invention, before forming the pixel electrode 103,
The region to be the storage capacitor 104 is selectively etched in advance. Therefore, the storage capacitor 104 has a structure in which a laminated film of an anodized film and a first interlayer insulating film or only an anodized film is provided between the gate line 101 and the pixel electrode 103.

Therefore, it is desirable to use a material having a high relative dielectric constant for the first interlayer insulating film. This is because the higher the relative dielectric constant, the larger the capacity of the storage capacitor. Further, the same effect can be obtained by making the thickness of the first interlayer insulating film as thin as possible.

Next, the gist of the second invention is that the edges of the pixel electrodes 103 overlap the gate lines 101 and the data lines 102 as shown in FIG. That is, the gate lines 101 and the data lines 102 are substituted for the black matrix.

In this case, the problem is the pixel electrode 103.
And the parasitic capacitance formed between the gate line 101 and the data line 102. However, in the present invention, since the organic resin material or the inorganic material having a low relative dielectric constant is used as the second interlayer insulating film, the parasitic capacitance can be minimized.

Furthermore, an organic resin material or an inorganic material is used.
Since the film thickness is increased to about 5 μm to form the film, the parasitic capacitance can be suppressed to a negligible level.

As described above, the necessary condition of the present invention is that the relative permittivity of the anodic oxide film and the first interlayer insulating film is higher than that of the second interlayer insulating film. Desirably, a material having a high relative permittivity is used for the first interlayer insulating film, and a material having a low relative permittivity is preferably used for the second interlayer insulating film.

The equivalent circuit of the pixel area having the structure shown in FIG. 1 has the structure shown in FIG. 6B.

Further, as shown in FIG. 1, at the same time when the wiring electrodes and the data lines extending from the wiring electrodes are formed, a light shielding film 105 for shielding at least a region for forming a channel is provided to prevent photoexcitation of the semiconductor layer. You can

The invention having the above structure will be described in detail with reference to the following embodiments.

【Example】

[Embodiment 1] In this embodiment, an example of forming a pixel region having the structure shown in FIG. 1 by utilizing the present invention will be described. Specifically, a detailed description will be given of a technique of substituting a black matrix with a gate line and a data line and a technique of substituting a capacitance line with a gate line.

FIG. 3 is a manufacturing process diagram of the pixel TFT which constitutes the pixel region shown in FIG. First, a glass substrate 301 having a 2000-mm insulating film as a base film on the surface.
An amorphous silicon film (not shown) having a thickness of 500Å is formed thereon. The insulating film is made of silicon oxide (SiO ₂ ), silicon oxynitride (S
iO _X N _Y ), silicon nitride film (SiN), etc.
The film may be formed by the D method or the low pressure thermal CVD method.

Next, this amorphous silicon film (not shown) is crystallized by heating, laser annealing, or a combination of both. Further, it is effective to add a metal element that promotes crystallization during crystallization.

After the crystallization is completed, the obtained crystalline silicon film (not shown) is patterned to form an island-shaped semiconductor layer 302. After forming the island-shaped semiconductor layer 302, a silicon oxide film 303 which later functions as a gate insulating film is formed to a thickness of 1500 Å. Of course, a silicon oxynitride film or a silicon nitride film may be used.

Next, a conductive film 304 having a light shielding property is formed.
Form a film with a thickness of 3000Å. In this embodiment, an aluminum film containing scandium of 0.2 wt% is used. Scandium has the effect of suppressing protrusions such as hillocks and whiskers generated on the aluminum surface during heat treatment and the like. This aluminum film 304 will later function as a gate electrode.

Thus, the state shown in FIG. 3A is obtained.
After the state of FIG. 3A is obtained, anodization is performed in the electrolytic solution using the aluminum film 304 as an anode. As the electrolytic solution, a 3% tartaric acid ethylene glycol solution neutralized with aqueous ammonia to adjust the pH to 6.92 is used. Further, platinum is used as a cathode, and the formation current is 5 mA, and the ultimate voltage is 10 V.

The thin and dense anodic oxide film (not shown) thus formed has the effect of enhancing the adhesion to the photoresist when patterning the aluminum film 304.
Further, the film thickness can be controlled by controlling the voltage application time.

Next, the aluminum film 304 is patterned to form a gate electrode (not shown). However, it is only a part of the inside that finally remains that substantially functions as the gate electrode.

Next, a second anodic oxidation is performed to form a porous anodic oxide film 305. The electrolytic solution was a 3% oxalic acid aqueous solution, and the formation current was 2 to 3 mA with platinum as the cathode.
It is processed as an ultimate voltage of 8V.

At this time, anodization proceeds in a direction parallel to the substrate. Further, the length of the porous anodic oxide film 305 can be controlled by controlling the voltage application time.

Further, after removing the photoresist (not shown) used for patterning the aluminum film with a dedicated stripping solution, anodic oxidation is performed for the third time to obtain the state of FIG. 3 (B).

For this anodic oxidation, an electrolytic solution prepared by neutralizing a 3% ethylene glycol solution of tartaric acid with aqueous ammonia to adjust the pH to 6.92 is used. Then, with platinum as the cathode, formation current 5-6 mA, ultimate voltage 1
Processed as 00V.

The anodic oxide film 306 formed at this time is extremely dense and strong. Therefore, the gate electrode 3 is protected from damage and heat generated in a post process such as a doping process.
Has the effect of protecting 07.

Further, since the strong anodic oxide film 306 is hard to be etched, there is a problem that the etching time becomes long when the contact hole is opened. Therefore, it is desirable that the thickness be 1000 mm or less.

Next, the silicon oxide film 303 is dry-etched using the porous anodic oxide film 305 and the gate electrode 307 as a mask to form a gate insulating film 308.

Next, impurities are implanted into the island-shaped semiconductor layer 302 by the ion doping method. For example, if an N-channel TFT is manufactured, P + ions may be implanted as impurities, and if a P-channel TFT is manufactured, B + ions may be implanted as impurities.

First, the first ion doping is performed in the state of FIG. In this example, the implantation of P + ions was performed at an acceleration voltage of 90 kV and a dose of 3 × 10 ¹³ atoms / cm 3.
Perform in ² .

As a result, the gate electrode 307 and the porous anodic oxide film 305 serve as masks, and regions 309 and 310 to be source / drain later are formed in a self-aligned manner.
(FIG. 3 (C))

Next, as shown in FIG. 3C, the porous anodic oxide film 305 is removed and a second doping is performed. Note that the second P + ion implantation was performed at an acceleration voltage of 10 k.
V and dose amount 5 × 10 ¹⁴ atoms / cm ² .

Then, the gate electrode 307 serves as a mask, and the low-concentration impurity regions 311 and 312 having a lower impurity concentration than the source region 309 and the drain region 310 are formed in a self-aligned manner.

At the same time, since no impurities are injected right under the gate electrode 307, a region 313 functioning as a channel of the TFT is formed in a self-aligned manner.

The low-concentration impurity region (or LDD region) 312 thus formed is the channel region 313.
It has the effect of suppressing the formation of a high electric field between the drain region 310 and the drain region 310.

Then, the KrF excimer laser is set to 200-
By irradiating with an energy density of 300 mJ / cm ² ,
Activation of the ion-implanted P + ions is performed. In addition,
Activation may be performed by thermal annealing at 300 to 450 ° C. for 2 hours, or laser annealing and thermal annealing may be used in combination.

Next, the first interlayer insulating film 314 is formed by the plasma CVD method. As the interlayer insulating film 314,
A silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like can be used. Since the first interlayer insulating film 314 serves as an insulating layer of the storage capacitor 104 in FIG. 1, it is desirable to use an insulating film having a relative dielectric constant as high as possible. for that reason,
In this embodiment, a silicon nitride film having a relative dielectric constant of about 7 is used. In addition, it is possible to increase the capacity by reducing the film thickness to about 1000Å.

After forming the first interlayer insulating film 314, a contact hole is formed in the source region 309, and an aluminum film (not shown) is formed to a thickness of 3000 Å. Next, the aluminum film (not shown) is patterned to form the source electrode 315 and the light shielding film 316. Shading film 31
Reference numeral 6 has a role of preventing light from being irradiated to the peripheral portion of the channel region 313 and exciting of carriers. (FIG. 3 (D))

Next, a second interlayer insulating film 317 is formed with a thickness of 1 to 5 μm so as to cover the source electrode 315 and the light shielding film 316. The second interlayer insulating film 317 may be made of an organic resin material or an inorganic material, but in this embodiment, polyimide is used as the organic resin material.

Then, the second interlayer insulating film 317 is patterned to form an opening for forming a storage capacitor on the gate line, and then a pixel electrode 318 made of a transparent conductive film is formed. (FIG. 3 (E))

In the present invention, the gate line 1 as shown in FIG.
When the wiring formed by 01 and the data line 102 is used as a black matrix, the parasitic capacitance between the pixel electrode and the wiring becomes a problem. However, the resin material has a relative permittivity of 2.8 to 3.4, which is lower than that of a silicified film such as a silicon nitride film, and the film thickness can be easily obtained, so that the parasitic capacitance can be set to a level at which there is no problem. It is possible.

Further, since the surface of the resin material 317 exhibits excellent flatness, the pixel electrode 318 formed thereon also exhibits excellent flatness, and rubbing failure at the time of cell assembly and an electric field applied to the liquid crystal. Disturbance can be eliminated.

In this way, a pixel TFT having a structure as shown in FIG. 3 (E) is manufactured. Although not described in this embodiment, when the drive circuit is incorporated on the same substrate, the driver TFT and the pixel TFT are manufactured at the same time.

The driver TFT is basically a pixel TFT.
It is made in the same process as. However, the pixel electrode is not necessary, and the source electrode 315 and the light-shielding film 31 in FIG.
This is completed by forming the drain electrode at the same time as forming 6.

Here, FIG. 4 shows a sectional view in which the storage capacitor 104 is divided by a line indicated by AB in FIG. FIG.
In (A), 401 is a gate insulating film, 402 is a gate line extending from a gate electrode, and 403 is an anodized film.

As shown in FIG. 4A, since the first interlayer insulating film 404 has a thin film thickness of about 1000 Å and has a high relative dielectric constant, it is held between the pixel electrode 405 and the gate line 402. Form a capacitor that can function as a capacitance. In addition,
Denoted by 406 is the pixel electrode end of another adjacent pixel.

Further, since the pixel electrodes 405 and 406 three-dimensionally overlap the gate line 402, it is possible to give the gate line 402 the same effect as that of the black matrix. In this case, since the second interlayer insulating film 407 made of a resin material has a large film thickness of 1 to 5 μm and has a low relative dielectric constant, the parasitic capacitance formed between the transparent electrode 405 and the gate line 402 can be reduced. The impact can be ignored.

Further, as shown in FIG. 4B, it is also possible to adopt a structure in which only an anodic oxide film is used as the insulating layer of the storage capacitor. At this time, the thickness of the holding capacity can be reduced to about 500 to 1000Å.

As described above, it is a necessary condition of the present invention to use a thin high dielectric constant material for the first interlayer insulating layer and a thick low dielectric constant material for the second interlayer insulating film. is there.

By satisfying this condition, the gate line can be substituted for the conventional capacitance line, and the gate line and the data line can be substituted for the conventional black matrix. That is, it is possible to realize a high aperture ratio in the active matrix type liquid crystal display device. [Embodiment 2] In this embodiment, an example in which the shape of the island-shaped semiconductor layer of Embodiment 1 is changed will be described. Since the manufacturing process of the pixel TFT and the driver TFT has already been described in detail in the first embodiment, it will be omitted here.

In FIG. 2, 201 is a gate line, 202 is a data line, and 203 is an island-shaped semiconductor layer forming an active layer. As shown in FIG. 2, the gate line 201 directly functions as a gate electrode.

The feature of this embodiment is that the island-shaped semiconductor layer 203 is completely shielded by the gate line 201 and the data line 202. Therefore, only the contact portion with the pixel electrode 204 is projected in the image display region. Therefore, it is not necessary to provide the light shielding film 316 made of the aluminum film, which is necessary in the first embodiment.

In the other structure, the gate line 2 is the same as in the first embodiment.
01 forms the storage capacitor 205 only through the laminated film of the pixel electrode 204, the anodic oxide film and the first interlayer insulating film or the anodic oxide film, and the gate line 201 and the data line 202.
Plays the role of a black matrix.

Therefore, according to this embodiment, it is possible to manufacture a liquid crystal display device having a high aperture ratio of 90% or more, which makes the best use of the image displayable region. [Example 3]

In this example, an example in which added value is added to the island-shaped semiconductor layer in Example 1 or Example 2 will be described.
Specifically, this is an example in which the channel length and the channel width of the channel region change depending on whether the TFT is in an on state or an off state.

This technique has already been reported by the present inventors, and its main purpose is to reduce the off current by substantially lengthening the channel length and narrowing the channel width when the TFT is in the off state. Is. The outline of the technology will be described below.

FIG. 7 shows an island-shaped semiconductor layer 701 formed according to the process procedure of the first embodiment. Ions are selectively implanted into a region 702 which later functions as a channel. For example, when manufacturing an N-channel TFT, P + ions are added at 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm 3.
² , preferably with a dose of 3 × 10 ^{12 to} 3 × 10 ¹³ atoms / cm ² .

Then, ion-implanted regions 703 to 705 are formed so as to block the channel region. The regions 703 to 705 do not have to be in contact with the outer edge of the island-shaped semiconductor layer as shown in FIG. That is, it may be in a state of being scattered like islands in the region 702 to be a channel later.

An outline of the electrical characteristics of the TFT manufactured using the island-shaped semiconductor layer thus ion-implanted will be described with reference to FIG.

In FIG. 8A, 801 is a source region,
Reference numeral 802 denotes a drain region, and reference numerals 803 to 805 denote regions into which ions have been previously implanted as described above, which will be referred to as floating island regions. At this time, an undoped substantially intrinsic semiconductor region (hereinafter referred to as a base region) 80
6 and the floating island regions 803 to 805 have high potential barriers. Therefore, when the N-channel TFT is in the off state, electrons slightly move along the arrow of the base region 806. This movement of electrons is observed as off current (or leak current).

However, when the N-channel type TFT is in the ON state, the base region 806 is inverted and the floating island regions 803-8.
Since the potential barrier with respect to 05 becomes negligible, a large amount of electrons move along the path shown by the arrow in FIG. This electron movement is observed as an on-current.

The manner in which the potential barrier changes between the off state and the on state of the TFT in this manner will be schematically described with reference to FIG. In FIG. 9, Vg is the gate voltage (V
g> 0), Ec is the conduction band, Ev is the valence band, and Ef is the Fermi level.

First, when the N-channel TFT is in an off state (a state in which a negative voltage is applied to the gate), the base region 80
6 has a band state as shown in FIG. That is, since holes, which are minority carriers, are gathered on the semiconductor surface and electrons are dissipated, the movement of electrons between the source / drain is extremely small.

On the other hand, since the floating island regions 803 to 805 are implanted with P + ions, the Fermi level Ef is equal to the conduction band E.
It is pushed up near c. At this time, floating island area 8
In Nos. 03 to 805, the band state is as shown in FIG.

As shown in FIG. 9B, in the floating island regions 803 to 805 which are N-type semiconductor layers, even if a negative voltage is applied to the gate, the energy band bends only slightly.

Therefore, the energy difference between the energy of the valence band on the semiconductor surface in FIG. 9A and the energy of the valence band on the semiconductor surface in FIG. 9B corresponds to the potential barrier. Therefore, the electrons are
6 and the floating island regions 803 to 805 are not reciprocated.

Next, when the N-channel TFT is in the ON state (a state where a positive voltage is applied to the gate), the base region 80
6 has a band state as shown in FIG. 9 (C). That is, since electrons, which are majority carriers, are accumulated on the semiconductor surface, electrons move between the source / drain.

At this time, the floating island regions 803 to 805 are in a band state as shown in FIG. 9 (D). FIG.
As shown in (D), floating island regions 803 to 80, which are N-type semiconductor layers, are formed similarly to when a negative voltage is applied to the gate.
In No. 5, the energy band is hardly bent even if a positive voltage is applied to the gate.

However, since the Fermi level Ef is originally pushed up near the conduction band Ec in FIG. 9D, a large number of electrons are always present in the conductor.

Therefore, when a positive voltage is applied to the gate,
Since both the base region 806 and the floating island regions 803 to 805 are in a band state in which electrons easily move, the potential barrier at the boundary between the base region 806 and the floating island regions 803 to 805 can be ignored.

As described above, the base region 80 is in the off state.
Only 6 is a movement path of electrons, and in the ON state, the base region 806 and the floating island regions 803 to 805 are movement paths of electrons.

That is, the W / L ratio when the TFT is in the OFF state is much larger than the W / L ratio when the TFT is in the OFF state, and it is possible to reduce the OFF current without impairing the ON current. . As a result, the on / off current ratio can be increased.

With such a structure, the island-shaped semiconductor layer of the pixel TFT can be made as small as possible and the on / off current ratio can be increased. Therefore, for example, even when the circuit configuration as shown in FIG. 1 is adopted, it is possible to arrange the high-performance pixel TFT without lowering the aperture ratio.

[Embodiment 4] In this embodiment, an example in which the shape of the storage capacitor is changed in Embodiments 1 to 3 will be shown. Since the manufacturing process of the TFT and the storage capacitor is the same as that of the first embodiment, the description thereof is omitted here.

FIG. 10 shows a sectional structure view of the storage capacitor in this example. In FIG. 10A, 11 is a gate insulating film, 12 is a gate line extending from the gate electrode, and 13 is an anodized film.

As shown in FIG. 10A, since the first interlayer insulating film 14 has a thin film thickness of about 1000 Å and has a high relative dielectric constant, it is held between the pixel electrode 15 and the gate line 12. Form a capacitor that can function as a capacitance. 16
Indicated by is the pixel electrode end of another adjacent pixel.

The difference from FIG. 4A described in the first embodiment is that in FIG. 4A, the capacitor is formed only on the upper surface of the gate line, whereas in FIG. 10A, the gate line is formed. The point is that a capacitor is formed on the upper surface and the side surface.

The pixel electrodes 15 and 16 are the gate lines 12
3D, the gate line 12 can be provided with the same effect as the black matrix. in this case,
The second interlayer insulating film 17 made of a resin material has a film thickness of 1 to 5 μm.
Since it has a large thickness of m and a low relative dielectric constant, the influence of the parasitic capacitance formed between the pixel electrode 15 and the gate line 12 can be ignored.

Further, as shown in FIG. 10B, it is also possible to adopt a structure using only an anodic oxide film as the insulating layer of the storage capacitor. At this time, set the thickness of the holding capacity to 500 to 1000Å
It can be made as thin as possible.

With the structure as described above, a larger storage capacity can be secured. That is, it becomes possible to realize a high aperture ratio and a high-definition image display in the active matrix type liquid crystal display device.

[Embodiment 5] In this embodiment, as a second interlayer insulating film, LPD (Liquid Phase Depo) is used.
An example of using an insulating film applied by the method) will be described. Of course, as shown in Example 1, it is important that the film has a low relative permittivity and can easily obtain a film thickness. The manufacturing process of the pixel TFT and the driver TFT has already been described in detail in the first embodiment, and therefore the description thereof is omitted here.

The outline of the film formation by the LPD method (also called the spin method) is as follows. Although the explanation is given for the case of a silicon oxide film (SiO _x ) which is an inorganic material, SiOF film (relative permittivity 3.2 to 3.3) as another inorganic material or polyimide (relative permittivity) as an organic resin material. 2.8-3.4) etc. can also be used.

First, a H ₂ SiF ₆ solution is prepared, SiO ₂ : xH ₂ O is added thereto, and stirring is carried out for 3 hours. The processing temperature at this time is kept at 30 ° C. Next, the solution after stirring is filtered so that the solution has a desired concentration. After the adjustment is completed, stir while warming in a water bath or the like until reaching 50 ° C.

This completes the preparation of the coating solution.
Also, for example, if H ₃ BO ₃ is added to this solution, B
It is possible to form a silicon oxide-based coating containing + ions (so-called BSG coating).

The film formation is completed by immersing the substrate to be treated in the solution prepared according to the above procedure, rinsing it with pure water and then drying it. If the organic resin material is applied, a desired coating solution may be prepared and the coating may be formed by the LPD method.

Polyimide or the like can be used as the organic resin material, and its relative dielectric constant is as low as 2.8 to 3.4. In this case, the coating solution is applied on the substrate to be treated held on the spinner, and the spinner is rotated at 2000 rpm to form the coating. After forming the film, bake at 300 ℃ for 30 min to improve the film quality.

As described above, the desired film can be formed relatively easily by the LPD method. That is, it is possible to significantly improve the throughput. Further, since the film thickness can be freely adjusted by the time of immersion in the solution (rotation speed when using a spinner) and the solution concentration, it is easy to form a thick and flat film.

[0101]

According to the first invention disclosed in the present specification, it becomes possible to substitute the gate line for the capacitance line. According to the second invention disclosed in this specification,
The gate lines and the data lines can be substituted for the black matrix.

As an effect of the above invention, since the pixel region can be formed without providing the capacitance line and the black matrix, the region surrounded by the gate line and the data line can be effectively used to the maximum extent, and the pixel region can be increased by 90% or more. It is possible to achieve an aperture ratio.

[0103]

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a pixel region in a liquid crystal display device.

FIG. 2 is a diagram showing a configuration of a pixel region in a liquid crystal display device.

FIG. 3 is a diagram schematically showing a manufacturing process of a pixel TFT.

FIG. 4 is a diagram showing a cross-sectional structure of a storage capacitor.

FIG. 5 is a diagram showing a configuration of a pixel region in a conventional liquid crystal display device.

FIG. 6 is a diagram showing an equivalent circuit of a pixel region in a liquid crystal display device.

FIG. 7 is a diagram showing an outline of a structure of a semiconductor layer.

FIG. 8 is a diagram showing an outline of electric characteristics of a semiconductor layer.

FIG. 9 is a diagram showing an outline of a band state of a semiconductor layer.

FIG. 10 is a diagram showing a cross-sectional structure of a storage capacitor.

[Explanation of symbols]

 101 gate line 102 data line 103 pixel electrode 104 storage capacitor 105 light shielding film 301 glass substrate 302 island-shaped semiconductor layer 303 silicon oxide film 304 conductive film 305 porous anodic oxide film 306 dense anodic oxide film 307 gate electrode 308 gate insulation Film 309 Source region 310 Drain region 311, 312 Low concentration impurity region 313 Channel formation region 314 First interlayer insulating film 315 Wiring electrode 316 Light shielding film 317 Second interlayer insulating film 318 Pixel electrode 508 Clearance part 509 Black matrix 701 Island shape Semiconductor layer 702 Channel region 703 to 705 Ion implantation region 801 Source region 802 Drain region 803 to 805 Floating island region 806 Base region

Claims (18)

[Claims] 1. An anodized film obtained by anodizing a gate electrode and a gate line extending from the gate electrode; a first interlayer insulating film formed to cover the anodized film; A wiring electrode formed on the interlayer insulating film, a data line extending from the wiring electrode, and a second interlayer insulating film formed to cover the wiring electrode and the data line extending from the wiring electrode, A pixel electrode made of a transparent conductive film formed on the second interlayer insulating film; and a second interlayer insulating film formed of the anodized film and / or the first interlayer insulating film. An active matrix type liquid crystal display device having a capacitor formed via an insulating layer having a high relative dielectric constant. 2. An anodized film obtained by anodizing a gate electrode and a gate line extending from the gate electrode; a first interlayer insulating film formed to cover the anodized film; A wiring electrode formed on the interlayer insulating film, a data line extending from the wiring electrode, and a second interlayer insulating film formed to cover the wiring electrode and the data line extending from the wiring electrode, A pixel electrode made of a transparent conductive film formed on the second interlayer insulating film, wherein at least a part of the gate line and the pixel electrode is the anodic oxide film and the first interlayer insulating film. An active matrix type liquid crystal display device, wherein a capacitor capable of functioning as a storage capacitor is formed through the laminated film of. 3. The active matrix type liquid crystal display device according to claim 2, wherein the relative dielectric constants of the first interlayer insulating film and the anodic oxide film are higher than the relative dielectric constant of the second interlayer insulating film. 4. The first interlayer insulating film according to claim 1, wherein the first interlayer insulating film is one or more insulating materials selected from a silicon oxide film, a silicon oxynitride film, and a silicon nitride film having a thickness of 250 to 2000 liters. An active matrix liquid crystal display device characterized by comprising a film. 5. An anodized film obtained by anodizing a gate electrode and a gate line extending from the gate electrode; a first interlayer insulating film formed to cover the anodized film; A wiring electrode formed on the interlayer insulating film, a data line extending from the wiring electrode, and a second interlayer insulating film formed to cover the wiring electrode and the data line extending from the wiring electrode, A pixel electrode made of a transparent conductive film formed on the second interlayer insulating film, and at least a part of the gate line and the pixel electrode functions as a storage capacitor via only the anodic oxide film. An active matrix type liquid crystal display device characterized by forming a capacitor. 6. The active matrix type liquid crystal display device according to claim 5, wherein the anodic oxide film has a relative dielectric constant higher than that of the second interlayer insulating film. 7. The pixel electrode forming the storage capacitor according to claim 1, 2, or 5, when the gate line forming any one storage capacitor is the Nth gate line from the top. An active matrix type liquid crystal display device characterized in that a voltage is applied by a pixel TFT controlled by an (N + 1) th gate line. 8. The semiconductor layer forming a pixel TFT for controlling a voltage applied to a pixel electrode is formed separately in a base region and a floating island region according to claim 2, claim 5, or claim 7. Active matrix liquid crystal display device. 9. A first interlayer insulating film formed to cover a gate electrode and a gate line extending from the gate electrode, a wiring electrode formed on the first interlayer insulating film, and the wiring electrode. An extending data line, a second interlayer insulating film formed to cover the wiring electrode and the data line extending from the wiring electrode, and a transparent conductive film formed on the second interlayer insulating film. An active matrix type liquid crystal display device, wherein the gate line and the data line double as a wiring and a black matrix. 10. The active matrix type liquid crystal display device according to claim 9, wherein the relative dielectric constant of the second interlayer insulating film is lower than the relative dielectric constant of the first interlayer insulating film. 11. The active matrix type liquid crystal display device according to claim 9, wherein the second interlayer insulating film is made of an organic resin material or an inorganic material having a thickness of 1 to 5 μm. 12. An active matrix type liquid crystal display device according to claim 9, wherein a semiconductor layer forming a pixel TFT for controlling a voltage applied to the pixel electrode is formed separately in a base region and a floating island region. 13. An anodized film obtained by anodizing a gate electrode and a gate line extending from the gate electrode; a first interlayer insulating film formed to cover the anodized film; A wiring electrode formed on the interlayer insulating film, a data line extending from the wiring electrode, and a second interlayer insulating film formed to cover the wiring electrode and the data line extending from the wiring electrode, A pixel electrode formed of a transparent conductive film formed on the second interlayer insulating film so as to three-dimensionally overlap the gate line and the data line, and a region in which the gate line and the pixel electrode overlap each other. Is an active matrix type liquid crystal display device, which includes a region which functions as a black matrix and which functions as a storage capacitor in the region. 14. The active matrix type liquid crystal display device according to claim 13, wherein the second interlayer insulating film is removed by etching from a region functioning as a storage capacitor. 15. The active matrix type liquid crystal display device according to claim 13, wherein the relative permittivity of the first interlayer insulating film and the anodic oxide film is higher than the relative permittivity of the second interlayer insulating film. 16. The method according to claim 13 or 14,
The active matrix type liquid crystal display device, wherein the second interlayer insulating film is made of an organic resin material or an inorganic material having a thickness of 1 to 5 μm. 17. The active matrix type liquid crystal display device according to claim 13, wherein the semiconductor layer forming the pixel TFT for controlling the voltage applied to the pixel electrode is formed separately in the base region and the floating island region. 18. The active matrix type device according to claim 13, further comprising a light-shielding film which shields at least a region for forming a channel, which is formed simultaneously with the formation of the wiring electrode and the data line extending from the wiring electrode. Liquid crystal display device.