JP3431741B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention disclosed in this specification relates to a structure of a liquid crystal electro-optical device or an EL type flat panel display, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Liquid crystal electro-optical devices are known as flat panel displays. Further, as a liquid crystal electro-optical device capable of displaying high image quality, an active matrix liquid crystal electro-optical device is known.

An active matrix type liquid crystal electro-optical device has a structure in which one or more thin film transistors are individually arranged in each pixel arranged in a matrix, and charges flowing in and out of each pixel electrode are switched by the thin film transistor. is doing.

In such a structure, a light-shielding film called a black matrix for securing display contrast and for shielding the thin film transistors arranged in each pixel from light is required.

A metal such as chromium is usually used as the black matrix. A metal material is used for the black matrix because it is easy to manufacture and there is no problem of impurities.

FIG. 9 shows a manufacturing process of a thin film transistor arranged in a pixel portion of a conventionally known active matrix type liquid crystal display device. First, a silicon oxide film 302 is formed as a base film on the glass substrate 301.

Further thereon, a silicon film which later constitutes an active layer is formed. As the silicon film, a crystalline silicon film obtained by crystallizing an amorphous silicon film formed by a CVD method by heating or laser light irradiation is used.

By patterning this crystalline silicon film, an active layer 303 of a thin film transistor is obtained. Then, a silicon oxide film 304 forming a gate insulating film is formed,
Further, the gate electrode 305 is made of a metal material or a silicide material. Thus, the state shown in FIG. 3A is obtained.

Next, the source region and the drain region are formed by implanting impurity ions. This step is performed by accelerating and implanting impurity ions by using the plasma doping method or the like with the gate electrode 305 as a mask as shown in FIG.

After the implantation of the impurity ions, annealing is performed by irradiation with laser light or irradiation with intense light to promote the resistance reduction of the source / drain regions. Thus the source region 3
06 and the drain region 308 are formed in a self-aligned manner.
Further, a region where the impurity ions are not implanted is formed as a channel forming region 307 in a self-aligned manner by using the gate electrode 305 as a mask.

Next, as shown in (C), the first interlayer insulating film 309 is formed of a silicon oxide film. Further, a contact hole is formed and a contact wiring (source wiring) 310 to the source region 306 is formed. And the second
The inter-layer insulating film 311 is formed of a silicon oxide film.

A black matrix 312 made of a metal film is formed on the silicon oxide film 311. Further, the third interlayer insulating film 313 is formed of a silicon oxide film. (Fig. 9
(D))

After forming the contact hole, the ITO electrode 314 forming the pixel electrode is formed.

In such a structure, a pinhole present in the third interlayer insulating film 313 becomes a problem. IT
The O film particularly has a good wraparound during film formation and is formed with good coverage in the pinhole. In other words, the minute pinholes are easily filled.

Reference numeral 316 in FIG. 9D is a pinhole. And IT is shown by 315.
This is a pinhole portion filled with O material.

In such a state, the ITO electrode 31
4 and the black matrix 312 are short-circuited. In order to solve this problem, a method of forming the interlayer insulating film 313 thicker than necessary can be considered. Further, a method may be considered in which a special multilayer film is used as the interlayer insulating film 313 so that the existence of pinholes can be ignored. Further, a method utilizing a film forming method such as a photo-CVD method that can obtain a film quality with few pinholes can be considered. However, such a method cannot be said to be a preferable means from the economical viewpoint.

When a multilayer wiring as shown in FIG. 9 is formed, a specific wiring portion has a potential during film formation using plasma or etching, which may cause local destruction. There are many. Such a phenomenon becomes a factor that reduces the production yield of the device.

[0018]

SUMMARY OF THE INVENTION The invention disclosed in the present specification suppresses the occurrence of a short circuit between upper and lower wirings and a defect in the process of utilizing plasma in a structure having a multilayer wiring as shown in FIG. The challenge is to provide a configuration.

Further, due to the pinholes existing in the interlayer insulating film formed on the upper surface of the black matrix made of a metal material, the pixel electrode formed on the interlayer insulating film and the black matrix are short-circuited. The challenge is to provide a preventive configuration. Another object is to realize the above problems without complicating the manufacturing process.

[0020]

[Means for Solving the Problems]

1. One of the inventions disclosed in this specification uses a thin film transistor formed on a substrate having an insulating surface, a multilayer wiring connected to the thin film transistor, and a material forming the multilayer wiring. And a light-shielding film that shields the thin film transistor formed in this way.

In particular, in the above structure, the material forming the light-shielding film is made of an anodizable metal material or a material containing the metal material as a main component, and an anodized film is formed on the surface thereof. Is characterized by.

Further, in the above structure, the material forming the light-shielding film is made of aluminum or a material containing aluminum as a main component, and an anodized film is formed on the surface thereof.

Further, in the above structure, the wiring of the lowermost layer of the multilayer wiring is characterized in that it is divided after the upper wiring on the wiring is formed.

Another structure of the present invention is a method of manufacturing a semiconductor device having multi-layered wiring, which comprises a step of forming a first wiring with a metal material capable of anodic oxidation, and an anode on the surface of the first wiring. A step of forming an oxide film, a step of forming an insulating film covering the first wiring, and a step of forming a second wiring above the first wiring with an anodizable metal material. A step of forming an anodic oxide film on the surface of the second wiring, a step of forming an opening reaching the first wiring, and a step of dividing the first wiring using the opening. It is characterized by having.

In particular, in the above structure, the material forming the light-shielding film is made of a metal material capable of anodizing or a material containing the metal material as a main component, and an anodizing film is formed on the surface thereof. Is characterized by.

In the above structure, the material forming the light-shielding film is made of aluminum or a material containing aluminum as a main component, and an anodic oxide film is formed on the surface thereof.

[0027]

EXAMPLES FIGS. 1 to 8 show steps of manufacturing the thin film transistor shown in this example. In this embodiment, the structure of one portion of a pixel of an active matrix type liquid crystal display device is shown. Further, a thin film transistor of a peripheral driving circuit portion and a part of a wiring portion which are integrated on the same substrate at the same time are also shown in the same drawing.

First, as shown in FIG. 1A, a silicon oxide film 102 is formed as a base film on a glass substrate (or a quartz substrate) 101 to a thickness of 3000 Å. As a film forming method, a plasma CVD method or a sputtering method may be used. This base film functions to relieve stress acting between the glass substrate and a semiconductor layer to be formed later and to prevent diffusion of impurities from the glass substrate.

Next, an amorphous silicon film (amorphous silicon film) is formed by the plasma CVD method or the low pressure thermal CVD method. Then, the amorphous silicon film is crystallized by heat treatment, irradiation with laser light, or a method using both of them. Thus, the crystalline silicon film 100 is obtained.

Next, the crystalline silicon film 100 obtained as shown in FIG. 1B is patterned to form the active layers 103 and 104 of the thin film transistor. Reference numeral 103 denotes an active layer of a thin film transistor arranged in the peripheral drive circuit,
Reference numeral 4 is an active layer of the thin film transistor arranged in the pixel portion.

Reference numeral 105 denotes a semiconductor layer which extends from the peripheral drive circuit and a gate electrode of a thin film transistor arranged in a pixel and remains in a wiring portion for electrically connecting the thin film transistors. Reference numeral 106 denotes a semiconductor layer remaining in a portion where a take-out electrode from a gate line (not shown) extending from the gate electrode is provided.

The remaining semiconductor layers 105 and 106
May be particularly left unremoved. In this case, the gate wiring is formed on the base film 102 in this region.

Next, as shown in FIG. 1C, a silicon oxide film 107 forming a gate insulating film is formed by plasma CVD to a thickness of 1000 Å.

Next, as shown in FIG. 1D, an aluminum film 108 for forming a gate electrode and wiring extending from the gate electrode later is formed to a thickness of 4000 Å. As a film forming method, a sputtering method or an electron beam evaporation method may be used.

Scandium is contained in the aluminum film 108 in an amount of about 0.1 to 1% by weight in order to suppress the generation of hillocks and whiskers in the subsequent step.

Hillocks and whiskers are needle-like or prickle-like protrusions formed as a result of abnormal growth of aluminum caused by heating or laser light irradiation. Hillocks and whiskers cause a short circuit between adjacent wirings and a short circuit between wirings that are vertically separated from each other, and therefore their occurrence must be suppressed.

Further, anodization using this aluminum film 108 as an anode is performed in an electrolytic solution to form a dense anodic oxide film 109 on the surface of the aluminum film 108.
Form a film with a thickness of Å. (Fig. 1 (D))

For anodic oxidation for forming this dense anodic oxide film, an ethylene glycol solution containing 3% tartaric acid neutralized with aqueous ammonia is used as an electrolytic solution. In this anodic oxidation, a dense and hard aluminum oxide film can be obtained. Further, the control of the film thickness can be controlled by the applied voltage.

This anodic oxide film is an aluminum film 108.
It is very effective in suppressing the formation of hillocks and whiskers on the surface of the. Further, after that, it becomes very useful for enhancing the adhesiveness of the resist mask arranged on the aluminum film 108.

Then, a resist mask (not shown) is arranged, and the aluminum film 108 is formed as shown in FIG.
Pattern. Thus the gate electrodes 110 and 11
1. Further, the wirings 112 and 113 extending therefrom are formed. These electrodes and wirings are referred to as first-layer wirings for convenience.

Although not shown, in the state shown in FIG. 2A, the resist film used for patterning is arranged on the gate electrodes 110 and 111 and the wirings 112 and 113 extending therefrom. .

In the state shown in FIG. 2A, the gate electrodes 110 and 111 are connected by the wiring 112. This is because the same current is applied to both gate electrodes during the subsequent anodic oxidation, and both electrodes are set to the same potential so that plasma damage is not concentrated on a specific region in the etching process or film forming process using plasma. This is because

When the state shown in FIG. 2A is obtained, the gate electrodes 110 and 111, and the wiring 112 extending therefrom.
And 113 are used as anodes to perform anodic oxidation to form a porous anodic oxide film on the side surface thereof.

Reference numerals 114 to 116 in FIG. 2B are porous anodic oxide films. This anodic oxide film is 3
% Oxalic acid aqueous solution as an electrolytic solution.

This anodic oxidation process is performed only on the exposed side surfaces of the gate electrodes 110 and 111 and the wirings 112 and 113 extending therefrom.

The porous anodic oxide film formed in this step can be grown to a thickness of several μm. The growth distance can be controlled by the anodic oxidation time.

After obtaining the state shown in FIG. 2B, the anodic oxide film 109 having a dense film quality is removed. Since this dense anodic oxide film 109 is extremely thin, it can be easily removed using buffer hydrofluoric acid.

Next, a dense anodic oxide film is formed again.
That is, an ethylene glycol solution containing 3% tartaric acid neutralized with aqueous ammonia is used as an electrolytic solution, and anodization is performed using the gate electrodes 110 and 111 and the wirings 112 and 113 as anodes. In this step, the electrolytic solution penetrates into the porous anodic oxide film, so that FIG.
A dense anodic oxide film 117 is formed as shown in FIG.

This anodic oxide film 117 has a gate electrode and a wiring or electrode on which a gate wiring is formed, and further B.
It works to prevent short circuit with M. The thickness of this anodic oxide film is 500 Å.

In the above steps, the gate electrode 1
10 and 111, and wirings 112 and 113 extending from them are all connected. In other words, the gate electrodes 110 and 111 are connected by the wiring 112.

This is because it is necessary to pass a current for anodic oxidation to all gate electrodes during anodic oxidation, and all electrodes are made to have the same potential in a film forming process using dry etching or plasma, This is to prevent plasma damage from being concentrated on the part.

Next, the silicon oxide film 10 exposed by using the remaining gate electrode and wiring (that is, the wiring of the first layer) as a mask
Remove 7. As a removing method, a dry etching method may be used. Thus, the state shown in FIG. 2D is obtained. Here, 118 and 119 function as gate insulating films and remain silicon oxide films.

In this etching step, since all the wirings in the first layer are electrically at the same potential, plasma for dry etching does not concentrate on a part of the wiring and uniform etching is performed. It can be carried out.

As a result of this step, a part of the active layers 103 and 104 is exposed as shown in FIG.

Next, as shown in FIG. 3A, impurity ions are implanted to form the source and drain regions. In this step, B ions are implanted if a P-channel type thin film transistor is formed, and P ions are implanted if an N-channel type thin film transistor is formed. If the P-channel type and the N-channel type are separately formed, both impurity ions are selectively implanted into a predetermined region using a resist mask.

By implanting the impurity ions, as shown in FIG. 3A, the regions 120, 123, 124, 127 into which the impurity ions are implanted at a high concentration and the impurity ions at a low concentration are implanted. Regions 121 and 125 and regions 122 and 126 into which impurity ions are not implanted are simultaneously formed in a self-aligned manner.

This is because the remaining silicon oxide films 118 and 11
This is because 9 and 9 function as a semi-transparent mask.

As a result of the implantation of the impurity ions, the regions 120, 123 and 12 in which the impurity ions are highly implanted.
4, 127 are the source and drain regions. Further, the regions 121 and 125 in which the impurity ions are implanted at a low concentration become the low concentration impurity regions. The drain region side of the low concentration impurity region becomes a region called an LDD (lightly doped drain) region.

After the implantation of the impurity ions is completed, laser light irradiation is performed to activate the previously implanted impurity ions and anneal damage to the active layer caused by the implantation of the ions.

Although the example of irradiating the laser beam is shown here, a method of irradiating intense light such as infrared light or heating may be adopted. However, in the case of heat treatment, it is necessary to pay attention to the heat resistance of the substrate.

Next, as shown in FIG. 3B, a first interlayer insulating film 128 is formed to a thickness of 4000Å. The interlayer insulating film 128 is composed of a silicon oxide film. Further, the film forming method is performed by using the plasma CVD method.

Next, as shown in FIG. 3B, an aluminum film 129 for forming the second layer wiring and BM (black matrix) is formed. This aluminum film has
In addition to the additive for preventing hillocks, an additive is added in the subsequent anodic oxidation process so that the precipitate (anodic oxide) becomes black. Such a technique is used when forming a colored anodic oxide film on the surface of an industrial product such as an aluminum sash.

After obtaining the state shown in FIG. 3B, the aluminum film 129 is patterned to leave a region 130 functioning as a BM and a region 131 functioning as a second layer wiring. The wiring 131 of the second layer is used for drawing out the connection between the wirings of the first layer and for connecting and routing the wiring of the third layer and the wiring of the first layer which are formed later. Thus, the state shown in FIG. 3C is obtained.

The second layer wiring 131 is patterned so as to be connected to all the regions. This is because a current is commonly applied in the subsequent anodic oxidation process, and in the film formation and etching process using plasma,
This is to prevent a specific region from having a potential, plasma damage being concentrated there, and unevenness in film formation and etching from occurring.

Next, as shown in FIG. 4, dense anodic oxide films 132 and 133 are formed on the exposed surfaces of the remaining aluminum films 130 and 131. The method of forming the dense anodic oxide film is performed according to the method described above. The film thickness is 500Å.

The anodic oxide film indicated by 132 has the surface of the BM region indicated by 130 colored as a light-shielding film with an appropriate color (preferably black), and further, the BM region and wirings and electrodes formed above are formed. Function to improve the insulation of the.

The anodic oxide film indicated by 133 functions to improve the insulation between the second layer wiring 131 and the wiring formed later.

The BM 130 and the wiring 1 of the second layer
Insulation from the wiring of the first layer as shown by 31 and 111 is maintained by a dense anodic oxide film (for example, shown by 117) formed on the surface of the wiring of the first layer.

After the state shown in FIG. 4 is obtained, a second interlayer insulating film 134 is formed as shown in FIG. 5 (A). This interlayer insulating film is composed of a silicon oxide film. The thickness shall be 5000Å.

Next, as shown in FIG. 5B, contact holes reaching the first layer wiring and the active layer are formed.

Then, a laminated film consisting of three layers of a titanium film, an aluminum film and a titanium film is formed and further patterned to form various take-out electrodes and a filling portion used in a subsequent dividing step.

That is, in the formation of the opening shown in FIG. 5B, in addition to the formation of the opening used as the contact hole, the formation of the opening used when dividing the wirings of the first and second layers later is formed. Is also done at the same time.

In FIG. 5C, 135 and 137 are the source and drain regions of the thin film transistor which constitutes the peripheral drive circuit. Further, 136 is an extraction electrode (or wiring) from the gate electrode.

Reference numeral 138 denotes a source electrode (or source wiring) of the thin film transistor arranged in the pixel. Reference numerals 139 and 140 are filling portions for dividing the first-layer wiring 112 later. By using this filling portion, the wiring 112, which connects the wirings of the first layer later, is divided in a region where the wiring 112 is required.

Reference numerals 141 and 143 are filling portions for dividing the second layer wiring 131 in a required region. Two
Since all the wirings 131 of the layer are also in a connected state, they are divided at a required position in the final stage.

Reference numeral 142 is a lead wiring of the wiring 131 of the second layer. 144 is an extraction electrode from the first layer wiring.

Next, as shown in FIG. 6A, a third interlayer insulating film 145 is formed. A resin material is used for the third interlayer insulating film. For example, it is configured by using a transparent polyimide resin or acrylic material. When the resin material is used as described above, the surface can be made flat.

The thickness of the third interlayer insulating film 145 is set to several μm (for example, 2 μm).

Next, as shown in FIG. 6B, necessary contact holes are formed.

Then, as shown in FIG. 7, an ITO film 146 forming a transparent electrode is formed on the entire surface by a sputtering method.

Then, as shown in FIG. 8, the ITO film is removed leaving the pixel electrode and the necessary extraction electrode portion.

In FIG. 8, 147 is a pixel electrode.
In the configuration shown in FIG. 8, the pixel electrode 147 is provided so as to cover the thin film transistor. Generally, such a configuration is not preferable due to the problem of parasitic capacitance. However, since the third interlayer insulating film is thick in this embodiment, the problem of parasitic capacitance can be ignored.

On the other hand, by forming the pixel electrode 147 as shown in FIG. 8, the area functioning as a pixel can be maximized and the aperture ratio can be increased.

The openings 148 and 149 are made of the ITO film 146.
This is for advancing the etching as it is at the time of patterning (see FIG. 7) and finally dividing the wiring 112 of the first layer.

Further, the openings 150 and 152 have the ITO film 1
This is for allowing the etching to proceed as it is at the time of patterning 46 (see FIG. 7) and finally dividing the wiring 131 of the second layer.

The step of dividing these wirings is performed after the steps of film formation and etching using plasma are completed. Therefore, in the steps up to that point, the wirings and electrodes of each layer can all be made to have the same potential, and plasma can be suppressed from being concentrated in a specific region. Although not shown, by forming contacts for connecting wirings in different layers, all wirings can have the same potential.

Reference numeral 151 denotes an extraction electrode from the second layer wiring 131. Reference numeral 153 is an extraction electrode from the first layer wiring 113.

When the configuration as shown in this embodiment is adopted, the following significance can be obtained.

(No. 1) Each electrode and wiring can be made to have a common potential in the middle step, and the problem of local concentration of plasma can be solved in the step using plasma.

(2) Since the wiring used for obtaining the significance of (1) above can be divided at the same time as the patterning of the pixel electrode in the final step, it is necessary to increase the number of masks. Therefore, the process can be simplified.

(Which 3) A BM (black matrix) is formed by using an aluminum film formed at the same time as the aluminum wiring of the second layer, and the thin film transistor of the pixel can be shielded by using this BM. . In particular, by using the aluminum film as the light-shielding film of the thin film transistor, it is possible to prevent the thin film transistor from being heated by the projected light.

(Part 4) By anodizing the surface of the BM, it is possible to prevent a short circuit between the BM and the wiring formed on the BM.

Although not clearly shown in this embodiment, the auxiliary capacitance can be formed by arranging the second layer wiring 131 so as to overlap the ITO electrode.

Also, an auxiliary capacitance can be formed between the BM and the ITO electrode.

In this embodiment, an example in which a silicon oxide film is mainly used as the interlayer insulating film is shown. However, a silicon nitride film or a silicon oxynitride film may be used instead of the silicon oxide film. Alternatively, a stacked body of a silicon oxide film and a silicon nitride film, or a stacked body to which a silicon oxynitride film is further added may be used. Further, necessary additives may be added to these insulating films.

[0096]

By utilizing the invention disclosed in this specification, an active matrix type liquid crystal display device can be obtained by a process with a high manufacturing yield. Further, since the black matrix can be formed simultaneously with the formation of the wiring, it is possible to obtain the significance in the manufacturing process that the number of processes is not increased.

In particular, in a structure having a multi-layered wiring, it is possible to realize a structure which suppresses the occurrence of a short circuit between the upper and lower wirings and the occurrence of defects in the process of utilizing plasma.

Further, it is possible to provide a structure in which the pixel electrode formed on the interlayer insulating film and the black matrix are prevented from being short-circuited.

The invention disclosed in this specification can be applied not only to a liquid crystal display device but also to an active matrix type flat panel display using EL elements.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a thin film transistor used in an active matrix liquid crystal display device.

2A to 2C are diagrams showing steps of manufacturing a thin film transistor used in an active matrix liquid crystal display device.

FIG. 3 is a diagram showing a manufacturing process of a thin film transistor used in an active matrix liquid crystal display device.

4A to 4C are diagrams showing steps of manufacturing a thin film transistor used for an active matrix liquid crystal display device.

5A to 5C are diagrams showing steps of manufacturing a thin film transistor used in an active matrix liquid crystal display device.

6A to 6C are diagrams showing steps of manufacturing a thin film transistor used in an active matrix liquid crystal display device.

7A to 7D are diagrams showing steps of manufacturing a thin film transistor used for an active matrix liquid crystal display device.

8A to 8C are diagrams showing steps of manufacturing a thin film transistor used in an active matrix liquid crystal display device.

FIG. 9 is a diagram showing a manufacturing process of a thin film transistor used in a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

101 Glass Substrate 102 Base Film (Silicon Oxide Film) 100 Silicon Films 103 and 104 Active Layers 105 and 106 Remaining Silicon Film Pattern 107 Gate Insulating Film (Silicon Oxide Film) 108 Aluminum Film 109 Dense Anodized Films 110 and 111 Gate Electrodes 112, 113 Wirings 114, 115, 116 Porous anodic oxide film 117 Dense anodic oxide films 118, 119 Gate insulating films 120, 124 Source regions (high concentration impurity regions) 121, 125 Low concentration impurity regions 122 Channel formation regions 123, 127 drain region 128 interlayer insulating film 129 aluminum film 130 aluminum film 131 for forming BM aluminum film 132 for forming wiring 132, 133 dense anodic oxide film 134 interlayer insulating film 135 source electrode 136 from gate electrode Extraction electrode 137 drain wiring 138 source electrodes 139, 140 charging portions 141 and 143 for dividing the wiring 112 charging portion 142 for dividing the wiring 131 142 contact electrode 144 to the wiring 131 contact electrode 145 to the wiring 113 made of resin Interlayer insulating film 146 ITO film 147 Pixel electrodes 148, 149 Opening 150, 152 for dividing the wiring 112 Opening 151 for dividing the wiring 131 Electrode 153 from the wiring 131 Drawer electrode from the wiring 113

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-138484 (JP, A) JP-A-63-280222 (JP, A) JP-A-5-343688 (JP, A) JP-A-7- 128685 (JP, A) JP 63-90155 (JP, A) JP 6-67210 (JP, A) JP 7-234421 (JP, A) JP 6-301052 (JP, A) JP 7-13145 (JP, A) JP 6-242433 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1/1368

Claims (5)

(57) [Claims] 1. A semiconductor device formed on a substrate having an insulating surface.
A body film, a gate wiring , a gate insulating film formed on the semiconductor film, a gate electrode formed on the gate insulating film, and a first electrode formed on the gate electrode and the gate wiring.
And the semiconductor film formed on the first interlayer insulating film.
A light shielding film which is anodized for shielding, the second interlayer insulating film formed on the light shielding film, is formed on the second interlayer insulating film, said semiconductor film
Connect the source electrode to be connected to the gate wiring.
Formed on the tact electrode, the source electrode and the contact electrode
A third interlayer insulating film made of a resin material, and the semiconductor film formed on the third interlayer insulating film.
A pixel electrode to be connected and an electrode to be connected to the contact electrode.
Out and an electrode, wherein the gate lines are made of the same material as the gate electrode, a semiconductor device which is characterized in that the auxiliary capacitance between the light shielding film and the front Symbol pixel electrode is formed. 2. A first formed on a substrate having an insulating surface.
And a second semiconductor film, a gate insulating film formed on the first semiconductor film, an insulating film formed on the second semiconductor film, and a gate electrode formed on the gate insulating film. When the a formed gate wiring on the insulating film, the first formed in said gate electrode and on said gate lines 1
An interlayer insulating film, and the first semiconductor film formed on the first interlayer insulating film.
A light shielding film which is anodized to shield the body layer, a second interlayer insulating film formed on the light shielding film, is formed on the second interlayer insulating film, the first semiconductor
The source electrode connected to the body film and the gate wiring are connected.
And a contact electrode formed on the source electrode and the contact electrode.
A third interlayer insulating film made of a resin material , and the first semiconductor layer formed on the third interlayer insulating film.
Pixel electrode connected to body film and connected to the contact electrode
The gate wiring is made of the same material as the gate electrode, and an auxiliary capacitance is formed between the light shielding film and the pixel electrode.
A semiconductor device characterized in that . 3. A semiconductor formed on a substrate having an insulating surface.
A body film, a gate insulating film formed on the semiconductor film, a gate electrode formed on the gate insulating film, a first interlayer insulating film formed on the gate electrode, and the first insulating film . The semiconductor film is formed on the interlayer insulating film and
Anodized light-shielding film that shields light , wiring formed on the first interlayer insulating film, and second interlayer insulation formed on the light-shielding film and the wiring
A film, and the semiconductor film formed on the second interlayer insulating film,
A source electrode to be connected and a lead wire to be connected to the wire
And a resin formed on the source electrode and the lead wiring.
A third interlayer insulating film made of a material, and the semiconductor film formed on the third interlayer insulating film.
Pixel electrodes to be connected, and drawers to be connected to the lead wires
An electrode, the light-shielding film is made of the same material as the wiring, and an auxiliary capacitance is formed between the light-shielding film and the pixel electrode.
A semiconductor device characterized in that. 4. The light shielding film according to claim 1 , wherein the light shielding film is made of an anodizable metal material or a material containing the metal material as a main component. A semiconductor device having an anodized film formed on its surface. 5. Any one smell <br/> of claims 1 to 4 Te, the material constituting the light shielding film is a semiconductor device characterized by comprising a material mainly composed of aluminum or aluminum.