JPH09181210A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect the wiring pattern on a semiconductor carrier against corrosion. SOLUTION: In a semiconductor carrier 4 where a semiconductor element 3 is bonded using Au bumps 2 through a conductive adhesive, a wiring pattern 8 is formed on the upper surface thereof on the inside of a fillet part 7a covering the circumferential end part of semiconductor element 3 while being coated with the fillet part 7a. This structure prevent the wiring pattern 8 on the semiconductor carrier 4 from being exposed and corroded through oxidation by the air or contaminant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which protects an integrated circuit portion of a semiconductor element, ensures stable electrical connection between an external device and the semiconductor element, and enables the highest density mounting. The present invention relates to a manufacturing method. With the semiconductor device and the manufacturing method thereof according to the present invention, it is easy to miniaturize information communication equipment, office electronic equipment, household electronic equipment, measuring equipment, industrial electronic equipment such as assembly robots, medical electronic equipment, electronic toys and the like. It is something to do.

[0002]

2. Description of the Related Art Recently, as a method for mounting a semiconductor element on a circuit board, a package using a flip chip mounting method has been studied.

A conventional semiconductor device will be described below with reference to the drawings. FIG. 14 is a cross-sectional view of a conventional semiconductor device called a chip size package (CSP), FIG.
5 is its plan view, and FIG. 16 is its bottom view. Note that FIG. 14 shows a cross section taken along line AA1 of FIG.

The structure of a conventional semiconductor device will be described with reference to FIGS. 14, 15 and 16.

As shown in FIG. 14, the surface electrode pad 1
The semiconductor element 3 on which the Au bumps 2 are formed is bonded to the semiconductor carrier 4, which is a multi-layer circuit board, face down, that is, with the front surface side facing down. A plurality of electrodes 5 for conduction with the semiconductor element 3 are formed on the upper surface of the semiconductor carrier 4, and the electrodes 5 and the two-stepped Au bumps 2 formed on the semiconductor element 3 are made of a conductive adhesive. It is joined at 6. Then, the gap between the bonded semiconductor element 3 and the semiconductor carrier 4 and the end of the semiconductor element 3 are filled and covered with the epoxy sealing resin 7. The end portion of the semiconductor element 3 and the portion covering the semiconductor carrier 4 are the fillet portions 7 a of the sealing resin 7.

Here, as shown in FIG. 14, the electrode 5 is laid out on the surface of the semiconductor carrier 4 by the wiring pattern 8 and electrically connected to the external electrode terminal 10 on the back surface of the semiconductor carrier 4 by the via 9. The wiring pattern 8 on the front surface of the semiconductor carrier 4 is routed inside the semiconductor carrier 4 which is a laminated substrate by the via 9, and the external electrode terminals 10 are arranged on the back surface of the semiconductor carrier 4 as shown in FIG. Configure.

Next, a conventional method of manufacturing a semiconductor device will be described with reference to the drawings. 17 to 21 are cross-sectional views showing a conventional method of manufacturing a semiconductor device for each step.

First, as shown in FIG. 17, Au bumps 2 (Au two-step protrusions) are formed on the electrode pads 1 of the semiconductor element 3 by a wire bonding method (ball bonding method).
To form In this method, as shown in FIG. 18, a ball formed at the tip of the Au wire 11 is thermally pressed against an aluminum electrode to form a lower step portion of the two-step protrusion (first bond), and further the capillary 12 is moved. The Au wire loop thus formed is used to form the upper step portion of the two-step protrusion (second bond). In the above state,
Since the height of the Au two-step protrusion is not uniform and lacks the flatness of the crown, the Au two-stage protrusion is pressed to make the height uniform and the crown flat, that is, so-called leveling.

Next, as shown in FIG. 19, the conductive adhesive 6 is supplied to the Au bumps 2 on the semiconductor element 3. As the conductive adhesive 6, an adhesive made of, for example, an epoxy resin as a binder and an Ag-Pd alloy as a conductor filler is used in consideration of reliability, thermal stress, and the like as described above.

Next, as shown in FIG. 20, the Au bumps 2 to which the conductive adhesive 6 is supplied on the semiconductor element 3 by the flip chip method, which is a method of mounting the semiconductor element 3 with the surface thereof facing downward, Surface electrode 5 is wiring pattern 8
The surface of the semiconductor carrier 4 is routed to the front surface of the semiconductor carrier 4 by the via 9 and is internally routed by the via 9 and is electrically connected to the external electrode terminal 10 on the back surface thereof. Let it harden.

Finally, as shown in FIG. 21, the epoxy type encapsulating resin 7 is injected into the peripheral end portion of the semiconductor element 3 and the gap formed between the semiconductor element 3 and the semiconductor carrier 4 to keep a constant amount. The sealing resin was cured at a temperature and resin-molded to complete the semiconductor device.

[0012]

However, in the conventional semiconductor device, as shown in FIG.
The wiring pattern 8 for drawing the electrode 5 on the surface of the sealing resin 7
Since it is exposed from the fillet portion 7a, it is exposed to the air and is corroded by oxidation.
In other words, conventionally, no attention has been paid to solving the problem that the wiring pattern corrodes, so that the fillet portion is formed with a small size.

The present invention pays attention to the fact that corrosion occurs due to the exposure of the wiring pattern on the semiconductor carrier, and pays attention to the arrangement of the wiring pattern for the wiring provided on the surface of the semiconductor carrier, the sealing resin and the fillet portion thereof. An object of the present invention is to provide a semiconductor device having a structure that prevents corrosion of a wiring pattern on a semiconductor carrier.

[0014]

To solve the above problems, a semiconductor device according to the present invention has the following configuration. That is, a semiconductor carrier having a plurality of electrodes on the upper surface, a wiring pattern for routing the electrodes, external electrode terminals electrically connected to the electrodes arranged on the bottom surface, a semiconductor element bonded to the upper surface of the semiconductor carrier, and a semiconductor element Provided on the upper electrode pad, a plurality of bump electrodes connecting the semiconductor element and a plurality of electrodes on the semiconductor carrier, and connecting a plurality of electrodes and bump electrodes on the upper surface of the semiconductor carrier,
A semiconductor device including a conductive adhesive provided on a bump electrode, a first resin filling a space between a semiconductor element and a semiconductor carrier, and a second resin covering a peripheral end portion of the semiconductor element. The wiring pattern on the semiconductor carrier is arranged inside the fillet portion, which is the second resin region covering the peripheral edge of the semiconductor element, and is covered with the fillet. When the wiring pattern is arranged on the semiconductor carrier in a region other than the region where the semiconductor element is bonded, the wiring pattern region on the carrier is entirely covered with resin.

According to the method of manufacturing a semiconductor device of the present invention,
In particular, in the resin encapsulation step, the first resin injects the encapsulation resin into the gap between the semiconductor element and the semiconductor carrier for encapsulation, and the second resin encloses all the wiring pattern regions on the semiconductor carrier. It is to coat. A semiconductor carrier having a convex portion or a concave portion at its peripheral end is used, and in the resin sealing step, the first resin is used to inject a sealing resin into the gap between the semiconductor element and the semiconductor carrier to seal the semiconductor element. At the same time, the second resin is coated from the end of the semiconductor element to the protrusion or recess of the peripheral edge of the semiconductor carrier to completely cover the wiring pattern region on the semiconductor carrier.

With the above structure, in the semiconductor device of the present invention, the wiring pattern on the semiconductor carrier is arranged inside the fillet portion, which is the second resin region covering the peripheral edge of the semiconductor element, and is covered with the fillet. Therefore, it is possible to prevent the wiring pattern on the semiconductor carrier from being exposed and prevent corrosion due to air oxidation or oxidation due to contamination. Further, when the wiring pattern is arranged in a region other than the region where the semiconductor element is bonded on the semiconductor carrier, the wiring pattern region on the carrier is entirely covered with the resin, and therefore the wiring pattern is similarly exposed. Prevents corrosion by oxidation due to air oxidation and pollution.

In the method of manufacturing a semiconductor device of the present invention, particularly, in the resin sealing step, the first resin is used to inject and seal the sealing resin into the gap between the semiconductor element and the semiconductor carrier, and Since the wiring pattern region on the semiconductor carrier is also entirely covered with the resin No. 2, the wiring pattern on the semiconductor carrier is prevented from being exposed, and corrosion due to air oxidation or oxidation due to contamination is prevented. A semiconductor carrier having a convex portion or a concave portion at its peripheral end is used, and in the resin sealing step, the first resin is used to inject a sealing resin into the gap between the semiconductor element and the semiconductor carrier to seal the semiconductor element. At the same time, the second resin covers from the end of the semiconductor element to the protrusions or recesses at the peripheral edge of the semiconductor carrier and completely covers the wiring pattern area on the semiconductor carrier, so that the wiring pattern on the semiconductor carrier is exposed. It is possible to prevent corrosion due to air oxidation and oxidation due to pollution.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of this semiconductor device, FIG. 2 is a plan view thereof, and FIG. 3 is a bottom view thereof. 1 is shown in FIG.
2 shows a cross section taken along line A-A1 of FIG.

As shown in FIGS. 1, 2 and 3, the semiconductor element 3 in which the two-stepped Au bumps 2 are formed on the electrode pad 1 on the surface of the semiconductor element 3 has the surface side down and the ceramic is used as an insulating substrate. It is bonded to the semiconductor carrier 4, which is a multilayer circuit board. A plurality of electrodes 5 for electrical connection with the semiconductor element 3 are formed on the upper surface of the semiconductor carrier 4.
The Au bumps 2 formed on the semiconductor element 3 are joined with a conductive adhesive 6. The conductive adhesive 6 is previously supplied to the Au bump 2. The gap between the bonded semiconductor element 3 and the semiconductor carrier 4 and the end of the semiconductor element 3 are filled and covered with an epoxy-based encapsulating resin 7. In addition, the end portion of the semiconductor element 3 and the portion that overlaps with the semiconductor carrier 4 are sealed resin 7 as a second resin portion.
Of the fillet portion 7a.

Although the bump electrodes are Au bumps 2, other than Au (gold), Pt (platinum), Ag (silver), A
1 (aluminum), Cu (copper), or the like may be used.
The sealing resin 7 is a resin obtained by adding aluminum nitride (AlN) or silicon carbide (SiC), which is a highly heat conductive ceramic, to an epoxy resin as a filler.

As shown in FIG. 3, a metallized metal layer A is formed on the bottom surface of the semiconductor carrier 4, which is a multilayer circuit board.
Circular external electrode terminals 10 made of g-Pd are formed in a grid pattern at regular intervals. This external electrode terminal 10
The arrangement of the electrodes 5 on the semiconductor carrier 4 is the semiconductor carrier 4
It is routed inside and arranged in a grid on the bottom. The arrangement of the external electrode terminals 10 can be freely selected according to the purpose, such as a staggered arrangement other than the grid shape. Also Ag-
Besides Pd, Cu and Au may be used as the metallized metal layer. Further, when solder is used for the conductive adhesive 6 used for Au plating for the purpose of preventing the surface oxidation of the external electrode material and for joining the Au bumps 2 of the semiconductor element 3 and the semiconductor carrier 4, the soldering of metallization is eroded. Ni plating is performed for the purpose of prevention.

Here, in the semiconductor carrier 4 in the semiconductor device of the present embodiment, as shown in FIG. 2, the electrode 5 on the surface is routed by the wiring pattern 8 and is routed inside by the via 9. Although the semiconductor carrier is electrically connected to the external electrode terminal 10 on the back surface thereof, the area around the wiring pattern 8 is the fillet portion 7 of the sealing resin 7.
Within the area a. Therefore, the arrangement area of the wiring pattern 8 is in the area where the semiconductor element 3 is joined on the semiconductor carrier 4 and in the area of the fillet portion 7a around the area. Note that, in FIG. 2, the wiring pattern 8 and the via 9 covered with the fillet portion 7a are shown by solid lines for convenience.

In order to arrange the wiring pattern 8 in the area where the semiconductor element 3 is bonded on the semiconductor carrier 4 and in the area of the fillet portion 7a around the area, the wiring pattern 8 is formed on the semiconductor carrier 4 in particular. The semiconductor carriers 3 are arranged at high density in the region where the semiconductor elements 3 of
It can be realized by routing in the internal area. Therefore, the vias 9 of the wiring pattern 8 also lead to high density routing inside the semiconductor carrier 4, so that the number of stacked semiconductor carriers 4 that are multilayer substrates is 3 or more. As shown in the internal configuration diagram of the semiconductor carrier 4 of FIG. 4, the wiring pattern 8 for arranging the electrodes 5 on the surface of the semiconductor carrier 4 has a region where the semiconductor element 3 is joined and a sealing resin 7 around the region. Although it is arranged in the region where the fillet portion 7a is formed, it is routed outside the region where the semiconductor element 3 is joined by the via 9 between the first layer and the second layer of the substrate, Between the second layer and the third layer, they are arranged so as to be arranged in a lattice pattern on the back surface of the semiconductor carrier 4. Then, the external electrode terminals 1 are formed on the wiring patterns 8 that are routed and arranged in a lattice on the back surface of the semiconductor carrier 4.
0 is provided.

Another example of the embodiment of the semiconductor device of the present invention will be described. FIG. 5 is a sectional view of the semiconductor device of this embodiment.

As shown in FIG. 5, a semiconductor element 3 having Au bumps 2 in a two-step shape formed on an electrode pad 1 on the surface is
It is bonded to the semiconductor carrier 4 which is a multi-layer circuit board with ceramics as an insulating base with the front side facing down. A plurality of electrodes 5 for electrical connection with the semiconductor element 3 are formed on the upper surface of the semiconductor carrier 4, and the electrodes 5 and the Au bumps 2 formed on the semiconductor element 3 are bonded with a conductive adhesive 6. ing. The conductive adhesive 6 is previously supplied to the Au bump 2. The gap between the joined semiconductor element 3 and the semiconductor carrier 4 and the entire end portion of the semiconductor element 3 are filled and covered with the epoxy-based sealing resin 7.
The end of the semiconductor element 3 and the portion that covers the semiconductor carrier 4 are the extended resin portion 7b of the sealing resin 7.

As described above, in the present embodiment, unlike the embodiment shown in FIG. 1, as shown in the plan view of FIG. 6, the routing area of the wiring pattern 8 on the semiconductor carrier 4 is a semiconductor. The region is not limited to the region where the semiconductor element 3 on the carrier 4 is joined, but is a region on the surface of the semiconductor carrier 4. Therefore, in contrast to the structure in which the wiring pattern 8 is covered with the fillet 7a in the embodiment shown in FIG. 1, in the present embodiment, the extension resin portion 7b having a larger covering area than the fillet 7a is provided to connect the wiring. The pattern 8 is covered. In FIG. 6, the wiring pattern 8 and the via 9 covered with the fillet portion 7a are shown by solid lines for convenience.

Since the wiring pattern 8 on the surface of the semiconductor carrier 4 is covered with the extended resin portion 7b, it is possible to prevent the wiring pattern from being exposed and corroded by air oxidation or oxidation due to contamination.

An embodiment of the method for manufacturing a semiconductor device of the present invention will be described. First, an example of a method for manufacturing the semiconductor device of the embodiment shown in FIG. 5 will be described with reference to FIGS.
This will be described with reference to the process chart of No. 1.

First, as shown in FIG. 7, with respect to the semiconductor element 3 having the electrode pad 1, a wire bonding method (ball bonding method) is used to form A on the electrode pad 1.
The u bump 2 (Au two-step protrusion) is formed. This method
As shown in the enlarged view of FIG. 8, the ball formed at the tip of the Au wire 11 is thermocompression-bonded to the electrode pad 1 that is an aluminum electrode to form the lower step portion 2a of the two-step protrusion (first bond), and The Au wire loop formed by moving the capillary 12 forms the upper step portion 2b of the two-step protrusion (second bond). After the Au bumps 2 are formed, the height of the Au two-step protrusion is not uniform and the flatness of the crown is also lacking. Flattening of the top, so-called leveling is performed.

Next, a conductive adhesive 6 containing Ag-Pd as a conductive substance is applied to the rotating disk by a doctor blade method to an appropriate thickness. At this time, the conductive adhesive 6 is stirred on a disk with a squeegee for the purpose of always maintaining a fresh surface. Au bump 2 on conductive adhesive 6
As shown in FIG. 9, by a method of pressing the semiconductor element 3 provided with the element and then pulling it up, a so-called transfer method, as shown in FIG.
A conductive adhesive 6 is supplied to the upper step portion 2b region of the bump 2. As the conductive adhesive 6, in consideration of reliability, thermal stress and the like, for example, an epoxy resin is used as a binder and an adhesive made of Ag—Pd alloy is used as a conductor filler.

Next, as shown in FIG.
By the flip-chip method, which is a method of mounting with the surface facing down, the Au bumps 2 on the semiconductor element 3 to which the conductive adhesive 6 is supplied and the electrodes 5 on the surface are laid out by the wiring pattern 8, and the vias 9 are formed. After that, the electrode 5 of the semiconductor carrier 4 which is routed inside and conductively connected to the external electrode terminal 10 on the back surface thereof is aligned and bonded with good positional accuracy, and then thermoset at a constant temperature. When the conductive adhesive 6 is, for example, an epoxy resin as a binder and a conductive adhesive made of an Ag-Pd alloy as a conductive filler is used, the curing condition is 100 ° C. for 1 hour and 1 hour.
The joining is completed by heating at a temperature of 20 ° C. for 2 hours.

Then, as shown in FIG. 11, the epoxy-based encapsulating resin 7 is injected into the gap formed between the semiconductor element 3 and the semiconductor carrier 4 and further into the peripheral end portion of the semiconductor element 3 to keep it constant. It is cured at the temperature of and is resin-molded. As a method of this resin molding, the semiconductor element 3 and the semiconductor carrier 4 are injected from one direction by using the injection nozzle of the sealing resin 7.
The resin is injected into the gap formed between the gaps to fill the gap, and then the extended resin portion 7b is formed at the peripheral end portion of the semiconductor element 3 and sealed. As a result, the extended resin portion 7b is formed in the area of the wiring pattern 8 exposed on the surface of the semiconductor carrier 4, so that the wiring pattern 8 is exposed and can be prevented from corroding due to air oxidation or oxidation due to contamination. This is because the wiring pattern 8 is composed of a copper (Cu) layer as a base and a nickel (Ni) layer and a gold (Au) layer (flash) formed thereon, and the surface thereof is covered by the extension resin portion 7b. By blocking the air, the corrosion of the wiring pattern 8 due to the oxidation growth of the nickel (Ni) layer is prevented.

As another resin sealing structure, the sealing resin 7 is injected from one direction into the gap formed between the semiconductor element 3 and the semiconductor carrier 4 by using an injection nozzle, and the gap is filled to fillet. After forming the portion, the extension resin portion 7b may be formed using another resin, for example, an insulating resin such as a polyimide resin. By forming the extension resin portion 7b using a resin such as a polyimide resin, the polyimide resin has transparency, so that the arrangement of the wiring pattern 8 can be confirmed even after sealing, and also alpha ray countermeasures can be taken. it can. The resin forming the extension resin portion 7b is
A resin having good adhesion with the semiconductor carrier 4 and high reliability is used.

Next, another example of the method for manufacturing the semiconductor device of the embodiment shown in FIG. 5 will be described with reference to FIGS.
3 will be described.

In the present embodiment, as shown in the plan view of FIG. 12, as the semiconductor carrier 4 on which the semiconductor element is mounted, a semiconductor carrier having a convex portion or a concave portion formed at the peripheral end portion is used. Then, continuous protrusions 13 are formed on the peripheral end portion of the semiconductor carrier 4 other than the region where the wiring pattern 8 is arranged. By using the semiconductor carrier 4 having such a structure, as shown in FIG. 13, when the extension resin portion 7b is formed in the resin sealing step after the semiconductor element 3 is bonded to the semiconductor carrier 4,
The injection of the sealing resin 7 prevents the resin from squeezing out from the semiconductor carrier 4, and the sealing accuracy can be improved. Note that, in FIG. 12, the wiring pattern 8 and the via 9 covered by the fillet portion 7a are shown by solid lines for convenience.

For the semiconductor device in which the external electrode terminals are arranged on the back surface as shown in the embodiment of the present invention, the resin protruding due to the resin leakage wraps around to the back surface and adheres to the external electrode terminals. It is extremely important to prevent this, and it is an effective means in the resin sealing step to form a convex portion or a concave portion on the peripheral end portion of the surface of the semiconductor carrier 4 so as to have a function as a stopper. The protrusion 1
3 may be formed of a resin having a thermal expansion coefficient equivalent to that of the semiconductor carrier 4, or may be integrally formed when the semiconductor carrier 4 is manufactured. Further, by removing the peripheral edge of the semiconductor carrier 4 by cutting or the like to form a recess,
A recess can be formed.

As an example of manufacturing the semiconductor carrier 4 shown in this embodiment, first, ceramic powder is put into a mixing mill together with glass powder and a solvent, and rotary mixing and pulverization are performed. Then, an organic binder is added and further mixed. This ceramic powder is usually composed mainly of alumina, but powders of aluminum nitride (AlN), silicon carbide (SiC), etc. are also added to improve the thermal conductivity.
After thorough mixing, the resulting slurry, a so-called slurry, is applied on the carrier sheet in an arbitrary thickness to form a green sheet. A doctor blade method or the like is used to adjust the thickness. By drying the solvent using infrared rays and hot air, the slurry on the carrier sheet becomes a green sheet which is rich in elasticity and excellent in the permeability of the paste solvent at the time of printing the conductive paste. If the wiring rule is 200 μm or more as an alignment method for this green sheet, a guide hole is directly provided in the green sheet to make the alignment rule 200 μm.
If less than the above, stick to the holding frame with guide holes.

Next, holes are formed in the front and back surfaces of the green sheet by mechanical processing in the portions where electrical conduction is required. These holes are filled with a conductive paste mainly containing Cu powder by a printing method. After printing the necessary circuit on the surface of the green sheet,
It is dried and the printed circuit is embedded in the green sheet with an appropriate load. The purpose of this is to flatten the surface of the green sheet on which the circuit is printed, thereby preventing lamination failure in the next lamination step, so-called delamination. In the laminating step, the laminated green sheets are accurately pressed by the guide holes provided in the green sheet or the guide holes of the holding frame to firmly bond the green sheets.

Sn-Pb eutectic solder cream is applied to the grid electrodes formed on the back surface of the ceramic carrier thus completed. Then, after supplying the high melting point solder balls to the coated solder cream using an alignment jig,
The semiconductor carrier 4 is formed by forming external electrode terminals, which are solder bumps, by heating and melting using a reflow furnace or the like.

As described above, in the semiconductor device of the present invention, the semiconductor device of the present invention has a plurality of electrodes on the top surface, a wiring pattern for routing the electrodes, and external electrode terminals electrically connected to the electrodes arranged on the bottom surface. A semiconductor carrier having, a semiconductor element bonded to the upper surface of the semiconductor carrier, a plurality of bump electrodes provided on the electrode pad on the semiconductor element, connecting the semiconductor element and a plurality of electrodes on the semiconductor carrier,
A plurality of electrodes on the upper surface of the semiconductor carrier are connected to the bump electrodes, a conductive adhesive provided on the bump electrodes, a first resin filling between the semiconductor element and the semiconductor carrier, and a peripheral edge of the semiconductor element. In a semiconductor device including a second resin covering a portion, a wiring pattern on a semiconductor carrier is arranged inside a fillet portion which is a second resin region covering a peripheral end portion of a semiconductor element. , Covered by its fillet. Further, when the wiring pattern is arranged in a region other than the region where the semiconductor element is bonded on the semiconductor carrier, the entire wiring pattern region on the carrier is covered with resin. As a result, the wiring pattern on the semiconductor carrier is exposed and can be prevented from being oxidized and corroded by air oxidation or contamination.

In the method of manufacturing a semiconductor device of the present invention, particularly, in the resin sealing step, the first resin is used to inject and seal the sealing resin into the gap between the semiconductor element and the semiconductor carrier, and The resin also covers the entire wiring pattern area on the semiconductor carrier. A semiconductor carrier having a convex portion or a concave portion at its peripheral end is used, and in the resin sealing step, the first resin is used to inject a sealing resin into the gap between the semiconductor element and the semiconductor carrier to seal the semiconductor element. At the same time, the second resin is coated from the end of the semiconductor element to the convex or concave portion at the peripheral end of the semiconductor carrier to completely cover the wiring pattern region on the semiconductor carrier. By covering the wiring pattern region, the wiring pattern is exposed and can be prevented from corroding due to air oxidation or oxidation due to contamination.

[0043]

In the semiconductor device according to the present invention, the wiring pattern region on the carrier is entirely covered with resin to prevent the wiring pattern on the semiconductor carrier from being exposed and to prevent corrosion due to air oxidation or oxidation due to contamination. it can.

In the method of manufacturing a semiconductor device of the present invention, in the resin sealing step, the first resin is used to inject and seal the sealing resin into the gap between the semiconductor element and the semiconductor carrier, and the second resin is also used. Thus, the entire wiring pattern area on the semiconductor carrier is also covered. A semiconductor carrier having a convex portion or a concave portion at its peripheral end is used, and in the resin sealing step, the first resin is used to inject a sealing resin into the gap between the semiconductor element and the semiconductor carrier to seal the semiconductor element. At the same time, the second resin is coated from the end of the semiconductor element to the convex or concave portion at the peripheral end of the semiconductor carrier to completely cover the wiring pattern region on the semiconductor carrier.
Therefore, by covering the wiring pattern area,
Corrosion due to air oxidation or oxidation due to pollution can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view of an example of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a plan view of an example of an embodiment of a semiconductor device of the present invention.

FIG. 3 is a bottom view of an example of the embodiment of the semiconductor device of the present invention.

FIG. 4 is an internal configuration diagram of a semiconductor carrier in an example of an embodiment of a semiconductor device of the present invention.

FIG. 5 is a sectional view of another example of the embodiment of the semiconductor device of the present invention.

FIG. 6 is a plan view of another example of the embodiment of the semiconductor device of the present invention.

FIG. 7 is a sectional process diagram of an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a sectional process diagram of an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a sectional process diagram of an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a sectional process drawing of an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a sectional process diagram of an example of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a plan view of another example of the embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 13 is a sectional process drawing of another example of the embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 14 is a sectional view of a conventional semiconductor device.

FIG. 15 is a plan view of a conventional semiconductor device.

FIG. 16 is a bottom view of a conventional semiconductor device.

FIG. 17 is a process sectional view for explaining a conventional method for manufacturing a semiconductor device.

FIG. 18 is a process sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 19 is a process cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 20 is a process sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 21 is a process sectional view for explaining the manufacturing method of the conventional semiconductor device.

[Explanation of symbols]

 1 Electrode Pad 2 Au Bump 3 Semiconductor Element 4 Semiconductor Carrier 5 Electrode 6 Conductive Adhesive 7 Sealing Resin 8 Wiring Pattern 9 Via 10 External Electrode Terminal 11 Au Wire 12 Capillary 13 Protrusion

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yuichi Sakata 1-1, Sachimachi, Takatsuki City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd. (72) Shinji Ishino 1-1, Sachimachi, Takatsuki City, Osaka Matsushita Electronics Industry Within the corporation

Claims (7)

[Claims] 1. A semiconductor carrier having a plurality of electrodes on an upper surface thereof, a wiring pattern for routing the electrodes, and external electrode terminals arranged on the bottom surface and electrically connected to the electrodes, and a semiconductor bonded to the upper surface of the semiconductor carrier. An element, a plurality of bump electrodes provided on the electrode pad on the semiconductor element and connecting the semiconductor element and a plurality of electrodes on the semiconductor carrier, between the semiconductor element and the semiconductor carrier, and the semiconductor A semiconductor device, comprising: a resin that fills and covers an element peripheral end portion, and the wiring pattern is arranged in a region of the semiconductor carrier to which a semiconductor element is joined. 2. A semiconductor carrier having a plurality of electrodes on an upper surface thereof, a wiring pattern for routing the electrodes, and external electrode terminals arranged on the bottom surface and electrically connected to the electrodes, and a semiconductor bonded to the upper surface of the semiconductor carrier. An element, a plurality of bump electrodes provided on the electrode pad on the semiconductor element, connecting the semiconductor element and a plurality of electrodes on the semiconductor carrier, and a plurality of electrodes and bump electrodes on the upper surface of the semiconductor carrier. A conductive adhesive that is connected to the bump electrode, fills the space between the semiconductor element and the semiconductor carrier, and a second resin that covers the peripheral edge of the semiconductor element. The semiconductor device is characterized in that the wiring pattern is made of a resin and is arranged inside a second resin region that covers the peripheral edge portion of the semiconductor element. 3. A semiconductor carrier having a plurality of electrodes on an upper surface thereof, a wiring pattern for routing the electrodes, and external electrode terminals arranged on the bottom surface and electrically connected to the electrodes, and a semiconductor bonded to the upper surface of the semiconductor carrier. An element, a plurality of bump electrodes provided on the electrode pad on the semiconductor element, connecting the semiconductor element and a plurality of electrodes on the semiconductor carrier, and a plurality of electrodes and bump electrodes on the upper surface of the semiconductor carrier. A conductive adhesive that is connected to the bump electrode, fills the space between the semiconductor element and the semiconductor carrier, and a second resin that covers the peripheral edge of the semiconductor element. And a second resin which covers the peripheral edge portion of the semiconductor element on the semiconductor carrier and covers the entire wiring pattern region. Place. 4. A semiconductor carrier having a plurality of electrodes on a top surface, a wiring pattern for routing the electrodes, and external electrode terminals arranged on the bottom surface and electrically connected to the electrodes, and a semiconductor bonded to the top surface of the semiconductor carrier. An element, a plurality of bump electrodes provided on the electrode pad on the semiconductor element, connecting the semiconductor element and a plurality of electrodes on the semiconductor carrier, and a plurality of electrodes and bump electrodes on the upper surface of the semiconductor carrier. A conductive adhesive that is connected to the bump electrode, fills the space between the semiconductor element and the semiconductor carrier, and a second resin that covers the peripheral edge of the semiconductor element. The semiconductor carrier has a convex portion or a concave portion at a peripheral end portion thereof, and a region from the peripheral end portion of the semiconductor element to the convex portion or the concave portion is covered with a second resin. A semiconductor device characterized by being provided. 5. The semiconductor device according to claim 2, wherein the second resin covering the peripheral edge portion of the semiconductor element on the semiconductor carrier is a polyimide resin. 6. A step of forming a bump electrode on an electrode pad on a semiconductor element, a step of forming a conductive adhesive on the bump electrode formed on the semiconductor element, and a bump connecting electrode on the first surface. A bump connecting electrode on the semiconductor carrier and a bump electrode on the semiconductor element are bonded to the semiconductor carrier having a wiring pattern and external electrode terminals on the second surface via the conductive adhesive. Injecting the sealing resin into the process and the gap between the semiconductor element and the semiconductor carrier,
Curing and resin-sealing, wherein the resin-sealing step is performed by injecting a sealing resin into the gap between the semiconductor element and the semiconductor carrier with the first resin and sealing the second resin. 2. A method of manufacturing a semiconductor device, which comprises the step of completely covering the wiring pattern region on the semiconductor carrier. 7. A step of forming a bump electrode on an electrode pad on a semiconductor element, a step of forming a conductive adhesive on the bump electrode formed on the semiconductor element, and a bump connecting electrode on the first surface. For a semiconductor carrier having a wiring pattern, a convex portion or a concave portion at a peripheral end portion, and an external electrode terminal on a second surface, bump connecting electrodes on the semiconductor carrier and bump electrodes on the semiconductor element are described above. The method includes a step of joining via a conductive adhesive and a step of injecting a sealing resin into a gap between the semiconductor element and the semiconductor carrier and curing the resin to perform resin sealing. While sealing resin is injected into the gap between the semiconductor element and the semiconductor carrier with the resin of No. 2, the second resin covers from the end of the semiconductor element to the convex portion or the concave portion of the peripheral edge of the semiconductor carrier. , Said half A method of manufacturing a semiconductor device, which is a step of covering the entire wiring pattern region on a conductor carrier.