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JPH09181119A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JPH09181119A
JPH09181119A JP34023195A JP34023195A JPH09181119A JP H09181119 A JPH09181119 A JP H09181119A JP 34023195 A JP34023195 A JP 34023195A JP 34023195 A JP34023195 A JP 34023195A JP H09181119 A JPH09181119 A JP H09181119A
Authority
JP
Japan
Prior art keywords
semiconductor
electrode
carrier
semiconductor carrier
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34023195A
Other languages
Japanese (ja)
Inventor
Akira Saito
彰 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP34023195A priority Critical patent/JPH09181119A/en
Publication of JPH09181119A publication Critical patent/JPH09181119A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To dissolve connection failures between a semiconductor element and a semiconductor carrier by bumping by a method wherein a bump electrode on the semiconductor carrier and an electrode pad of the semiconductor element are composed of a low melting metal, and connected by melting with respect to metals. SOLUTION: A bump electrode 15 composed of a low melting metal is formed on an electrode 14 on the side of a semiconductor carrier 13, and by a metal connection between the bump electrode 15 and an electrode pad 12 on a semiconductor element 11, the semiconductor element 11 is connected to the semiconductor carrier 13. Further, the bump electrode 15 is formed on the electrode 14 on the side of the semiconductor carrier 13 and they are melt-connected by the electrode pad 12 on the semiconductor element 11 and pressing. Thus, it is possible to enhance reliability such as heat-resistance, wet-resistance or the like. Further, it is possible to connect by mitigating variations in a height of the bump electrode by variations of levelling of the bump electrode, and to reduce connection fail.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子の集積回
路部を保護し、かつ外部装置と半導体素子の電気的接続
を安定に確保し、さらにもっとも高密度な実装を可能と
した半導体装置およびその製造方法に関するものであ
る。本発明の半導体装置およびその製造方法により、情
報通信機器、事務用電子機器、家庭用電子機器、測定装
置、組み立てロボット等の産業用電子機器、医療用電子
機器、電子玩具等の小型化を容易にするものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which protects an integrated circuit portion of a semiconductor element, ensures stable electrical connection between an external device and the semiconductor element, and enables the highest density mounting. The present invention relates to a manufacturing method. With the semiconductor device and the manufacturing method thereof according to the present invention, it is easy to miniaturize information communication equipment, office electronic equipment, household electronic equipment, measuring equipment, industrial electronic equipment such as assembly robots, medical electronic equipment, electronic toys and the like. It is something to do.

【0002】[0002]

【従来の技術】近年、半導体素子を回路基板に実装する
方法として、フリップチップ実装工法を用いたパッケー
ジの検討がなされている。
2. Description of the Related Art Recently, as a method for mounting a semiconductor element on a circuit board, a package using a flip chip mounting method has been studied.

【0003】以下、従来の半導体装置について図面を参
照しながら説明する。図7はチップサイズパッケージ
(CSP)と呼ばれる、従来の半導体装置の平面図、図
8はその底面図、図9は図7のA−A1線に沿った断面
図である。
A conventional semiconductor device will be described below with reference to the drawings. 7 is a plan view of a conventional semiconductor device called a chip size package (CSP), FIG. 8 is a bottom view thereof, and FIG. 9 is a sectional view taken along line AA1 of FIG.

【0004】図7、図8および図9において、従来の半
導体装置の構造について説明する。図示するように、表
面の電極パッド1にAuバンプ2の形成された半導体素
子3がフェースダウン方式、すなわち表面側を下向きに
して多層回路基板である半導体キャリア4に接合されて
いる。半導体キャリア4の上面には半導体素子3との導
通のための複数の電極5が形成されており、この電極5
と半導体素子3上に形成された二段形状のAuバンプ2
とが導電性接着剤6で接合されている。そして接合され
た半導体素子3と半導体キャリア4との間の隙間と、半
導体素子3の端部はエポキシ系封止樹脂7で充填被覆さ
れている。半導体素子3の端部と半導体キャリア4にか
かる部分は、封止樹脂7のフィレット部である。
The structure of a conventional semiconductor device will be described with reference to FIGS. 7, 8 and 9. As shown in the figure, a semiconductor element 3 having Au bumps 2 formed on an electrode pad 1 on the front surface is bonded to a semiconductor carrier 4, which is a multilayer circuit board, in a face-down manner, that is, with the front surface side facing downward. A plurality of electrodes 5 for electrical connection with the semiconductor element 3 are formed on the upper surface of the semiconductor carrier 4.
And a two-stage Au bump 2 formed on the semiconductor element 3
And are joined by a conductive adhesive 6. The gap between the bonded semiconductor element 3 and the semiconductor carrier 4 and the end of the semiconductor element 3 are filled and covered with an epoxy-based sealing resin 7. The end portion of the semiconductor element 3 and the portion covering the semiconductor carrier 4 are fillet portions of the sealing resin 7.

【0005】ここで半導体キャリア4上の電極5は、配
線パターン8により半導体キャリア4表面で引き回さ
れ、ビア9により半導体キャリア4の裏面の外部電極端
子10に導通されている。なお、半導体キャリア4表面
の配線パターン8は、ビア9により積層基板である半導
体キャリア4の内部で引き回されて、図8に示すよう
に、半導体キャリア4の裏面で外部電極端子10の配列
を構成する。
Here, the electrode 5 on the semiconductor carrier 4 is routed on the surface of the semiconductor carrier 4 by the wiring pattern 8 and is electrically connected to the external electrode terminal 10 on the back surface of the semiconductor carrier 4 by the via 9. The wiring pattern 8 on the surface of the semiconductor carrier 4 is routed inside the semiconductor carrier 4 which is a laminated substrate by the via 9, and the external electrode terminals 10 are arranged on the back surface of the semiconductor carrier 4 as shown in FIG. Configure.

【0006】次に従来の半導体装置の製造方法について
図面を参照しながら説明する。図10〜図13は従来の
半導体装置の製造方法を工程順に示した断面図である。
Next, a conventional method of manufacturing a semiconductor device will be described with reference to the drawings. 10 to 13 are sectional views showing a conventional method of manufacturing a semiconductor device in the order of steps.

【0007】まず図10に示すように、半導体素子3の
電極パッド1上にワイヤーボンディング法(ボールボン
ディング法)を用いて、Auバンプ2(Au二段突起)
を形成する。この方法はAuワイヤー先端に形成したボ
ールをアルミ電極に熱圧接することにより、二段突起の
下段部を形成し(第1ボンド)、さらにワイヤーボンダ
ーのキャピラリを移動させることにより形成したAuワ
イヤーループをもって二段突起の上段部を形成する(第
2ボンド)。このような状態においては、Au二段突起
の高さは均一でなくかつ頭頂部の平坦性にも欠けている
ためにAu二段突起を加圧することにより高さの均一化
と頭頂部の平坦化、いわゆるレベリングを行なう。
First, as shown in FIG. 10, Au bumps 2 (Au two-step protrusions) are formed on the electrode pads 1 of the semiconductor element 3 by a wire bonding method (ball bonding method).
To form In this method, the ball formed at the tip of the Au wire is thermally pressed against the aluminum electrode to form the lower step of the two-step protrusion (first bond), and the capillary of the wire bonder is moved to form the Au wire loop. To form the upper step portion of the two-step protrusion (second bond). In such a state, the height of the Au two-step protrusion is not uniform and lacks the flatness of the crown. Therefore, by pressing the Au two-step protrusion, the height is made uniform and the crown is flat. The so-called leveling.

【0008】次に図11に示すように、半導体素子3上
のAuバンプ2に導電性接着剤6を供給する。導電性接
着剤6としては、上述と同様に信頼性、熱応力などを考
慮してたとえばバインダーとしてエポキシレジン、導体
フィラーとしてAg−Pd合金によりなる接着剤を用い
ている。
Next, as shown in FIG. 11, a conductive adhesive 6 is supplied to the Au bumps 2 on the semiconductor element 3. As the conductive adhesive 6, an adhesive made of, for example, an epoxy resin as a binder and an Ag-Pd alloy as a conductor filler is used in consideration of reliability, thermal stress, and the like as described above.

【0009】次に図12に示すように、半導体素子3の
表面を下向きにして実装する方法であるフリップチップ
方式によって、半導体素子3上の導電性接着剤6が供給
されたAuバンプ2と、表面の電極5が配線パターン8
により表面引き回しされ、ビア9によりその内部で引き
回されてその裏面の外部電極端子10に導通された半導
体キャリア4の前記電極5とを位置精度よく合わせて接
合した後、一定の温度にて熱硬化させる。
Next, as shown in FIG. 12, an Au bump 2 to which the conductive adhesive 6 is supplied on the semiconductor element 3 is provided by a flip chip method, which is a method of mounting the semiconductor element 3 with its surface facing downward. Surface electrode 5 is wiring pattern 8
The surface of the semiconductor carrier 4 is routed to the front surface of the semiconductor carrier 4 by the via 9 and is internally routed by the via 9 and is electrically connected to the external electrode terminal 10 on the back surface thereof. Let it harden.

【0010】そして最後に図13に示すように、エポキ
シ系の封止樹脂7を半導体素子3の周辺端部と、半導体
素子3と半導体キャリア4との間に形成された隙間に注
入し、一定の温度にて封止樹脂を硬化させ樹脂モールド
し、半導体装置を完成させていた。
Finally, as shown in FIG. 13, epoxy-based encapsulating resin 7 is injected into the peripheral end portion of the semiconductor element 3 and a gap formed between the semiconductor element 3 and the semiconductor carrier 4 to keep the same. The semiconductor device was completed by curing the encapsulating resin and resin-molding at the temperature of.

【0011】[0011]

【発明が解決しようとする課題】従来は複数のAuバン
プを半導体素子の電極パッド上に形成し、バンプ高さの
レベリングを行なった後に導電性接着剤を介して半導体
キャリアと接合していたが、導電性接着剤をその上段部
に形成したバンプの高さはレベリングしたにもかかわら
ず、ばらつきを有しており、高さばらつきのあるバンプ
で半導体素子と半導体キャリアとを接合した場合には、
接合不良が発生する恐れがあった。そして導電性接着剤
をその上段部に形成したバンプの高さの高さ精度の管理
が非常に困難であった。また半導体素子と半導体キャリ
アとは、導電性接着剤を用いた接合であるので、バンプ
に導電性接着剤を形成する工程が必要であった。さらに
バンプのレベリングが半導体素子上の電極パッド上で加
圧により行なうものであるので、加圧力によって半導体
素子自体が破損する危険があった。
Conventionally, a plurality of Au bumps are formed on the electrode pads of a semiconductor element, and the bump height is leveled, and then bonded to a semiconductor carrier via a conductive adhesive. , The height of the bumps formed with the conductive adhesive on the upper step has leveling, but has a variation, and when the semiconductor element and the semiconductor carrier are joined by bumps having a height variation, ,
There was a risk of defective bonding. Further, it is very difficult to control the height accuracy of the bumps having the conductive adhesive formed on the upper part thereof. In addition, since the semiconductor element and the semiconductor carrier are bonded using a conductive adhesive, a step of forming the conductive adhesive on the bump is required. Furthermore, since the bumps are leveled by pressure on the electrode pads on the semiconductor element, there is a risk that the semiconductor element itself may be damaged by the applied pressure.

【0012】本発明は、このような従来の不都合を解決
するものであって、フリップチップ実装における半導体
素子と半導体キャリアとのバンプによる接合に着目し、
バンプ高さ管理が容易であって、バンプによる半導体素
子と半導体キャリアとを接合の不良を解消できる半導体
装置およびその製造方法を提供することを課題とする。
The present invention solves such a conventional inconvenience, and pays attention to the bonding of the semiconductor element and the semiconductor carrier by the bump in the flip chip mounting,
It is an object of the present invention to provide a semiconductor device in which bump height management is easy and a bonding defect between a semiconductor element and a semiconductor carrier due to the bump can be eliminated, and a manufacturing method thereof.

【0013】[0013]

【課題を解決するための手段】従来の課題を解決するた
め本発明における半導体装置は、半導体キャリア上の電
極上に設けられたバンプ電極が半導体素子の電極パッド
と接合されたものであり、そのバンプ電極と半導体素子
の電極パッドとは低融点金属から構成され、金属同士の
溶融により接合されたものである。したがって、導電性
接着剤を介さずに半導体素子と半導体キャリアとを接合
したものである。
In order to solve the conventional problems, a semiconductor device according to the present invention is one in which a bump electrode provided on an electrode on a semiconductor carrier is bonded to an electrode pad of a semiconductor element. The bump electrode and the electrode pad of the semiconductor element are made of a low melting point metal and are joined by melting the metals. Therefore, the semiconductor element and the semiconductor carrier are bonded together without a conductive adhesive.

【0014】これにより、半導体素子と半導体キャリア
とがバンプ電極のみで接合されているので、半導体素子
と半導体キャリアとの隙間を充填している封止樹脂の熱
膨張係数と異なる熱膨張係数を有した導電性接着剤等が
キャリア/素子の隙間に存在せず、耐熱性、耐湿性等の
信頼性を向上させることができる。
Since the semiconductor element and the semiconductor carrier are bonded to each other only by the bump electrodes, the coefficient of thermal expansion differs from that of the sealing resin filling the gap between the semiconductor element and the semiconductor carrier. The conductive adhesive or the like does not exist in the gap between the carrier and the element, and reliability such as heat resistance and moisture resistance can be improved.

【0015】また本発明の半導体装置の製造方法は、フ
リップチップ実装工法を用いて半導体素子を回路構成さ
れた半導体キャリアに実装する方法において、半導体キ
ャリア側にバンプ電極を形成する工程を有し、その半導
体キャリア上のバンプ電極に対して半導体素子上の電極
パッドを接合するものである。
A method of manufacturing a semiconductor device of the present invention is a method of mounting a semiconductor element on a circuit-configured semiconductor carrier by using a flip-chip mounting method, including a step of forming bump electrodes on the semiconductor carrier side. The electrode pads on the semiconductor element are bonded to the bump electrodes on the semiconductor carrier.

【0016】この方法では、特に半導体キャリアと半導
体素子との接合工程において、半導体キャリア側の電極
上にバンプ電極を形成するものであり、そのバンプ電極
と半導体素子上の電極パッドとの金属同士の固相接合を
するもので、導電性接着剤などの接着手段を用いずに半
導体キャリアと半導体素子とを接合させることができ
る。さらに溶融させた金属同士の押圧による接合である
ので、バンプ電極のレベリングのばらつきによるバンプ
電極の高さのばらつきを緩和して接合することができ、
接合不良を低減させることができる。
In this method, a bump electrode is formed on the electrode on the semiconductor carrier side, particularly in the step of joining the semiconductor carrier and the semiconductor element, and the metal between the bump electrode and the electrode pad on the semiconductor element is changed. Since solid-phase joining is performed, the semiconductor carrier and the semiconductor element can be joined without using an adhesive means such as a conductive adhesive. Further, since the joining is performed by pressing the melted metals, it is possible to alleviate the variation in the height of the bump electrodes due to the variation in the leveling of the bump electrodes and perform the joining.
Bonding defects can be reduced.

【0017】[0017]

【発明の実施の形態】以下、本発明の半導体装置の実施
の形態について、図面を参照しながら説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device of the present invention will be described below with reference to the drawings.

【0018】図1は本実施の形態の平面図、図2はその
底面図、図3は図1のA−A1線に沿った断面図であ
る。
FIG. 1 is a plan view of this embodiment, FIG. 2 is a bottom view thereof, and FIG. 3 is a sectional view taken along the line AA1 of FIG.

【0019】図1,図2および図3に示すように、半導
体素子11上の電極パッド12と、セラミックを絶縁基
体とした多層回路基板である半導体キャリア13上の電
極14とが接合されている。その接合は、半導体キャリ
ア13上の電極14上に形成された低融点金属からなる
バンプ電極15により接合されているものであり、本実
施の形態では、バンプ電極15と電極パッド12とは、
低融点金属として金(Au)で形成されたものであり、
金−金で固相接続されている。そして接合された半導体
素子11と半導体キャリア13との間の隙間と、半導体
素子11の端部はエポキシ系封止樹脂16で充填被覆さ
れている。また半導体素子11の端部と半導体キャリア
13にかかる部分は、封止樹脂16のフィレット部であ
り、半導体キャリア13上面の配線パターン17、ビア
18を被覆し、腐食を防止している。なお、図2におい
ては、フィレット部に覆われている配線パターン17お
よびビア18の表示は、便宜上、実線で示している。
As shown in FIGS. 1, 2 and 3, an electrode pad 12 on a semiconductor element 11 and an electrode 14 on a semiconductor carrier 13 which is a multilayer circuit board using ceramics as an insulating base are joined. . The bonding is performed by the bump electrode 15 made of a low melting point metal formed on the electrode 14 on the semiconductor carrier 13. In the present embodiment, the bump electrode 15 and the electrode pad 12 are
It is formed of gold (Au) as a low melting point metal,
It is solid-phase connected with gold-gold. The gap between the bonded semiconductor element 11 and the semiconductor carrier 13 and the end of the semiconductor element 11 are filled and covered with an epoxy-based sealing resin 16. Further, the end portion of the semiconductor element 11 and the portion that is in contact with the semiconductor carrier 13 are the fillet portion of the sealing resin 16, and cover the wiring pattern 17 and the via 18 on the upper surface of the semiconductor carrier 13 to prevent corrosion. Note that, in FIG. 2, the wiring pattern 17 and the via 18 covered by the fillet portion are shown by solid lines for convenience.

【0020】なお、バンプ電極15を金(Au)として
いるが、Au(金)以外にPt(白金)、Ag(銀)、
Al(アルミニウム)、Sn/Zn半田などでもよい。
Although the bump electrode 15 is made of gold (Au), other than Au (gold), Pt (platinum), Ag (silver),
Al (aluminum), Sn / Zn solder or the like may be used.

【0021】なお、本実施の形態では、封止樹脂7はエ
ポキシ系樹脂にフィラーとして高熱伝導セラミックであ
る窒化アルミニウム(AlN)、もしくは炭化珪素(S
iC)を添加した樹脂を用いている。多層回路基板であ
る前記半導体キャリア4の底面には、図2に示すよう
に、メタライズ金属層としてAg−Pdよりなる円形の
外部電極端子19が一定の間隔で格子状に形成されてい
る。この外部電極端子19は、半導体キャリア13上の
電極14の配列が配線パターン17とビア18により半
導体キャリア13内部で引き回され、底面で格子状に配
列されているものである。外部電極端子19の配列は格
子状以外にも、千鳥配列等目的に応じて自由に選ぶこと
ができる。またAg−Pd以外にもCu、Auをメタラ
イズ金属層として用いてもよい。またさらに外部電極材
料の表面酸化防止を目的としてAuめっきを行なう。
In this embodiment, the encapsulating resin 7 is a high heat conductive ceramic such as aluminum nitride (AlN) or silicon carbide (S) as a filler in an epoxy resin.
iC) is added to the resin. As shown in FIG. 2, circular external electrode terminals 19 made of Ag-Pd as metallized metal layers are formed in a grid pattern at regular intervals on the bottom surface of the semiconductor carrier 4 which is a multilayer circuit board. The external electrode terminals 19 are arranged such that the electrodes 14 on the semiconductor carrier 13 are arranged inside the semiconductor carrier 13 by the wiring pattern 17 and the vias 18, and are arranged in a grid pattern on the bottom surface. The arrangement of the external electrode terminals 19 can be freely selected according to the purpose such as a zigzag arrangement other than the grid shape. In addition to Ag-Pd, Cu or Au may be used as the metallized metal layer. Further, Au plating is performed for the purpose of preventing surface oxidation of the external electrode material.

【0022】ここで、本実施の形態の特徴とする点は、
半導体キャリア13側の電極14上に低融点金属からな
るバンプ電極15を形成して、バンプ電極15と半導体
素子11上の電極パッド12との金属接合により半導体
素子11と半導体キャリア13とを接合している点であ
る。したがって、導電性接着剤等の接着手段を用いずに
接合しているものであり、耐熱性、耐湿性などの信頼性
を高めることができる。また半導体キャリア13側の電
極14上にバンプ電極15を形成し、半導体素子11上
の電極パッド12と押圧により金属接合させているの
で、バンプ電極15のレベリングのばらつきの管理が容
易であり、接合不良を低減させることができる。さらに
バンプ電極15は半導体キャリア13側に形成し、レベ
リングしたものであるので、半導体素子11上に形成す
るものではなく、リベリングの加圧による半導体素子1
1の欠損もない。
Here, the characteristic point of this embodiment is that
A bump electrode 15 made of a low melting point metal is formed on the electrode 14 on the semiconductor carrier 13 side, and the bump electrode 15 and the electrode pad 12 on the semiconductor element 11 are metal-bonded to bond the semiconductor element 11 and the semiconductor carrier 13 to each other. That is the point. Therefore, they are joined without using an adhesive means such as a conductive adhesive, and reliability such as heat resistance and moisture resistance can be improved. Further, since the bump electrode 15 is formed on the electrode 14 on the semiconductor carrier 13 side and is metal-bonded to the electrode pad 12 on the semiconductor element 11 by pressing, it is easy to manage the variation in the leveling of the bump electrode 15 and to bond it. Defects can be reduced. Further, since the bump electrode 15 is formed on the semiconductor carrier 13 side and leveled, the bump electrode 15 is not formed on the semiconductor element 11, but is applied to the semiconductor element 1 by the pressure of the leveling.
There is no loss of 1.

【0023】半導体装置の信頼性について、本実施の形
態は、半導体素子11と半導体キャリア13とが接合さ
れ、その隙間を封止樹脂16で充填したものであり、隙
間に充填された封止樹脂16の熱膨張を考慮した場合、
半導体素子11と半導体キャリア13との間には、極力
他の材料が存在しない方が好適である。これは、封止樹
脂16の熱膨張係数と異なる熱膨張係数を有した導電性
接着剤等が封止樹脂16とともに隙間に存在すると、耐
熱性、耐湿性等が劣化し、信頼性上好ましくないためで
ある。
Regarding the reliability of the semiconductor device, in the present embodiment, the semiconductor element 11 and the semiconductor carrier 13 are joined and the gap is filled with the sealing resin 16, and the sealing resin filled in the gap. Considering the thermal expansion of 16,
It is preferable that no other material be present between the semiconductor element 11 and the semiconductor carrier 13 as much as possible. This is not preferable in terms of reliability because heat resistance, moisture resistance, etc. deteriorate when a conductive adhesive or the like having a thermal expansion coefficient different from that of the sealing resin 16 exists in the gap together with the sealing resin 16. This is because.

【0024】次に半導体装置の製造方法の実施の形態に
ついて、図面を参照しながら説明する。図4〜図6は本
実施の形態を説明するための工程図である。
Next, an embodiment of a method of manufacturing a semiconductor device will be described with reference to the drawings. 4 to 6 are process drawings for explaining the present embodiment.

【0025】まず図4に示すように、上面に複数の電極
14と、その電極14を引き回す配線パターン17と、
底面に配列され、電極14とビア18により導通された
外部電極端子19とを有した半導体キャリア13の電極
14上にバンプ電極15を形成する。このバンプ電極1
5の形成は、ワイヤーボンディング法(ボールボンディ
ング法)を用いて、Auワイヤー先端に形成したボール
を電極14に熱圧接することにより、二段突起の下段部
を形成し(第1ボンド)、さらにワイヤーボンダーのキ
ャピラリを移動させることにより形成したAuワイヤー
ループをもって二段突起の上段部を形成(第2ボンド)
する。またこの状態においては、Au二段突起の高さは
均一でなくかつ頭頂部の平坦性にも欠けているためにA
u二段突起を加圧することにより高さの均一化と頭頂部
の平坦化、いわゆるレベリングを行なう。
First, as shown in FIG. 4, a plurality of electrodes 14 on the upper surface, a wiring pattern 17 for leading the electrodes 14,
The bump electrode 15 is formed on the electrode 14 of the semiconductor carrier 13 which is arranged on the bottom surface and has the electrode 14 and the external electrode terminal 19 electrically connected by the via 18. This bump electrode 1
5 is formed by hot pressing the ball formed at the tip of the Au wire to the electrode 14 using the wire bonding method (ball bonding method) to form the lower step portion of the two-step protrusion (first bond). The upper step part of the two-step protrusion is formed by the Au wire loop formed by moving the capillary of the wire bonder (second bond).
I do. Also, in this state, the height of the Au two-step protrusion is not uniform and the flatness of the crown is also lacking.
By pressing the u two-stage protrusion, the height is made uniform and the crown is flattened, that is, so-called leveling is performed.

【0026】次に図5に示すように、半導体素子11の
表面を下にして実装する方法であるフリップチップ方式
によって、半導体素子11上の電極パッド12と、半導
体キャリア13上の電極14とを位置精度よく合わせて
接合する。この接合は、本実施形態では、電極パッド1
2を金(Au)で形成し、バンプ電極15も金で形成し
ているので、金−金の固相接合により行なうもので、ス
パークなどの部分加熱手段により金を溶融し、押圧して
接合する手段の他、半導体素子11、半導体キャリア1
3に超音波を印加して電極パッド12の金(Au)、バ
ンプ電極15の金を溶融させ、押圧する手段により行な
う。
Next, as shown in FIG. 5, the electrode pads 12 on the semiconductor element 11 and the electrodes 14 on the semiconductor carrier 13 are formed by a flip chip method, which is a method of mounting the semiconductor element 11 with the surface thereof facing down. Align and join with good positional accuracy. In this embodiment, this bonding is performed by the electrode pad 1
2 is formed of gold (Au), and the bump electrode 15 is also formed of gold, so solid-state bonding of gold-gold is performed, and gold is melted by partial heating means such as spark and pressed to bond. In addition to the means, a semiconductor element 11 and a semiconductor carrier 1
Ultrasonic waves are applied to 3 to melt the gold (Au) of the electrode pad 12 and the gold of the bump electrode 15 and press it.

【0027】そして最後に図6に示すように、エポキシ
系封止樹脂16を半導体素子11の周辺端部と、半導体
素子11と半導体キャリア13との間に形成された隙間
に注入し、一定の温度にて封止樹脂を硬化させ樹脂モー
ルドし、半導体装置を完成させる。
Finally, as shown in FIG. 6, epoxy-based encapsulating resin 16 is injected into the peripheral end portion of the semiconductor element 11 and a gap formed between the semiconductor element 11 and the semiconductor carrier 13 to keep a constant amount. The sealing resin is cured at a temperature and resin-molded to complete the semiconductor device.

【0028】以上、本実施の形態で示すように、半導体
キャリア13側の電極14上にバンプ電極15を形成
し、半導体素子11上の電極パッド12と金属の固相接
合をしているので、導電性接着剤などの接着手段を用い
ずに半導体キャリア13と半導体素子11とを接合させ
ることができる。また溶融させた金属同士の押圧による
接合であるので、レベリングのばらつきによるバンプ電
極15の高さのばらつきを緩和して接合することがで
き、接合不良を低減させることができる。さらにバンプ
電極15は半導体キャリア13側に形成して、レベリン
グしたものであるので、半導体素子11上に形成してそ
の上でレベリングするものではなく、リベリングの加圧
による半導体素子11の欠損もない。
As described above in the present embodiment, since the bump electrode 15 is formed on the electrode 14 on the semiconductor carrier 13 side and the electrode pad 12 on the semiconductor element 11 is solid-phase bonded to the metal, The semiconductor carrier 13 and the semiconductor element 11 can be joined without using an adhesive means such as a conductive adhesive. Moreover, since the joining is performed by pressing the molten metals together, the variation in the height of the bump electrode 15 due to the variation in the leveling can be alleviated and the joining can be reduced. Further, since the bump electrode 15 is formed on the semiconductor carrier 13 side and leveled, it is not formed on the semiconductor element 11 and then leveled thereon, and there is no loss of the semiconductor element 11 due to the pressure of the leveling. .

【0029】なお、本実施の形態では、バンプ電極15
と電極パッド12を金により形成しているが、金以外に
Pt(白金)、Ag(銀)、Al(アルミニウム)、C
u(銅)などの固相接合可能な材料であればよい。
In this embodiment, the bump electrode 15
And the electrode pad 12 are made of gold, but in addition to gold, Pt (platinum), Ag (silver), Al (aluminum), C
Any material capable of solid phase bonding such as u (copper) may be used.

【0030】次に参考として、本実施の形態で示した半
導体キャリア13の作製方法について説明する。まずセ
ラミック粉末をガラス粉末と溶剤と共に混合ミルに投入
し回転混合粉砕を行なう。さらに有機バインダーを添加
しさらに混合する。このセラミック粉末は通常アルミナ
を主体とするが特に熱伝導性を向上させるために窒化ア
ルミニウム(AlN)、炭化珪素(SiC)等の粉末も
添加する。十分混合を行なった後、得られる泥しょう、
いわゆるスラリーはグリーンシート成型のために搬送シ
ート上に任意の厚みで塗布される。厚みの調整はドクタ
ーブレード法等を用いる。搬送シート上のスラリーは赤
外線および熱風を用いて溶剤を乾燥することにより弾力
性に富み導電ペースト印刷時のペースト溶剤の浸透性に
すぐれたグリーンシートを得る。このグリーンシートに
対して位置合わせ手法として配線ルール200μm以上
の場合には、グリーンシートに直接ガイド穴を設け、2
00μm未満の場合には、ガイド穴を有した保持枠に張
り付ける。次にグリーンシートの表裏の電気的導通が必
要な部分に機械的加工法にて穴を設ける。この穴に印刷
法にてCu粉末を主成分とした導電性ペーストを充填す
る。次にグリーンシート表面に必要な回路を印刷した後
乾燥を行い、適当な荷重にて印刷された回路をグリーン
シート中に埋没させる。この目的は回路が印刷されたグ
リーンシート表面を平坦にすることにより、次の工程で
ある積層工程における積層不良、いわゆるデラミネーシ
ョンを防止するためである。積層工程においては、グリ
ーンシートに設けられたガイド穴もしくは保持枠のガイ
ド穴により精度よく積層されたグリーンシートを加圧す
ることにより強固に接着する。こうして完成したセラミ
ックキャリアの背面に形成された格子状電極にSn−P
bの共晶はんだクリームを塗布する。そして整列治具を
用いて高融点はんだボールを塗布されたはんだクリーム
に供給した後、リフロー炉等を用いて加熱溶融すること
によりはんだ突起バンプである外部電極端子を形成し、
半導体キャリア13を形成する。
Next, as a reference, a method of manufacturing the semiconductor carrier 13 shown in this embodiment will be described. First, ceramic powder is put into a mixing mill together with glass powder and a solvent, and rotary mixing and pulverization are performed. Further, an organic binder is added and further mixed. This ceramic powder is usually composed mainly of alumina, but powders of aluminum nitride (AlN), silicon carbide (SiC), etc. are also added to improve the thermal conductivity. The mud obtained after thorough mixing,
The so-called slurry is applied to the conveying sheet with an arbitrary thickness for forming the green sheet. A doctor blade method or the like is used to adjust the thickness. The slurry on the carrier sheet is dried by using infrared rays and hot air to dry the solvent, thereby obtaining a green sheet having excellent elasticity and excellent permeability of the paste solvent at the time of printing the conductive paste. When the wiring rule is 200 μm or more as an alignment method for this green sheet, a guide hole is provided directly in the green sheet.
If it is less than 00 μm, it is attached to a holding frame having guide holes. Next, holes are formed by mechanical processing in the front and back portions of the green sheet where electrical conduction is required. These holes are filled with a conductive paste mainly containing Cu powder by a printing method. Next, after printing a necessary circuit on the surface of the green sheet and drying, the printed circuit is embedded in the green sheet with an appropriate load. The purpose of this is to flatten the surface of the green sheet on which the circuit is printed, thereby preventing lamination failure in the next lamination step, so-called delamination. In the laminating step, the laminated green sheets are accurately pressed by the guide holes provided in the green sheet or the guide holes of the holding frame to firmly bond the green sheets. Sn-P is formed on the grid-like electrode formed on the back surface of the ceramic carrier thus completed.
Apply b eutectic solder cream. Then, after supplying the high melting point solder balls to the applied solder cream using an alignment jig, the external electrode terminals that are solder bump bumps are formed by heating and melting using a reflow furnace or the like,
The semiconductor carrier 13 is formed.

【0031】本発明の半導体装置の実施の形態は、半導
体素子11と半導体キャリア13との接合を導電性接着
剤等の接着手段を用いず、半導体キャリア13上のバン
プ電極15の金属材料と、半導体素子11上の電極パッ
ド12の金属材料との金属接合で行なったものであり、
従来のように封止樹脂16の熱膨張係数と異なる熱膨張
係数を有した導電性接着剤等がキャリア/素子の隙間に
存在せず、耐熱性、耐湿性等の信頼性を向上させること
ができる。
According to the embodiment of the semiconductor device of the present invention, the semiconductor element 11 and the semiconductor carrier 13 are joined to each other by using a metal material of the bump electrode 15 on the semiconductor carrier 13 without using an adhesive means such as a conductive adhesive. This is performed by metal bonding with the metal material of the electrode pad 12 on the semiconductor element 11,
A conductive adhesive or the like having a thermal expansion coefficient different from the thermal expansion coefficient of the sealing resin 16 as in the prior art does not exist in the gap between the carrier / element, and reliability such as heat resistance and moisture resistance can be improved. it can.

【0032】また本発明の半導体装置の製造方法の実施
の形態は、特に半導体キャリア13と半導体素子11と
の接合工程において、半導体キャリア13側の電極14
上にバンプ電極15を形成するものであり、そのバンプ
電極15と半導体素子11上の電極パッド12との金属
同士の固相接合をするもので、導電性接着剤などの接着
手段を用いずに半導体キャリア13と半導体素子11と
を接合させることができる。さらに溶融させた金属同士
の押圧による接合であるので、バンプ電極15のレベリ
ングのばらつきによるバンプ電極15の高さのばらつき
を緩和して接合することができ、接合不良を低減させる
ことができる。
In the embodiment of the method for manufacturing a semiconductor device of the present invention, the electrode 14 on the semiconductor carrier 13 side is particularly used in the step of joining the semiconductor carrier 13 and the semiconductor element 11.
The bump electrode 15 is formed on the bump electrode 15, and the bump electrode 15 and the electrode pad 12 on the semiconductor element 11 are solid-phase bonded to each other without using a bonding means such as a conductive adhesive. The semiconductor carrier 13 and the semiconductor element 11 can be joined. Further, since the joining is performed by pressing the melted metals, the variation in the height of the bump electrode 15 due to the variation in the leveling of the bump electrode 15 can be mitigated and the joining can be reduced.

【0033】[0033]

【発明の効果】本発明にかかる半導体装置は、半導体素
子と半導体キャリアとの接合を従来のように導電性接着
剤等の接着手段を用いず、半導体キャリア上のバンプ電
極の金属材料と、半導体素子上の電極の金属材料との金
属接合で行なったものであり、導電性接着剤等がキャリ
アと素子との隙間に存在せず、耐熱性、耐湿性等の信頼
性を向上させることができる。
The semiconductor device according to the present invention does not use a bonding means such as a conductive adhesive to bond a semiconductor element and a semiconductor carrier, unlike the conventional case, and uses a metal material for a bump electrode on the semiconductor carrier and a semiconductor. It is performed by metal bonding with the metal material of the electrode on the element, and the conductive adhesive or the like does not exist in the gap between the carrier and the element, and reliability such as heat resistance and moisture resistance can be improved. .

【0034】また本発明の半導体装置の製造方法は、特
に半導体キャリアと半導体素子との接合工程において、
半導体キャリア側の電極上にバンプ電極を形成するもの
であり、そのバンプ電極と半導体素子上の電極パッドと
を押圧によって金属同士の固相接合をするもので、導電
性接着剤などの接着手段を用いずに半導体キャリアと半
導体素子とを接合させることができる。さらに溶融させ
た金属同士の押圧による接合であるので、バンプ電極の
レベリングのばらつきによるバンプ電極の高さのばらつ
きを緩和して接合することができ、接合不良を低減させ
ることができる。
Further, in the method of manufacturing a semiconductor device of the present invention, particularly in the step of joining the semiconductor carrier and the semiconductor element,
A bump electrode is formed on an electrode on the semiconductor carrier side, and the bump electrode and the electrode pad on the semiconductor element are pressed to perform solid-phase bonding between metals, and an adhesive means such as a conductive adhesive is used. The semiconductor carrier and the semiconductor element can be bonded without using them. Further, since the joining is performed by pressing the melted metals together, it is possible to alleviate the variation in the height of the bump electrode due to the variation in the leveling of the bump electrode, and it is possible to reduce the defective joining.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の実施の形態の平面図FIG. 1 is a plan view of an embodiment of a semiconductor device of the present invention.

【図2】本発明の半導体装置の実施の形態の底面図FIG. 2 is a bottom view of the embodiment of the semiconductor device of the present invention.

【図3】本発明の半導体装置の実施の形態の断面図FIG. 3 is a sectional view of an embodiment of a semiconductor device of the present invention.

【図4】本発明の半導体装置の製造方法の実施の形態を
説明するための工程断面図
FIG. 4 is a process sectional view for explaining the embodiment of the method for manufacturing the semiconductor device of the present invention.

【図5】本発明の半導体装置の製造方法の実施の形態を
説明するための工程断面図
FIG. 5 is a process sectional view for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention.

【図6】本発明の半導体装置の製造方法の実施の形態を
説明するための工程断面図
FIG. 6 is a process sectional view for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention.

【図7】従来の半導体装置の平面図FIG. 7 is a plan view of a conventional semiconductor device.

【図8】従来の半導体装置の底面図FIG. 8 is a bottom view of a conventional semiconductor device.

【図9】従来の半導体装置の断面図FIG. 9 is a sectional view of a conventional semiconductor device.

【図10】従来の半導体装置の製造方法を説明するため
の工程断面図
FIG. 10 is a process cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

【図11】従来の半導体装置の製造方法を説明するため
の工程断面図
FIG. 11 is a process cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

【図12】従来の半導体装置の製造方法を説明するため
の工程断面図
FIG. 12 is a process sectional view for explaining a conventional method for manufacturing a semiconductor device.

【図13】従来の半導体装置の製造方法を説明するため
の工程断面図
FIG. 13 is a process sectional view for explaining the conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 電極パッド 2 Auバンプ 3 半導体素子 4 半導体キャリア 5 電極 6 導電性接着剤 7 封止樹脂 8 配線パターン 9 ビア 10 外部電極端子 11 半導体素子 12 電極パッド 13 半導体キャリア 14 電極 15 バンプ電極 16 封止樹脂 17 配線パターン 18 ビア 19 外部電極端子 1 Electrode Pad 2 Au Bump 3 Semiconductor Element 4 Semiconductor Carrier 5 Electrode 6 Conductive Adhesive 7 Sealing Resin 8 Wiring Pattern 9 Via 10 External Electrode Terminal 11 Semiconductor Element 12 Electrode Pad 13 Semiconductor Carrier 14 Electrode 15 Bump Electrode 16 Sealing Resin 17 Wiring pattern 18 Via 19 External electrode terminal

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 上面に複数の電極と、前記電極を引き回
す配線パターンと、底面に配列され、前記電極と導通し
た外部電極端子とを有した半導体キャリアと、前記半導
体キャリア上面に接合された半導体素子と、前記半導体
キャリア上の電極上に設けられ、半導体キャリアと前記
半導体素子上の電極パッドとを接合した複数のバンプ電
極と、前記半導体素子と前記半導体キャリアとの間隔と
前記半導体素子周辺端部とを充填被覆している樹脂とよ
りなる半導体装置。
1. A semiconductor carrier having a plurality of electrodes on an upper surface thereof, a wiring pattern for routing the electrodes, and external electrode terminals arranged on the bottom surface and electrically connected to the electrodes, and a semiconductor bonded to the upper surface of the semiconductor carrier. An element, a plurality of bump electrodes provided on an electrode on the semiconductor carrier and joining the semiconductor carrier and an electrode pad on the semiconductor element, a gap between the semiconductor element and the semiconductor carrier, and a peripheral edge of the semiconductor element A semiconductor device made of a resin filling and covering a portion.
【請求項2】 上面に複数の電極と、前記電極を引き回
す配線パターンと、底面に配列され、前記電極と導通し
た外部電極端子とを有した半導体キャリアと、前記半導
体キャリア上面に接合された半導体素子と、前記半導体
キャリア上の電極上に設けられ、半導体キャリアと前記
半導体素子上の低融点金属からなる電極パッドとを金属
接合した低融点金属からなる複数のバンプ電極と、前記
半導体素子と前記半導体キャリアとの間隔と前記半導体
素子周辺端部とを充填被覆している樹脂とよりなる半導
体装置。
2. A semiconductor carrier having a plurality of electrodes on an upper surface thereof, a wiring pattern for routing the electrodes, and external electrode terminals arranged on the bottom surface and electrically connected to the electrodes, and a semiconductor bonded to the upper surface of the semiconductor carrier. An element, a plurality of bump electrodes made of a low melting point metal, which are provided on the electrodes on the semiconductor carrier, and are metal-bonded to the semiconductor carrier and an electrode pad made of a low melting point metal on the semiconductor element; A semiconductor device comprising a resin filling and covering a space between the semiconductor carrier and the peripheral edge of the semiconductor element.
【請求項3】 第1面にバンプ用電極と配線パターン
と、第2面に前記配線パターンとその内部で導通された
外部電極端子とを有した半導体キャリアに対して、前記
バンプ用電極上にバンプ電極を形成する工程と、前記半
導体キャリア上のバンプ電極に対して半導体素子上の電
極パッドを接合する工程と、前記半導体素子と半導体キ
ャリアとの隙間に封止樹脂を注入し、硬化させ樹脂封止
を行なう工程とを有することを特徴とする半導体装置の
製造方法。
3. A semiconductor carrier having a bump electrode and a wiring pattern on a first surface, and the wiring pattern and an external electrode terminal electrically connected to the inside on the second surface, with respect to the bump electrode. A step of forming a bump electrode, a step of joining an electrode pad on a semiconductor element to a bump electrode on the semiconductor carrier, a sealing resin is injected into a gap between the semiconductor element and the semiconductor carrier, and the resin is cured. And a step of performing encapsulation.
【請求項4】 第1面にバンプ用電極と配線パターン
と、第2面に前記配線パターンとその内部で導通された
外部電極端子とを有した半導体キャリアに対して、前記
バンプ用電極上に低融点金属からなるバンプ電極を形成
する工程と、前記半導体キャリア上のバンプ電極に対し
て半導体素子上の低融点金属からなる電極パッドを当接
し、前記バンプ電極と電極パッドとを溶融により接合す
る工程と、前記半導体素子と半導体キャリアとの隙間に
封止樹脂を注入し、硬化させ樹脂封止を行なう工程とを
有することを特徴とする半導体装置の製造方法。
4. A semiconductor carrier having a bump electrode and a wiring pattern on a first surface, and the wiring pattern and an external electrode terminal electrically connected to the inside on the second surface, with respect to the bump electrode on the semiconductor carrier. A step of forming a bump electrode made of a low melting point metal, and an electrode pad made of a low melting point metal on a semiconductor element is brought into contact with the bump electrode on the semiconductor carrier, and the bump electrode and the electrode pad are joined by melting. A method for manufacturing a semiconductor device, comprising: a step; and a step of injecting a sealing resin into a gap between the semiconductor element and the semiconductor carrier, curing the resin, and sealing the resin.
【請求項5】 第1面にバンプ用電極と配線パターン
と、第2面に前記配線パターンとその内部で導通された
外部電極端子とを有した半導体キャリアの前記バンプ用
電極上に低融点金属からなるバンプ電極を形成する工程
と、前記半導体キャリア上のバンプ電極を加圧によりレ
ベリングする工程と、前記半導体キャリア上のバンプ電
極に対して半導体素子上の低融点金属からなる電極パッ
ドを当接し、前記バンプ電極と電極パッドとを溶融によ
り接合する工程と、前記半導体素子と半導体キャリアと
の隙間に封止樹脂を注入し、硬化させ樹脂封止を行なう
工程とを有し、バンプレベリング時の加圧の影響を考慮
して、バンプ電極を半導体キャリア側に形成するもので
あることを特徴とする半導体装置の製造方法。
5. A low melting point metal on the bump electrode of a semiconductor carrier having a bump electrode and a wiring pattern on a first surface and the wiring pattern and an external electrode terminal electrically connected therein on a second surface. A bump electrode on the semiconductor carrier, and a step of applying pressure to the bump electrode on the semiconductor carrier, and contacting the bump electrode on the semiconductor carrier with an electrode pad made of a low melting point metal on a semiconductor element. , A step of joining the bump electrode and the electrode pad by melting, and a step of injecting a sealing resin into a gap between the semiconductor element and the semiconductor carrier and curing the resin to perform resin sealing. A method of manufacturing a semiconductor device, wherein a bump electrode is formed on the semiconductor carrier side in consideration of the influence of pressure.
JP34023195A 1995-12-27 1995-12-27 Semiconductor device and its manufacturing method Pending JPH09181119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34023195A JPH09181119A (en) 1995-12-27 1995-12-27 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34023195A JPH09181119A (en) 1995-12-27 1995-12-27 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH09181119A true JPH09181119A (en) 1997-07-11

Family

ID=18334960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34023195A Pending JPH09181119A (en) 1995-12-27 1995-12-27 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPH09181119A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003077307A1 (en) * 2002-03-11 2003-09-18 Toyo Kohan Co., Ltd. Electronic circuit device and porduction method therefor
US7390692B2 (en) 2002-10-30 2008-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003077307A1 (en) * 2002-03-11 2003-09-18 Toyo Kohan Co., Ltd. Electronic circuit device and porduction method therefor
US7390692B2 (en) 2002-10-30 2008-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same

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