JPH0917954A - Semiconductor integrated device - Google Patents

Abstract

(57) [Summary] [Structure] A static electricity protection circuit for semiconductor integrated devices. A pad 1 electrically connected to an external terminal; a resistance element 4 electrically connected to the pad 1 by a metal wiring and formed of an impurity diffusion layer; and an impurity diffusion layer having the same polarity as the resistance element 4. The well contact 9 is formed. Between the resistance element 4 and the well contact 9, an impurity diffusion layer 7 having the same pole as the substrate and a higher concentration than that of the substrate is arranged. Moreover, the junction breakdown voltage of the element to which static electricity is applied is increased. [Effect] Since the current amplification factor of the parasitic bipolar transistor which is turned on by the application of static electricity can be reduced, it is possible to prevent the junction breakdown due to the current flowing by the parasitic bipolar transistor. Further, since the junction breakdown voltage of the element to which static electricity is applied is increased, the junction breakdown voltage can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit for a semiconductor integrated device.

[0002]

2. Description of the Related Art An example of the layout of a conventional electrostatic protection circuit will be described with reference to FIG. In FIG. 5, 1 is a pad for electrical connection with an external terminal, 2 is an aluminum wiring, 3 is a contact for electrically connecting the aluminum wiring with an impurity diffusion layer or an ion implantation layer, and 4 is an impurity diffusion layer or an ion implantation layer. The formed resistance element, 6 is an aluminum wiring, 7 is an impurity diffusion layer or an ion implantation layer of the same polarity as the substrate, and a sub contact for applying a potential to the substrate,
Reference numeral 8 is a well region, 9 is a well contact for applying a potential to the well with an impurity diffusion layer or an ion implantation layer, 1
Reference numeral 0 denotes an impurity diffusion layer or an ion implantation layer having a different polarity from that of the well 8, and 11 denotes an impurity diffusion layer or an ion implantation layer having a different polarity from the substrate. Reference numeral 12 is a contact for the well contact 9 to be electrically connected to the aluminum wiring of the positive power source. The aluminum wiring of the positive power source is not shown in order to make the drawing easier to see. Reference numeral 13 is a contact for the sub-contact 7 to be electrically connected to the aluminum wiring of the ground power supply. Aluminum wiring of ground power supply is not shown in order to make the drawing easier to see. The region other than the above-mentioned impurity diffusion layer or ion implantation layer is the substrate region. Here, in the present invention, the impurity region formed by the impurity diffusion layer or the ion implantation layer has the same configuration in the case of the impurity diffusion layer or the ion implantation layer,
Since the effect is the same, the impurity diffusion layer will be described in the following description for simplification of description.

A resistor 4 is connected from the pad 1 to the aluminum wiring 2.
Are connected in series, and further connected to two diodes, a diode formed by the impurity diffusion layer 10 and the well contact 9 by the resistor 4 and the aluminum wiring 6, and a diode formed by the impurity diffusion layer 11 and the sub contact 7. There is. The diode formed by the impurity diffusion layer 10 and the well contact 9, and the impurity diffusion layer 1
The diode formed by 1 and the sub-contact 7 has opposite polarities when viewed from the pad. Here, a case where static electricity is applied to the pad 1 will be described. When a positive static electricity is applied to the pad 1, the static energy is attenuated by the resistor 4, and then the static electricity is absorbed by the positive power source by the diode formed by the impurity diffusion layer 10 and the well contact 9. On the other hand, if negative static electricity is applied to the pad 1, the impurity diffusion layer 1
Static electricity is absorbed by the ground power source by the diode formed by 1 and the sub contact 7. As described above, the semiconductor integrated device is prevented from being broken by the static electricity applied to the pad.

[0004]

However, the conventional technique has the following problems. Similarly, it demonstrates using FIG. In FIG. 5, the substrate of the semiconductor integrated device is a P type. Then, the resistance element 4 is an N-type high-concentration impurity diffusion layer, 7 is a sub-contact of the P-type high-concentration impurity diffusion layer, 8 is a well and is an N-type low-concentration impurity diffusion layer, and 9 is N.
Type well high-concentration impurity diffusion layer well contact, 10 is P
The high-concentration impurity diffusion layer 11 is formed of an N-type high-concentration impurity diffusion layer.

Here, it is assumed that the negative static electricity is applied to the pad 1 with respect to the positive power source.

Then, the NPN type bipolar transistor parasitically formed by the well contact 9 of the N type high concentration impurity diffusion layer, the P type substrate and the resistance element 4 of the N type high concentration impurity diffusion layer is turned on. . Then, when the applied voltage of the static electricity is gradually increased and the application is repeated, there is a problem that the junction between the well contact 9 of the N-type high-concentration impurity diffusion layer and the P-type substrate eventually breaks. there were.

If positive static electricity is applied to the pad 1 with respect to the ground power source, the reverse of the diode formed by the P-type substrate and the resistance element 4 formed by the N-type high-concentration impurity diffusion layer. The voltage is applied in the direction. Then, when the applied voltage of the static electricity is gradually increased and the application is repeated, finally, the junction between the resistance element 4 of the N-type high-concentration impurity diffusion layer and the P-type substrate near the pad 1 causes a junction breakdown. There was a problem that it would end up.

[0008]

A semiconductor integrated device according to the present invention comprises (Means 1) at least a pad electrically connected to an external terminal, a pad electrically connected to the pad by a metal wiring, and an impurity diffusion layer. A resistance element formed and a well contact formed of an impurity diffusion layer of the same polarity as the resistance element, between the resistance element and the well contact,
The feature is that an impurity diffusion layer having the same polarity as the substrate and a higher concentration than the substrate is arranged.

(Means 2) Further, the resistance element formed of the impurity diffusion layer is arranged such that a long side thereof is parallel to a side direction of a chip of the adjacent semiconductor integrated device. To do.

(Means 3) Further, it comprises at least a pad electrically connected to an external terminal and a resistance element electrically connected to the pad by a metal wiring and formed of an impurity diffusion layer, wherein the resistance element is The resistive element is formed of a high-concentration impurity diffusion layer having a different polarity from the substrate, and the resistance element is formed in a diffusion layer having the same polarity as the high-concentration impurity diffusion layer and a lower concentration than the high-concentration impurity diffusion layer, 2 resistive elements
It is characterized by connecting more than one in series.

(Means 4) Further, at least a pad electrically connected to an external terminal, a resistance element electrically connected to the pad by a metal wiring and formed of an impurity diffusion layer, and the resistance element are the same as the resistance element. The well contact is formed of a polar impurity diffusion layer, and the junction breakdown voltage of the well contact is higher than the drain breakdown voltage formed in the semiconductor integrated device.

[0012]

According to the above-mentioned structure of the present invention, the current amplification factor of the parasitically formed bipolar transistor can be suppressed low. In addition, the reverse breakdown voltage of the parasitically formed diode can be improved. In addition, the collector breakdown voltage of the bipolar transistor parasitically formed can be improved.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a layout plan view of an electrostatic protection circuit according to an embodiment of the present invention. In FIG. 1, the same components as those in FIG. 5 described above are denoted by the same numbers as in FIG. As in FIG. 5, the substrate is P-type. FIG.
Similar to the above, a portion other than the impurity diffusion layer is the substrate region. The difference from FIG. 5 is that the well contact 9 of the N-type high-concentration impurity diffusion layer is arranged at a position surrounded by the sub-contact 7 of the P-type high-concentration impurity diffusion layer. Further, the resistance element 4 of the N-type high-concentration impurity diffusion layer connected in series to the pad 1 by the aluminum wiring 2 is divided into two and connected in series by the aluminum wiring 14. Also, 5 is N
The N-type high-concentration impurity diffusion layer surrounds the resistance element 4 of the N-type high-concentration impurity diffusion layer.

The means 1 will be described with reference to FIG. 1, the resistance element 4 of the N-type high-concentration impurity diffusion layer or the N-type low-concentration impurity diffusion layer 5, the P-type substrate region, and the N-type high-concentration are also shown in FIG. NP is parasitically formed with the well contact 9 of the impurity diffusion layer.
An N-type bipolar transistor is formed. This parasitically formed NPN bipolar transistor will be described with reference to the sectional view of FIG. The sectional view of FIG. 2 is a sectional view of a portion XX ′ in FIG. In FIG. 2, the same components as those in FIG. 1 have the same numbers. As shown in the sectional view of FIG. 2, the N-type low-concentration impurity diffusion layer 5 is used as an emitter,
A parasitic NPN bipolar transistor is formed in which a substrate formed by P type low concentration impurity diffusion is used as a base and a well 8 of an N type low concentration impurity diffusion layer is used as a collector. The description now returns to FIG. 1 of the present invention. FIG. 1 of the present invention.
Then, the well contact 9 of the N-type high-concentration impurity diffusion layer forming the NPN-type parasitic bipolar transistor is arranged at a position surrounded by the sub-contact 7 of the P-type high-concentration impurity diffusion layer having a higher concentration than the substrate. There is. This is because the resistance element 4 of the N-type high-concentration impurity diffusion layer or N
Type low concentration impurity diffusion layer 5, P type substrate region, and P type substrate region portion corresponding to the base of an NPN type bipolar transistor parasitically formed by well contact 9 of N type high concentration impurity diffusion layer It means that the impurity concentration of was substantially increased by the sub-contact 7. Generally, it is said that the higher the ratio of the impurity concentration of the emitter region to the impurity concentration of the base region, the higher the current amplification factor of the bipolar transistor. Therefore,
According to the present invention described above, the resistance element 4 of the N-type high-concentration impurity diffusion layer or the N-type low-concentration impurity diffusion layer 5, and P
The current amplification factor of the NPN type parasitic bipolar transistor formed by the type substrate region and the well contact 9 of the N type high concentration impurity diffusion layer is reduced.

Next, the means 2 will be described with reference to FIG. The resistance element 4 connected in series to the pad 1 by the aluminum wiring 2 or the aluminum wiring 14 is for attenuating the energy of the static electricity applied to the pad 1, as described in the section of the prior art. . The resistance value of the resistance element 4 is preferably about 200Ω according to the experiments conducted by the inventors. If the resistance value of the resistance element 4 is too large, the resistance element 4 limits the electrostatic current, and the resistance element 4 is formed by the diode formed by the impurity diffusion layer 10 and the well contact 9 or by the impurity diffusion layer 11 and the sub contact. The diode does not absorb static electricity,
The resistance element 4 itself is destroyed. On the other hand, the resistance element 4
If the resistance value is too small, the static electricity does not sufficiently attenuate the energy in the resistance element 4, and the diode formed by the impurity diffusion layer 10 and the well contact 9 or the diode formed by the impurity diffusion layer 11 and the sub contact 7. Applied to the diode, the diode formed by the impurity diffusion layer 10 and the well contact 9 or the diode formed by the impurity diffusion layer 11 and the sub contact 7 is easily destroyed. The resistance value of the resistance element formed by diffusion of impurities in the semiconductor integrated device can be obtained by multiplying the specific resistance of the impurity diffusion layer in which the resistance element is formed by the length of the resistance element and dividing by the width of the resistance element. Therefore, 200
There is a size required as a resistance element to obtain a resistance value of Ω. In FIG. 1, the resistance element 4 is divided into two and arranged in order to increase the integration degree of the semiconductor integrated device. The resistance element 4 is arranged laterally so that the long side is parallel to the side direction of the chip of the semiconductor integrated device. When the resistance elements are arranged as described above, the resistance element 4 of the N-type high-concentration impurity diffusion layer or the N-type low-concentration impurity diffusion layer 5, the P-type substrate region, and
N of the NPN type bipolar transistor parasitically formed by the well contact 9 of the N type high concentration impurity diffusion layer
The distance between the resistance element 4 of the N-type high-concentration impurity diffusion layer and the well contact 9 of the N-type high-concentration impurity diffusion layer can be increased. This corresponds to the fact that the base length of the NPN type parasitic bipolar transistor can be increased, and in this case, the resistance element 4 of the N type high concentration impurity diffusion layer or the N type low concentration impurity diffusion layer 5 and the P type substrate. N formed by the region and the well contact 9 of the N-type high-concentration impurity diffusion layer
The current amplification factor of the PN type parasitic bipolar transistor is reduced.

Next, the means 3 will be described with reference to FIG. The resistance element 4 of the N-type high-concentration impurity diffusion layer has the same polarity N
It is surrounded by an impurity diffusion layer 5 having a lower concentration than the resistance element 4 of the mold. The N-type low-concentration impurity diffusion layer 5 is formed in the well 8
It may be manufactured in the same manner as the impurity diffusion of. In FIG. 1, the resistance element 4 of the N-type high-concentration impurity diffusion layer surrounded by the N-type low-concentration impurity diffusion layer 5 is divided into two, which are connected in series by an aluminum wiring 14. In this way, in the case of a long resistance element, it can be arranged in about half the length, the pitch between adjacent pads can be narrowed, and the integration degree of the semiconductor integrated device can be improved. On the other hand, in the case of FIG. 1, the P-type substrate is joined to the low-concentration N-type impurity diffusion layer 5. In the case of the prior art of FIG. 5, the connection of the resistive element 4 portion to the substrate is performed by connecting the P-type substrate and the resistive element 4 to each other.
And the N-type high-concentration impurity diffusion layer. This will be described with reference to the sectional view of FIG. Also in FIG. 3, the same components as those in FIGS. 1 and 5 described above are denoted by the same reference numerals. FIG. 3A is a cross-sectional view of a conventional resistance element portion. Reference numeral 4 is a resistance element of an N-type high-concentration impurity diffusion layer, and 15 is a P-type substrate. As shown in FIG. 3A, the P-type substrate 15 is joined to the resistance element 4 of the N-type high-concentration impurity diffusion layer. Next, an embodiment of the present invention will be described with reference to FIG. Reference numeral 4 is a resistance element of an N-type high-concentration impurity diffusion layer, 5 is an N-type low-concentration impurity diffusion layer, and 15 is a P-type substrate. The resistance element 4 has the same polarity as the resistance element 4, and is surrounded by a diffusion layer 5 having a lower concentration than the resistance element 4. Therefore, the P-type substrate 15 is joined to the N-type low-concentration impurity diffusion layer 5. Generally, the lower the diffusion concentration of the junction, the higher the junction withstand voltage. Therefore, the present invention has a higher junction withstand voltage than the conventional example.

Next, the means 4 will be described with reference to FIG. FIG. 4 is a layout plan view showing a well contact portion of an N-type high-concentration impurity diffusion layer forming the NPN-type parasitic bipolar transistor described above. Parts unnecessary for the explanation are not shown. FIG. 4A shows a conventional well contact portion. 8 is a well of an N-type low-concentration impurity diffusion layer selectively formed in the P-type substrate region, and 9 is N
Type well contact formed of high concentration impurity diffusion layer,
Reference numeral 10 is a P-type high-concentration impurity diffusion layer for forming a diode with the well contact 9. The P-type substrate is joined to the N-type high-concentration impurity diffusion layer 9. Since the N-type drain formed in the semiconductor integrated device is also formed by the N-type high-concentration impurity diffusion layer in the P-type substrate region, it is the same as the above-mentioned junction between the P-type substrate and the well contact 9. Becomes Next, an embodiment of the present invention will be described with reference to FIG.
(B). The well contact 9 is arranged so as to be surrounded by the well 8 as compared with the conventional example shown in FIG. Thus, the P type substrate is joined to the well 8 of the N type low concentration impurity diffusion layer. Therefore, similarly to the description of the means 3 described above, the junction breakdown voltage is higher in the present invention.

Although the P-type substrate has been described above as an example, the same effect can be obtained even in the case of the N-type substrate only by reversing the polarities of the well contact and the diode.

[0019]

As described above, according to the present invention, the current amplification factor of the parasitic bipolar transistor can be reduced by increasing the impurity concentration of the base region of the parasitic bipolar transistor, and the parasitic bipolar transistor is turned on by the application of static electricity. It is possible to limit the current flowing therethrough and prevent the junction from being destroyed by the current.

Further, according to the present invention, the base of the parasitic bipolar transistor can be lengthened, the current amplification factor of the parasitic bipolar transistor can be reduced, and the current flowing when the parasitic bipolar transistor is turned on by the application of static electricity can be limited. It is possible to prevent the destruction of the joint part.

Further, according to the present invention, since the junction breakdown voltage between the resistance element formed in the impurity diffusion layer and connected to the pad in series is improved, static electricity is applied between the substrate and the resistance element. In this case, the junction breakdown voltage between the substrate and the resistance element can be improved.

Further, according to the present invention, since the junction breakdown voltage between the well contact and the substrate forming the parasitic bipolar transistor is improved, the parasitic bipolar transistor is turned on by the application of static electricity and is formed by the well contact and the substrate. It is possible to improve the junction breakdown voltage between the well contact and the substrate when a reverse bias is applied to the diode.

[Brief description of the drawings]

FIG. 1 is a layout plan view of an electrostatic protection circuit that is an embodiment of the present invention.

FIG. 2 is a layout cross-sectional view of the electrostatic protection circuit in the section XX ′ of FIG.

FIG. 3 is a sectional view of a resistance element portion.

FIG. 4 is a sectional view of a well contact portion.

FIG. 5 is a layout plan view of a conventional electrostatic protection circuit.

[Explanation of symbols]

 1 Aluminum Pad 2 Aluminum Wiring 3 Contact 4 Resistance Element 5 Low Concentration Diffusion Layer 6 Aluminum Wiring 7 Sub-Contact 8 Well Region 9 Well Contact 10 Impurity Diffusion Layer 11 Impurity Diffusion Layer 12 Contact 13 Contact 14 Aluminum Wiring 15 Substrate

Claims (4)

[Claims] 1. A pad electrically connected to at least an external terminal, and electrically connected to the pad by a metal wiring,
And a resistance element formed of an impurity diffusion layer or an ion implantation layer, and a well contact formed of an impurity diffusion layer or an ion implantation layer of the same polarity as the resistance element,
A semiconductor integrated device characterized in that an impurity diffusion layer or an ion implantation layer having the same polarity as the substrate and having a higher concentration than the substrate is arranged between the resistance element and the well contact. 2. The semiconductor integrated device according to claim 1, wherein
The resistance element formed of the impurity diffusion layer or the ion implantation layer is arranged such that a long side is parallel to a side direction of a chip of the adjacent semiconductor integrated apparatus. 3. A pad electrically connected to at least an external terminal, and electrically connected to the pad by a metal wiring,
And a resistance element formed of an impurity diffusion layer or an ion implantation layer, the resistance element being formed of a high-concentration impurity diffusion layer or an ion implantation layer having a different polarity from the substrate, and the resistance element being the high-concentration impurity diffusion layer. Characterized by being formed in an impurity diffusion layer or an ion implantation layer having a lower concentration than that of the high concentration impurity diffusion layer or the ion implantation layer and having the same polarity as that of the layer or the ion implantation layer, and two or more resistance elements are connected in series. Semiconductor integrated device. 4. A pad electrically connected to at least an external terminal, and electrically connected to the pad by a metal wiring,
And a resistance element formed of an impurity diffusion layer or an ion implantation layer, and a well contact formed of an impurity diffusion layer or an ion implantation layer of the same polarity as the resistance element,
A semiconductor integrated device, wherein a junction breakdown voltage of the well contact is higher than a drain breakdown voltage formed in the semiconductor integrated device.