JP3119029B2 - Semiconductor integrated circuit device having input protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an input protection circuit, and more particularly to an input protection circuit including a diode capable of easily setting a predetermined high clamp level value.

[0002]

2. Description of the Related Art In order to protect an internal semiconductor integrated circuit from static electricity from the outside and a large abnormal voltage applied accidentally, an example of the prior art in which a diode is connected to an input bonding pad as an input protection circuit is shown. It is shown in FIG. In the same figure, (A) is a plan view, (B) is a sectional view including a partial circuit diagram of a BB portion of (A), and (C) is a circuit diagram.

An input bonding pad 2 and an input wiring layer 3 are continuously formed of aluminum on a P-type semiconductor substrate 1 on which a semiconductor integrated circuit (not shown) is formed. It is connected to the input contact of the semiconductor integrated circuit. The reference potential wiring layer 13 that supplies a reference potential (for example, ground potential: GND) to the semiconductor integrated circuit is also formed of aluminum. Then, a high impurity concentration of N ⁺
The semiconductor region 44 is connected through the contact hole 11, and a P ⁺ -type semiconductor region 45 having a high impurity concentration is formed at a branched portion of the reference potential wiring layer 13.
A diode 46 serving as an input protection circuit 40 is formed by a PN junction 46 formed by the N ⁺ type semiconductor region 44 and the P ⁺ type semiconductor region 45.
This is the input circuit shown in the circuit diagram of FIG.

Normally, when an excessive electric field is applied to a gate electrode located at an input contact of a semiconductor integrated circuit, a gate insulating film thereunder has a small thickness of several tens of nanometers (nanometers), so that the insulating film is damaged. This causes a malfunction of the semiconductor integrated circuit. If an excessive abnormal voltage is applied from the outside through the input bonding pad 2 by the input protection circuit, the voltage is clamped by the protection diode 46 and applied to the gate electrode. The electric field strength can be reduced, and the gate insulating film is prevented from being broken.

However, in the input protection circuit of the semiconductor integrated circuit device, the clamp level (breakdown voltage) of the PN junction diode against an excessive abnormal voltage
Is, N ⁺ -type semiconductor formed simultaneously with the wiring layer and the N ⁺ -type semiconductor region and the P ⁺ -type semiconductor regions are formed in the semiconductor circuit area for ohmic contact in fabricating semiconductor integrated circuits to be protected It is determined by the impurity concentration of region 44 and P ⁺ type semiconductor region 45. That is, it is uniquely determined by a combination of impurity concentrations for obtaining ohmic contact. The N ⁺ type semiconductor region 44 also has an impurity concentration for making ohmic contact with the input wiring layer 3, and the P ⁺ type semiconductor region 45 has an impurity concentration for making ohmic contact with the reference potential wiring layer 13.

Therefore, there is a limitation in increasing the clamp level to a desired value, and it becomes impossible to set various clamp levels suitable for various semiconductor integrated circuits.
There is a disadvantage that the degree of freedom in design and manufacture is lacking.

FIG. 6 shows another prior art in which a protected element and a protection diode in a semiconductor integrated circuit are formed in the same semiconductor region of a semiconductor substrate. Such a semiconductor integrated circuit device is disclosed, for example, in Japanese Patent Publication No. Sho 60-56310.

In a P-type well 62, which is one semiconductor region of a semiconductor substrate 61, an FET 60 which constitutes a semiconductor integrated circuit and must be protected from an excessive abnormal voltage applied to the input bonding pad 2 and provides this protection. The protection diode 66 coexists. That is, FET6
0 is N connected to the reference voltage wiring layer 13 such as V _SS or GND.
⁺ Type source region 63, N ⁺ type drain region 64 for sending the output signal of FET 60 to the next stage element, gate insulating film 68 on the channel region between the two regions, and input bonding pad formed on the gate insulating film. 2 and a gate electrode 69 for receiving an input signal.
On the other hand, a P ⁺ type semiconductor region 67 having an ohmic contact with the P well region 62 is formed, the reference voltage wiring layer 13 is connected to the P ⁺ type semiconductor region 67, and an N ⁺ type semiconductor region 65 for forming the protection diode 66 is formed. It is connected to the input bonding pad 2.

In this device, the N ⁺ type semiconductor region 65
And the P ⁺ type semiconductor region 67 are separated from each other, and the protection diode 66 is formed by the PN junction 66 formed by the N ⁺ type semiconductor region 65 and the P well region 62 around the N ⁺ type semiconductor region 65. Is higher than in FIG. However, the impurity concentration of P well region 62 is FE
Since it is determined by characteristics such as the threshold voltage of T, it is still impossible to freely set the breakdown voltage, that is, the clamp level of the protection diode 66 to a predetermined value.

[0010]

As described above, since the breakdown voltage of the clamp diode in the prior art protection circuit depends only on the impurity concentration of the region constituting the same, various types of semiconductor integrated circuits can be protected. If a clamp level is required, it will be difficult to deal with it.

It is an object of the present invention to provide a semiconductor integrated circuit device having an input protection circuit including a diode which can freely set various clamp levels (breakdown voltages).

[0012]

The present invention is characterized in that a semiconductor integrated circuit provided at a first location on a semiconductor substrate, an input bonding pad provided at a second location on the semiconductor substrate, An input wiring layer connecting between the bonding pad and the semiconductor integrated circuit, a reference potential wiring layer for supplying a reference potential, and the input wiring layer and the reference potential wiring provided at a third location of the semiconductor substrate; And an input protection circuit coupled between the input wiring layer and the input wiring pad, wherein the input protection circuit is connected to the input wiring layer and has a high impurity concentration. A first semiconductor region of one conductivity type, a second semiconductor region of a second conductivity type with a high impurity concentration connected to the reference potential wiring layer, the first semiconductor region and the second semiconductor region; Is arranged between the conductor regions, the first
And second a field strength relaxing region of low impurity concentration to form either a PN junction of a semiconductor region, wherein
When the abnormal voltage is applied to the input bonding pad
The depletion layer extending from the PN junction is connected to the first and second depletion layers.
By reaching one of the other semiconductor regions
Breaking down between the first and second semiconductor regions.
And an electric field intensity alleviating region for clamping the abnormal voltage . here,
The electric field intensity relaxation region is a first conductivity type region having a lower impurity concentration than the first semiconductor region, forms the PN junction with the second semiconductor region, and forms the PN junction with the first semiconductor region. it is possible to configure the input protection diode and the second semiconductor region. Alternatively, the electric field strength relaxation region is a region of a second conductivity type having an impurity concentration lower than that of the second semiconductor region and forms the PN junction with the first semiconductor region, An input protection diode can be constituted by the region and the second semiconductor region. Further, the first semiconductor region, the first
2 and the electric field intensity alleviating region,
It is preferable that they are formed at the same depth in the conductive substrate.
No. Here, it is preferable that the first semiconductor region and the second semiconductor region are separated from each other by 1 to 10 μm, and the space between the first semiconductor region and the second semiconductor region is filled with the electric field intensity relaxation region. Further, the input protection circuit has a third semiconductor region of a first conductivity type that absorbs a breakdown current generated by breakdown when clamping an abnormal voltage from the input bonding pad, and It is preferable that the region is formed so as to be connected to the reference potential wiring layer together with the second semiconductor region.

Another feature of the present invention is that a semiconductor integrated circuit provided at a first location on a semiconductor substrate, an input bonding pad provided at a second location on the semiconductor substrate, An input wiring layer for connecting with a semiconductor integrated circuit, a reference potential wiring layer for supplying a reference potential, and a third wiring board provided at a third location on the semiconductor substrate and between the input wiring layer and the reference potential wiring layer. And an input protection circuit for clamping an abnormal voltage from the input bonding pad, wherein the input protection circuit is connected to the input wiring layer. And a region surrounding the first semiconductor region having a lower impurity concentration than the first semiconductor region and having a width of preferably 1 to 10 μm from at least three directions. The formed first conductivity type electric field intensity relaxing region is connected to the reference potential wiring layer and forms a PN junction with the electric field intensity relaxing region to surround the electric field intensity relaxing region from at least three directions. A second conductivity type second semiconductor region, and a first conductivity type second conductivity type connected to the reference potential wiring layer together with the second semiconductor region and surrounding the second semiconductor region from at least three directions. And a third semiconductor region, wherein a clamp level is set by the electric field intensity relaxing region, and the first semiconductor device is used to clamp an abnormal voltage from the input bonding pad.
And a semiconductor integrated circuit device in which a breakdown current generated by breakdown between the second semiconductor regions is absorbed by the third semiconductor regions.

Another feature of the present invention is that a semiconductor integrated circuit provided at a first location on a semiconductor substrate, an input bonding pad provided at a second location on the semiconductor substrate, An input wiring layer for connecting with a semiconductor integrated circuit, a reference potential wiring layer for supplying a reference potential, and a third wiring board provided at a third location on the semiconductor substrate and between the input wiring layer and the reference potential wiring layer. And an input protection circuit coupled to the input bonding pad, wherein the input protection circuit is connected to the input wiring layer. And forming a PN junction with the first semiconductor region to surround the first semiconductor region, preferably having a width of 1 to 10 μm, from at least three directions. A second-conductivity-type electric-field-strength relaxation region, and a second conductive-type electric-field-strength relaxation region connected to the reference potential wiring layer and having a higher impurity concentration than the electric-field-strength relaxation region. A second conductive type second semiconductor region; and a first conductive type third semiconductor region connected to the reference potential wiring layer together with the second semiconductor region and surrounding the second semiconductor region in at least three directions. A breakdown between the first and second semiconductor regions when a clamp level is set by the electric field intensity relaxation region and an abnormal voltage from the input bonding pad is clamped. In the semiconductor integrated circuit device, wherein the breakdown current generated by the third semiconductor region is absorbed by the third semiconductor region.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a plan view schematically showing the entirety of a semiconductor integrated circuit device (semiconductor chip) 30 according to an embodiment of the present invention.
3 are formed, and the input bonding pad 2 and the input protection circuit 10 (20) of the present invention are formed at each part of the peripheral part 32 except the central part 31. The input wiring layer 3 is formed by connecting the input bonding pad 2 and the input contact (node) 37 of the semiconductor integrated circuit 33, and the reference potential wiring layer 13 for supplying a reference potential to the semiconductor integrated circuit 33 is connected to a ground terminal or the like. And is connected to the reference potential terminal 38 of FIG. The input protection circuit 10 (20) is connected between the reference potential wiring layer 13 and the input wiring layer 3.

The semiconductor integrated circuit 33 includes an element 34. This element is a CCD when the device 30 is a solid-state image pickup device, and may be a MOS type FET in other devices. In either case of the CCD and the MOS type FET, when a clock signal or information signal of a normal level positive voltage is applied to the gate electrode 35 connected to the input node 37, the channel region becomes conductive. However, since the gate insulating film under the gate electrode is as thin as several tens of nm, the input protection circuit 10 (20) is required to protect the input bonding pad 2 from a large abnormal voltage applied accidentally from the outside. .

Referring to FIGS. 2A and 2B, the configuration of the protection circuit 10 according to the first embodiment of the present invention will be described. An input wiring layer 3 connecting the input bonding pad 2 and the input node 37 of the semiconductor integrated circuit is formed of aluminum continuously with the input bonding pad 2 and is connected to a reference potential terminal 38 to supply a reference potential. The reference potential wiring layer 13 is also formed of aluminum.

The input protection circuit 10 coupled between the input wiring layer 3 and the reference potential wiring layer 13 to clamp an abnormal voltage from the input bonding pad 2 includes an insulating film ( An N ⁺ -type semiconductor region 4 having an impurity concentration (peak concentration, the same applies hereinafter) of 5 × 10 ²¹ / cm ³ connected through a plurality of contact holes 11 provided in the N ⁺ -type semiconductor region 4. Has a low impurity concentration of 5 × 10 ¹⁷ / cm ³ and a width w of 3 μm.
And an N-type electric field relaxation region 9 formed so as to surround the N ⁺ type semiconductor region 4 from three directions, and an electric field intensity relaxation region connected to a branched portion of the reference potential wiring layer 13 through a plurality of contact holes 11. And a P ⁺ -type semiconductor region 5 having an impurity concentration of 1 × 10 ¹⁹ / cm ³ formed by forming a PN junction 6 and the region 9 from three directions.
When, further connected through a plurality of contact holes 11 to the reference potential wiring layer 13 with P ⁺ type semiconductor region 5 P ⁺
An N ⁺ type semiconductor region 7 having an impurity concentration of 5 × 10 ¹⁹ / cm ³ formed by surrounding the type semiconductor region 5 from three directions.

As shown in FIG. 2C, the protection circuit 10 includes a protection diode 6 ′ formed between the N ⁺ type semiconductor region 4 and the P ⁺ type semiconductor region 5 and an N type electric field intensity relaxation region 9.
A series body with the resistance element 12 formed in the input wiring layer 3
And the reference potential wiring layer 13.
The breakdown voltage of this protection diode 6 'is PN
One of the features of the present invention is determined by the action of the junction 6 and the depletion layer in the N-type electric field intensity relaxation region 9.

The abnormal voltage from the input bonding pad causes a breakdown of the protection diode 6 ′, and the input voltage at the input node 37 of the internal semiconductor integrated circuit 33 is clamped by the breakdown voltage.
Element 34 (FIG. 1) is protected.

As described above, since the N-type electric field intensity relaxing region 9 of this embodiment is not related to the ohmic contact, it can be set to a low impurity concentration suitable for a required high clamping level. Further, since the N-type electric field intensity relaxing region 9 has a low impurity concentration, it is possible to form the resistive element 12 which functions as a limiter after the diode 6 'has been broken down. Since the resistance value of the resistance element 12 is preferably about 50Ω in an actual device, the impurity concentration and the shape of the N-type electric field intensity relaxation region 9 are adjusted so as to obtain a predetermined breakdown voltage and obtain this resistance value. Can be set.

On the other hand, the N.sup. ⁺ Type semiconductor region 7 functions to effectively absorb the breakdown current generated by the breakdown. That is, the hot electrons are absorbed by the N ⁺ type semiconductor region 7 of the present invention in the same manner as the hot holes generated by the breakdown are absorbed by the P ⁺ type semiconductor region 5 and flow into the reference potential wiring layer 13. Reference potential wiring layer 1
3, it is possible to prevent the operation of the internal semiconductor integrated circuit 33 (FIG. 1) from becoming unstable due to floating and diverging hot electrons on the substrate.

Next, the operation of the electric field intensity relaxing region will be described in detail. The role of the N-type electric field intensity relaxing region 9 is not to use the breakdown voltage between the N-type electric field intensity relaxing region 9 and the P ⁺ type semiconductor region 5 but to use the N ⁺ type semiconductor region 4.
A P ⁺ -type to relax the electric field strength between the semiconductor regions 5, thereby the N ⁺ -type semiconductor region 4 and is shifted an effective breakdown voltage between P ⁺ -type semiconductor regions 5, any breakdown voltage ( (Clamp level) can be set. That is, when an excessively large positive voltage is applied to the input bonding pad 2, the PN junction 6 is in a reverse bias state, and a depletion layer extending in the electric field intensity relaxation region reaches the N ⁺ type semiconductor region 4 from there, resulting in a breakdown phenomenon. Occurs.

Since the breakdown voltage is determined by the manner in which the depletion layer extending to the N ⁺ type semiconductor region 4 reaches the N ⁺ type semiconductor region 4, the width (N ⁺ type semiconductor region) The same voltage is determined by the distance (w) between the 4-P ⁺ type semiconductor regions 5).

Therefore, by arranging the electric field intensity relaxing region 9, a plurality of arbitrary breakdown voltages (clamp levels) can be made the same using the distance w between the N ⁺ type semiconductor region 4 and the P ⁺ type semiconductor region 5 as a parameter. On a semiconductor chip without increasing the number of steps. By the way, if w is made longer, the breakdown voltage becomes higher. On the other hand, if the same breakdown voltage value is obtained by making w longer, it is necessary to lower the impurity concentration in the electric field intensity relaxation region.

When actually designing the device, first, the impurity concentration of the electric field intensity relaxing region is set to 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁷ / cm ^3.
Set a predetermined value from the range of × 10 ¹⁸ / cm ³ ,
Next, the length w is determined so that a predetermined breakdown voltage (clamp level) can be obtained.

In the first embodiment, the impurity concentration of the electric field intensity relaxing region 9 is 5 × 10 ¹⁷ / cm ³ and the width w is 3 μm.
As a result, the breakdown voltage is designed to be 37.5V.

FIG. 3 shows the breakdown voltage (V _BD [A.
U. ] (Arbitrary unit)) and the width w of the electric field intensity relaxation region. The V _{BD at the} point A where w is zero corresponds to that of FIG. w is V _BD from the point B of w ₁ to point C of the w ₂
Is a transition region in which the range of ΔV _BD can be changed by changing w. In this range, a breakdown voltage of any various values, that is, a clap level can be obtained. For example, point A is 25V, point B is 27.5V, C
The point becomes 47.5 V, and by changing w between w _{1 and} w ₂ , the breakdown voltage can be changed over a range of 20 V between B and C. Lower limit w ₁ and w that can change the breakdown voltage is due to lithographic techniques including introduction and diffusion of impurities, the value is 1 [mu] m. On the other hand, the upper limit value w ₂ and w of the electric field strength relaxing region capable of changing the breakdown voltage depends on the impurity concentration of the region, the lowest among the concentration ranges selected in designing actual devices described above When the concentration is 1 × 10 ¹⁷ / cm ³ , w ₂ is 10
μm. As the impurity concentration increases, w ₂ becomes smaller. For example, when the impurity concentration is set to 5 × 10 ¹⁷ / cm ³ as in the first embodiment, w ₂ is 8 μm.
m. The region D where w is larger than w ₂ is the PN generated by the N-type electric field intensity relaxing region 9 and the P ⁺ type semiconductor region 5.
Depletion layer extending from the junction 6 is a saturated region to break down at the electric field strength relaxing region 9 and the P ⁺ -type semiconductor region 5 before reaching the N ⁺ -type semiconductor region 4, in this case, the N ⁺ -type semiconductor region 4 Merely acts as an ohmic contact region, and V _BD is a normal PN junction breakdown voltage which is independent of w and depends only on the impurity concentration of the N-type electric field intensity alleviating region 9 and the P ⁺ -type semiconductor region 5. . Although formed in the same place as the integrated circuit to be protected and the P type and the N type are reversed, the protection diode 66 in FIG. 6 of the prior art corresponds to this region D.

FIGS. 4A to 4C show a protection circuit 20 according to a second embodiment of the present invention. In FIGS. 4A to 4C, the same or similar functions as those in FIGS. 2A to 2C are denoted by the same reference numerals, and the description thereof will not be repeated.

A different point is that a P-type electric field intensity relaxing region 8 is used instead of the N-type electric field intensity relaxing region 9 as an area for setting the clamp level. Is the same as That is, a PN junction 16 is generated between the P-type electric field intensity relaxation region 8 and the N ⁺ type semiconductor region 4, and a depletion layer extending from the PN junction 16 into the P-type electric field intensity relaxation region 8 is a P ⁺ -type. The breakdown voltage of the protection diode 16 ′ between the N ⁺ type semiconductor region 4 and the P ⁺ type semiconductor region 5 is determined so as to reach the semiconductor region 5.
Then, the resistance element 22 formed as a limiter in the P-type electric field intensity relaxation region 8 is inserted between the protection diode 6 ′ and the reference potential wiring layer 13. In the second embodiment, the same effect as in the first embodiment can be obtained.

In the first and second embodiments, the input protection circuit formed on the P-type semiconductor substrate has been described. However, the input protection circuit formed on the N-type semiconductor substrate is also applicable to the P-type semiconductor substrate. The present invention can be applied to an input protection circuit formed in a P-type or N-type well layer in a substrate and to an input protection circuit formed in a P-type or N-type well layer in an N-type semiconductor substrate. Further, the present invention can be applied to an input protection circuit connected to an input bonding pad through a resistance value of polysilicon or a diffusion layer.

[0033]

As described above, according to the present invention, since the PN junctions 6 and 16 are formed by providing the electric field intensity relaxing regions 9 and 8 for setting the clamp level in the diode of the input protection circuit, the semiconductor integrated circuit to be protected is provided. Various values of the clamp level according to the circuit can be designed and set only by selecting the width w of the electric field intensity region. Therefore, it is particularly effective to apply the present invention to a solid-state imaging device requiring various clamp level values. Further, the adverse effect on the inside of the semiconductor integrated circuit due to the emission of the hot electrons into the substrate due to the breakdown current generated by the breakdown is reduced by the PN junctions 6, 16
By forming the N ⁺ -type semiconductor region 7 connected to the reference potential wiring layer 13 in close proximity to the substrate, the above problem can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing an entire semiconductor integrated circuit device according to an embodiment of the present invention.

FIGS. 2A and 2B are diagrams showing an input protection circuit according to the first embodiment of the present invention, wherein FIG. 2A is a plan view and FIG.
FIG. 3C is a cross-sectional view including a partial circuit diagram in a part B, and FIG.

FIG. 3 is a graph showing the relationship between the width (length between the first and second semiconductor regions) w of the electric field intensity relaxation region 9 and the breakdown voltage V _BD in the input protection circuit of the first embodiment. is there.

FIGS. 4A and 4B are diagrams showing an input protection circuit according to a second embodiment of the present invention, wherein FIG. 4A is a plan view and FIG.
FIG. 3C is a cross-sectional view including a partial circuit diagram in a part B, and FIG.

FIG. 5 is a diagram showing a conventional input protection circuit;
(A) is a plan view, (B) is a cross-sectional view including a partial circuit diagram in a BB portion of (A), and (C) is a circuit diagram.

FIG. 6 is a sectional view including a partial circuit diagram showing another conventional technique.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 input bonding pad 3 input wiring layer 4 N ⁺ type semiconductor region 5 P ⁺ type semiconductor region 6, 16 PN junction 6 ′, 16 ′ protection diode 7 N ⁺ type semiconductor region 8 P type electric field relaxation region 9 N Type electric field intensity reduction region 10, 20 input protection circuit 11 contact hole 12, 22 resistor element 13 reference potential wiring layer 30 semiconductor integrated circuit device (semiconductor chip) 31 central portion of semiconductor substrate 1 32 peripheral portion of semiconductor substrate 1 33 semiconductor integration Circuit 34 Element 35 Gate electrode 37 Input contact (node) of semiconductor integrated circuit 33 38 Reference potential terminal 40 Input protection circuit 44 N ⁺ type semiconductor region 45 P ⁺ type semiconductor region 46 PN junction (diode) 60 FET 61 Semiconductor substrate 62 P Type well 63 N ⁺ type source region 64 N ⁺ type drain region 65 N ⁺ type semiconductor region 66 Protection diode 67 P ⁺ type semiconductor region 68 Gate insulating film 69 Gate electrode

Claims (12)

(57) [Claims] 1. A semiconductor integrated circuit provided at a first location on a semiconductor substrate, an input bonding pad provided at a second location on the semiconductor substrate, and between the input bonding pad and the semiconductor integrated circuit. And a reference potential wiring layer for supplying a reference potential, the input wiring layer being provided at a third location of the semiconductor substrate and being coupled between the input wiring layer and the reference potential wiring layer. A semiconductor integrated circuit device comprising: an input protection circuit for clamping an abnormal voltage from a bonding pad; wherein the input protection circuit includes a first impurity type first semiconductor region having a high impurity concentration connected to the input wiring layer; A second conductive type second semiconductor region having a high impurity concentration connected to the reference potential wiring layer; and a second semiconductor region disposed between the first semiconductor region and the second semiconductor region. A field strength relaxing region of low impurity concentration to form either a PN junction of the first and second semiconductor regions, the input bonding pad
Extends from the PN junction when the abnormal voltage is applied to the gate
The depletion layer to be formed in any one of the first and second semiconductor regions.
To reach the other of the first and second
Breaking down between the semiconductor regions to eliminate the abnormal voltage
A semiconductor integrated circuit device having an electric field intensity relaxing region to be ramped . 2. The method according to claim 1, wherein the electric field intensity relaxing region is a region of a first conductivity type having a lower impurity concentration than the first semiconductor region and forms the PN junction with the second semiconductor region. the semiconductor integrated circuit device according to claim 1, characterized in that it constitutes a <br/> input protection diode in the first semiconductor region and said second semiconductor region. 3. The electric field intensity relaxation region is a region of a second conductivity type having an impurity concentration lower than that of the second semiconductor region, forming the PN junction with the first semiconductor region, and the semiconductor integrated circuit device according to claim 1, characterized in that it constitutes a <br/> input protection diode in the first semiconductor region and said second semiconductor region. 4. The first semiconductor region and the second semiconductor region.
The body region and the electric field intensity alleviating region are the semiconductor substrate.
That are formed at the same depth Claims characterized by the following:
2. The semiconductor integrated circuit device according to 1. 5. The semiconductor device according to claim 1, wherein the first semiconductor region and the second semiconductor region are separated from each other by 1 to 10 μm, and the electric field intensity relaxing region is filled between the first semiconductor region and the second semiconductor region. The semiconductor integrated circuit device according to claim 2 or 3. Wherein said claim 1 the electric field strength relaxing region is characterized by having a function as resistive elements, according to claim 2, the semiconductor integrated circuit device according to claim 3 or claim 4. 7. The resistance of the electric field intensity relaxing region between the first semiconductor region and the second semiconductor region is about 5
6. The semiconductor integrated circuit device according to claim 5, wherein the resistance is 0Ω. Wherein said input protection circuit has a third semiconductor region of the first conductivity type for absorbing the breakdown current generated by breakdown when clamping the abnormal voltage from said input bonding pad, said 3. The semiconductor device according to claim 1, wherein the third semiconductor region is formed together with the second semiconductor region so as to be connected to the reference potential wiring layer. A semiconductor integrated circuit device according to claim 6. 9. A semiconductor integrated circuit provided at a first location on a semiconductor substrate, an input bonding pad provided at a second location on the semiconductor substrate, and a portion between the input bonding pad and the semiconductor integrated circuit. And a reference potential wiring layer for supplying a reference potential, the input wiring layer being provided at a third location of the semiconductor substrate and being coupled between the input wiring layer and the reference potential wiring layer. A semiconductor integrated circuit device comprising: an input protection circuit that clamps an abnormal voltage from a bonding pad; wherein the input protection circuit has a first conductivity type first semiconductor region connected to the input wiring layer; A first-conductivity-type field-strength relaxation region having a lower impurity concentration than that of the first semiconductor region and surrounding the first semiconductor region in at least three directions; A second semiconductor region of a second conductivity type having a high impurity concentration which is connected to a line layer and forms a PN junction with the electric field intensity relaxing region and surrounds the electric field intensity relaxing region from at least three directions; A third semiconductor region of the first conductivity type connected to the reference potential wiring layer together with the second semiconductor region and formed so as to surround the second semiconductor region from at least three directions; A clamp level is set by the electric field intensity relaxation area,
Further, a breakdown current generated by a breakdown between the first and second semiconductor regions when clamping an abnormal voltage from the input bonding pad is absorbed by the third semiconductor region. Semiconductor integrated circuit device. Wherein said electric field strength relaxing region is 1~10μm
9. The semiconductor integrated circuit device according to claim 8, wherein the first semiconductor region has a width of the first semiconductor region and surrounds the first semiconductor region. 11. A semiconductor integrated circuit provided at a first location on a semiconductor substrate, an input bonding pad provided at a second location on the semiconductor substrate, and a portion between the input bonding pad and the semiconductor integrated circuit. And a reference potential wiring layer for supplying a reference potential, the input wiring layer being provided at a third location of the semiconductor substrate and being coupled between the input wiring layer and the reference potential wiring layer. A semiconductor integrated circuit device comprising: an input protection circuit that clamps an abnormal voltage from a bonding pad; wherein the input protection circuit has a first conductivity type first semiconductor region connected to the input wiring layer; Semiconductor region and P
A second conductivity type electric field intensity relaxing region formed by forming an N-junction to surround the first semiconductor region from at least three directions, and connected to the reference potential wiring layer and higher than the electric field intensity relaxing region. A second semiconductor region of a second conductivity type having an impurity concentration and formed so as to surround the electric field intensity relaxation region from at least three directions; and a second semiconductor region connected to the reference potential wiring layer together with the second semiconductor region. A third semiconductor region of the first conductivity type formed so as to surround the second semiconductor region from at least three directions, and a clamp level is set by the electric field intensity relaxing region;
Further, a breakdown current generated by a breakdown between the first and second semiconductor regions when clamping an abnormal voltage from the input bonding pad is absorbed by the third semiconductor region. Semiconductor integrated circuit device. 12. The method of claim 11, wherein the electric field strength relaxing region is 1~10μm
11. The semiconductor integrated circuit device according to claim 10, wherein the first semiconductor region has a width of the first semiconductor region in a band shape.