JPH09171484A - Memory control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate the memory access speed so as to judge page hit at a high speed. SOLUTION: While using not a DRAM logic address but a CPU address, a page hit judgement circuit 126 judges whether the memory access of this time is performed to the same bank and the same page as the memory access of the last time or not. The CPU address can be utilized for judging the page hit since the unit of address translation from the CPU address to the DRAM logic address due to an address translation circuit 121 is set to the value higher than the page size of DRAM bank. Thus, the address translating operation and the page hit judging operation can be parallelly performed so that the page hit can be judging at a high speed and the memory access speed can be accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system, and more particularly to an improved memory control system for efficiently accessing a DRAM bank used as a main memory of a personal computer.

[0002]

2. Description of the Related Art In recent years, various notebook-type or laptop-type portable personal computers which are easy to carry and can be operated by a battery have been developed. In this type of personal computer, it is desired to increase the operating speed, and recently, a high-performance microprocessor incorporating a large-scale cache has begun to be used as a CPU.

A microprocessor with a built-in cache is a C
When used as a PU, the number of accesses to the main memory can be reduced, and the system operation performance can be improved to some extent.

However, even if the CPU has a built-in cache, access to the main memory is not lost, and when a cache miss occurs, the CP
It is required that U perform a memory read / write cycle to main memory. Therefore, in actuality, in order to improve the system performance, it is indispensable to increase the execution speed of the memory read / memory write cycle by the CPU.

A dynamic RAM (DRAM) is usually used as a main memory of a personal computer. DRAM is a static RAM (SRA
Compared with M), the cost is lower, but the access speed is slower. In order to solve this problem, recently, in addition to the improvement on the semiconductor technology level such as the improvement of the DRAM chip itself, the improvement on the memory architecture level by adopting the page mode access and the interleave control has been promoted.

In order to perform the page mode access and the interleave control, the memory control system is usually provided with
Built-in logic for determining page hits. The page hit determination is to determine whether or not the address of the memory access generated by the CPU can be obtained in the same page of the same DRAM bank as the access performed immediately before in the page mode access method of the DRAM. If the same page, high-speed access that does not require re-issuance of RAS (row address strobe) is possible.

In the conventional memory control system, first, C
A PU address to DRAM logical address conversion is performed, then a DRAM bank to be accessed is selected, and whether or not the selected DRAM bank is the same as the previously accessed DRAM bank is determined by RAS. Looked up by the decoder. In the case of the same bank, the row address to the selected DRAM bank and the row address of the immediately preceding access are compared by the page hit determination circuit to make a page hit determination.

[0008]

As described above, in the prior art, address translation, before page hit determination is performed,
Processing such as RAS decoding is necessary, and as a result, there is a problem that it takes time to determine a page hit. Therefore, even if the page is hit, a wait cycle is required, and it is impossible to realize a sufficiently high speed access.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory control system capable of executing page hit determination at high speed and realizing high speed memory access. And

[0010]

A memory control system according to the present invention comprises a plurality of DRAM banks to which a plurality of RAS signals are assigned and which can be accessed independently of each other, and a conversion unit which is larger than the page size of these DRAM banks. , The memory address from the CPU to the plurality of D
Address conversion means for converting to a DRAM logical address continuously assigned to the RAM bank and a memory address from the CPU at the time of the previous memory access are held, and the memory address and the memory address from the CPU at the time of this memory access And a page hit determination unit that outputs a page hit signal indicating that the current memory access is in the same bank and the same page as the previous memory access when they match, and the DRAM logic output from the address conversion unit. A RAS decoder that decodes an address and determines which RAS signal of the DRAM bank is to be output, wherein the RAS decoder performs RAS signal output control for DRAM page mode access when the page hit signal is output. And is equipped with .

In this memory control system, the page hit determination means determines whether the current memory access is in the same bank and the same page as the previous memory access by using the CPU address instead of the DRAM logical address. A page hit decision is made. The CPU address can be used for the page hit determination because the unit of address conversion from the CPU address to the DRAM logical address is set to a value equal to or larger than the page size of the DRAM bank. As a result, DRA
Even if the M logical address specifies the same page between the previous access and the current access, the pages with different CPU addresses are not specified. Therefore, the address translation operation and the page hit determination operation can be performed in parallel, the page hit determination can be performed at high speed, and the memory access speed can be increased.

Further, the page hit determination means is a memory in which the memory address from the CPU at the time of the previous memory access and the memory attribute information of the memory address area corresponding to the memory address are different between the write access and the read access. Information indicating whether or not a device is specified and cycle type information indicating whether the memory access at that time is a write access or a read access are held, and the memory device to be accessed is determined by the write access and the read access. If they are different, the held memory address and the memory address from the CPU at the time of the current memory access match, and the held cycle type information and the cycle type of the current memory access match. Output the page hit signal It is preferably configured to.

As a result, the memory attribute can be determined at high speed even when the memory device to be accessed differs between write access and read access.
High-speed memory access that makes use of high-speed page hit determination is possible.

Further, as the memory attribute information, write protection information indicating whether or not write protection is performed and cache information indicating whether or not the caching operation using the cache memory is effective are used as a memory address by the page hit determination means. By holding them together, the cycle to be executed next can be efficiently determined.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a computer system to which a memory control system according to an embodiment of the present invention is applied.

This computer system is for realizing a notebook type or laptop type portable personal computer, and a CPU 11, a system controller 12, a system memory 13 and a BIOS are mounted on a system board 10 as shown in the figure.
ROM 14, real-time clock (RTC) 15, interrupt controller (PIC) 16, keyboard controller (KBC) 17, display controller 18
Etc. have been implemented.

The system board 10 has a CPU
Local bus (sometimes called processor bus) 3
1, a system bus 32 having specifications such as ISA / EISA / PCI, and a memory address bus 33 are provided.

Further, this system has two expansion memory connectors 21 and 22 for connecting expansion memories.
Is provided. FIG. 1 shows a state in which the expansion memories 41 and 42 are connected to the expansion memory connectors 21 and 22, respectively.

The additional memories 41 and 42 are optional memories that are installed by the user as needed to expand the system memory size, and are composed of, for example, a DRAM card, DIMM or SIMM memory module. These additional memories are usually composed of one or more DRAM banks.

The CPU 11 is a microprocessor incorporating a large-scale cache memory, and is connected to the system controller 12 via a CPU local bus 31. The CPU local bus 31 is a group of signals directly connected to the input / output pins of the microprocessor forming the CPU 11. This includes a 32-bit data bus, a 32-bit address bus, various status signal lines and the like.

The system controller 12 is connected between the CPU local bus 31 and the system bus 32, and controls all the memories and I / O devices in the system in response to a request from the CPU 11. The system controller 12 is realized by a single LSI composed of a gate array, in which the system memory 13 and the DRAMs of the expansion memories 41 and 42 are included.
A memory control logic lock is built in to control the.

The system memory 13 is used as a main memory of this system, and is usually composed of one or more DRAM banks. The system memory 13 stores an operating system, application programs to be executed, various processing data, and the like.

The system memory 13 is mounted on the system board 10 via a predetermined connector or directly. The system memory 13 is a 32-bit memory device, and its data port is a CPU local bus 31.
32 bit data bus, and the address input port is connected to the memory address bus 33.
The memory address bus 33 is an address bus dedicated to DRAM, and the physical address (row address / column address) of the DRAM is output from the system controller 12 onto this memory address bus 33.

Similarly, the expansion memories 41 and 42 are also 32-bit memory devices, and their data ports are connected to the 32-bit data bus of the CPU local bus 31 via the corresponding connectors 21 and 22, and the address input ports are provided. Are connected to the memory address bus 33.

The system memory 13 has two row address strobe signal lines (RAS lines: RAS0, RA).
S1) is connected. Similarly, another two row address strobe signal lines (R
AS lines: RAS2, RAS3) are connected, and the extended memory connector 22 is also connected with another two row address strobe signal lines (RAS lines: RAS4, RAS5).

Further, in the system memory 13 and the expansion memories 41 and 42, a column address strobe signal line (CAS line) and other various control signal lines (write enable signal line WE, output enable signal line OE) are provided.
Etc.) are commonly connected.

System memory 13 and additional memory 4
All DRAM banks in 1, 42 are D of CPU11.
It is located in the RAM memory address space. In this system, in order to simplify the decoding condition of each RAS line and to make the best use of the interleave architecture, those DRAM banks are arranged at the smaller addresses in the larger memory size.

System memory 13 and additional memory 4
In the read / write access control of 1, 42, R
One of the AS lines (RAS0 to RAS5) is set to the active state, and the DRAM bank connected to the active RAS line is selected as the DRAM bank to be accessed. Such energization control of the RAS line is executed by the memory control logic of the system controller 12.

FIG. 2 shows the structure of the memory control logic.

The memory control logic lock 120 is a DRAM.
Of the address conversion circuit 121, the RAS decoder 122, the row address / column address multiplexer 123, and the CAS generation circuit 1.
24, a timing control circuit 125, and a page hit determination circuit 126.

The address conversion circuit 121 converts the CPU address (A31: 02) into the DRAM logical address (MA3).
1:02). This conversion is performed in order to continuously allocate a plurality of DRAM memory areas distributed in the memory address space of the CPU 11 to the logical address space dedicated to DRAM access. An example of this address conversion operation is shown in FIG.

That is, as shown in FIG. 3A, the memory address space of the CPU 11 is usually a DRAM such as a system memory area or a PM memory area.
In addition to the area, a reserved area (0A0000H to 0C0000H) for allocating a video RAM, a BIOS ROM, various option ROMs, and the like is secured. The address conversion circuit 121 determines the DRA immediately before and after the reserved area according to the CPU memory map.
Address conversion is performed so that addresses in the M area are continuous.

In addition, the VG stored in the BIOS ROM
When A BIOS, system BIOS, etc. are copied to the DRAM and used, as shown in FIG. 3B, the CPU addresses assigned to the VGA BIOS area and the system BIOS area of the reserved area are also
Converted to DRAM logical address. Further, in the case of the CPU having the system management mode (SMM), the CPU address assigned to the SMRAM area used only in the SMM is also converted into the DRAM logical address.

The conversion from the CPU address to the DRAM logical address is performed in units of 16 Kbytes, for example. Therefore, the lower bit part (MA13: 02) of the DRAM logical address is C even after the address conversion.
It is equal to the lower bit part (A13: 02) of the PU address.

The DRAM logical address (MA31: 02) obtained by the address conversion circuit 121 is used for addressing a DRAM bank in the system.

The RAS decoder 122 has a DRAM logical address (MA31: 0) according to the decoding conditions of RAS0 to RAS5 set in its internal register.
2) is decoded and its D is detected in the RAS0 to RAS5 lines.
RAS having a decoding condition satisfied by the RAM logical address
Select a line to activate it. The timing control circuit 1 determines the timing of activating the RAS line.
It is controlled by the timing control signal CONT1 from 25.

The decoding operation of the RAS decoder 122 can be performed only by detecting the match / mismatch between the decode condition of each RAS line and the DRAM logical address. How the decoding conditions of the RAS0 to RAS5 lines are determined will be described in detail with reference to FIG.

The row address / column address multiplexer 123 has a DRAM logical address (MA31: 0).
2) is a row address (RA) and a column address (C) for addressing the DRAM bank to be accessed.
Decomposes into A). A control parameter indicating the start bit position of the row address (RA) of each DRAM bank is preset in the internal register of the row address / column address multiplexer 123. Row address (R
The operation of decomposing into A) and the column address (CA) is performed according to the control parameter corresponding to the DRAM bank to be accessed.

The row address (RA) and the column address (CA) are output on the memory bus 33 in a time division manner. This output timing is the timing control circuit 125.
Is controlled by the timing control signal CONT2.

The CAS generation circuit 124 controls the energization of the CAS line according to the timing control signal CONT3 from the timing control circuit 125.

The timing control circuit 125 controls the operations of the RAS decoder 122, the row address / column address multiplexer 123, and the CAS generation circuit 124 by generating the timing control signals CONT1 to CONT3 described above. The operation of generating the timing control signal is controlled by the page hit signal HIT from the page hit determination circuit 126.

The page hit determination circuit 126 uses the previous D
The CPU address at the time of RAM access is held as a page heat determination CPU address, and the presence or absence of a page hit is determined by comparing the CPU address with the CPU address at the time of the next DRAM access. Here, the page hit means that the next DRAM access accesses the same page in the same DRAM bank as the previous time. When it is determined that a page hit has occurred, this is notified to the timing control circuit 125 by a page hit signal HIT.

As described above, the page hit determination operation is
This is done based on the value of the CPU address, not the DRAM logical address. This makes it possible to perform the address translation operation and the page hit determination operation in parallel. The CPU address can be used for page hit determination because the unit of address conversion from the CPU address to the DRAM logical address (16K bytes) is DRAM.
This is because it is set to a value larger than the page size of the bank (up to about 4 Kbytes). This makes DR
Even if the AM logical address specifies the same page for the previous access and the current access, the page with different CPU addresses will not be specified.

To determine a page hit, all upper addresses after the column address in the CPU address (A31: 02) are used. In the conventional method, the address used for determining whether or not the DRAM is accessed and for determining the DRAM access narrative bank is included.

The number of bits of the column address, that is, the page size is different for each DRAM bank to be accessed. Therefore, a control parameter for designating a bit to be used for page hit determination for each RAS line is set in advance in the internal register of the page hit determination circuit 126, and the page hit determination is performed according to the control parameter corresponding to the DRAM bank to be accessed. A decision is made.

DR by this memory control logic 120
The AM control timing is classified into cycle timings corresponding to the following three states.

(1) Page hit This is because the DRAM access this time is the same as the previous DRA.
Accessing the same page in M bank. In this case, the DRAM bank is access controlled in page mode. That is, only the column address and the activation timing of the CAS line are controlled, and the RAS decoder 122 does not switch the RAS line. Further, the RAS line continues to be maintained in the active state even after the last memory cycle is completed.

(2) Bank miss This is because the DRAM access this time is different from the previous one.
It refers to accessing the M bank. In this case, RAS
Switching of the RAS line by the decoder 122 occurs, and D
The RAM bank is accessed in a normal DRAM access cycle. Further, the page hit determination CPU address held in the page hit determination circuit 126 is updated.

(3) Page miss This is because the DRAM access this time is the same as the previous DRA access.
It refers to accessing different pages in M bank.
In this case, the RAS decoder 122 resets the same RAS line as the previous one to the active state again, and the DRA
The M bank is accessed in a normal DRAM access cycle. Further, the page hit determination CPU address held in the page hit determination circuit 126 is updated.

Next, the decoding conditions of each RAS line set in the RAS decoder 122 will be described with reference to FIGS. 4 to 6.

FIG. 4 shows an example of the DRAM memory map in the system. This DRAM memory map is, as shown in FIG. 1, two 2 Mbyte DRAMs as the system memory 13 on the system board 10.
The banks are mounted, the expansion memory 41 of the expansion memory connector 21 is composed of one 8 Mbyte DRAM bank, and the expansion memory 42 of the expansion memory connector 22 is
Corresponds to the case where it is composed of two 4 Mbyte DRAM banks.

In this case, these DRAM banks are arranged in descending order of memory size, that is, as shown in FIG.
M-byte DRAM bank, 2 4 M-byte DRAM banks, 2 2 M-byte DRAM banks
It is placed in a 0 Mbyte DRAM logical address space.

In this memory arrangement, 8 Mbyte D
An address range of 0 to 8 Mbytes is assigned to the RAS2 line corresponding to the RAM bank. In addition, the RAS4 line corresponding to the first 4 Mbyte DRAM bank has 8 to 12
An address range of M bytes and an address range of 12 to 16 Mbytes are assigned to the RAS5 line corresponding to the next 4 Mbyte DRAM bank. Furthermore, the RAS0 line corresponding to the first 2 Mbyte DRAM bank has 16 to 18 M
An address range of 18 to 20 Mbytes is assigned to the RAS1 line corresponding to the byte address range and the next 2 Mbyte DRAM bank. Since the RAS3 line is not used, no address range is assigned to this RAS3 line.

At this time, the decoding conditions of the RAS0 to RAS5 lines are determined as shown in FIG.

As a decoding condition for each of the RAS0 to RAS5 lines, all the DRAM logical address values (MA31: which belong to the address range assigned to each RAS line are set).
The bit string that is commonly present only in 02) is used.

That is, the decoding condition of the RAS2 line is
Upper 9 bits (MA31 to 23) of DRAM logical address value (MA31: 02) = “0000 0000 0”
Becomes The lower 21 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of the 8-Mbyte DRAM bank connected to the RAS2 line.

The decoding condition of the RAS4 line is DR
Upper 10 bits (MA31 to 22) of AM logical address value (MA31: 02) = “0000 0000 10”
Becomes The lower 20 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of a 4 Mbyte DRAM bank connected to the RAS4 line.

The decode condition of the RAS5 line is that the upper 10 bits (M) of the DRAM logical address value (MA31: 02) are set.
A31 to 22) = “0000 0000 11”. The lower 20 bits of the DRAM logical address value (MA31: 02) are 4M bytes DR connected to the RAS5 line.
It is used as the row address and column address of the AM bank.

The decode condition of the RAS0 line is that the upper 11 bits (M) of the DRAM logical address value (MA31: 02).
A31 to 21) = “0000 0001 000”. The lower 19 bits of the DRAM logical address value (MA31: 02) are 2M bytes DR connected to the RAS0 line.
It is used as the row address and column address of the AM bank.

The decoding condition of the RAS1 line is that the upper 11 bits (M) of the DRAM logical address value (MA31: 02) are set.
A31 to 21) = “0000 0001 000”. The lower 19 bits of the DRAM logical address value (MA31: 02) are 2M bytes DR connected to the RAS0 line.
It is used as the row address and column address of the AM bank.

As described above, the common bit string belonging to the address range corresponding to each RAS line is used as the decoding condition of each RAS line. Therefore, the RAS decoder 122 described above only needs to detect the match / mismatch between the DRAM logical address value and the decode condition for each RAS line.
The hardware configuration can be greatly simplified as compared with the conventional one.

Next, the decoding condition of each RAS line when the page interleave architecture is adopted will be described.

When page interleaving is performed, FIG.
The five DRAM banks thus mapped are classified into bank groups capable of page interleaving.
Each bank group includes a combination of banks having adjacent memory address ranges and matching total memory sizes. Such grouping is performed in order from the smallest DRAM logical address.

That is, in the example of FIG. 4, 8M of RAS2
Two 4 allocated to the address range following the byte DRAM bank address range (0 to 8 Mbytes)
Since the total memory size of the M-byte DRAM bank is 8 M bytes, one page interleave group is formed by the three banks corresponding to RAS2, RAS4, and RAS5.

Since the 2-Mbyte DRAM bank of RAS1 is assigned to the address range subsequent to the address range of the 2-Mbyte DRAM bank of RAS0 (16 to 8 Mbytes), 2 corresponding to RAS0 and RAS1.
One bank constitutes another page interleave group.

In this case, the decoding condition of each RAS line is changed as shown in FIGS.

That is, RAS2 and RAS of group 1
4 and RAS5, as a decoding condition, a bit string commonly present in all DRAM logical address values (MA31: 02) belonging to an address range of 16 Mbytes (0 to 16 Mbytes) assigned to group 1, RAS2, Column address of DRAM bank corresponding to RAS4 and RAS5 (in-page address)
And the bit string between the row address (page address) is used.

That is, as shown in FIG. 6, RAS2, RA
In the total address range of 16 Mbytes allocated to S4 and RAS5, the upper 8 bits (MA31 to 24) of the DRAM logical address value (MA31: 02)
= “0000 0000” is commonly present and does not exist in group 2. Therefore, (MA31-2
4) = “0000 0000” means RAS2, RAS
4 and RAS5 are used as common decoding conditions.

With respect to RAS2, the start position of the row address in the DRAM logical address is left shifted by 1 bit, and 1 bit (M bit) between the row address and the column address of the 8-Mbyte DRAM bank corresponding to RAS2 is shifted.
A12) = “0” is added as a decoding condition.

For each of RAS4 and RAS5,
The starting position of the row address in the DRAM logical address is shifted to the left by 2 bits, and the value of 2 bits (MA13, 12) between the row address and the column address of each corresponding 4 Mbyte DRAM bank is added as an address condition. . 2 bits are used for RA
This is because the memory size of each of S4 and RAS5 is half the memory size of RAS2.

That is, for RAS4, its RA
2 bits between the row address and the column address of the 4-Mbyte DRAM bank corresponding to S4 (MA13, 12)
= “01” is added as a decoding condition, and for RAS5, a 4-Mbyte DRAM corresponding to that RAS5
2 bits (MA13, 12) = “11” between the row address and the column address of the bank are added as an address condition.

In this way, RAS2, RAS4, RAS5
When the decoding conditions for RAS2 are determined, 8 Mbyte D of RAS2
Even pages (0, 2, 4, 6, ...) Within the address range of 0 to 16 Mbytes are allocated to the RAM bank, and 0 to 16 are allocated to the 4 Mbyte DRAM bank of RAS4.
Part of an odd-numbered page in the M-byte address range (1,
, 5), and the remaining odd pages (3, 7, 11, ...) In the address range of 0 to 16 Mbytes are assigned to the 4 Mbyte DRAM bank of RAS5.

Therefore, when continuous access is performed in the range of 0 to 16 Mbytes, RAS2, RAS4, R
In the order of AS2, RAS5, RAS2, ..., Three DRAM banks are alternately accessed in page units.

On the other hand, the decoding conditions of RAS0 and RAS1 of group 2 are as follows.

That is, as the decoding conditions of RAS0 and RAS1, all DRAM logical address values (MA31: 0) belonging to the address range of 4 Mbytes (16 to 20 Mbytes) assigned to group 2 are assigned.
2) bit strings commonly present in RAS0 and RAS1
The column address and the bit string between the row addresses of the DRAM bank corresponding to each are used.

In the total address range of 4 Mbytes allocated to RAS0 and RAS1, the upper 10 bits (MA3) of the DRAM logical address value (MA31: 02).
1 to 22) = “0000 0001 00” exist in common, and this does not exist in group 1. Therefore, (MA31-22) = “0000 0001 0
0 ″ is used as a common decoding condition for RAS0 and RAS1.

As for RAS0, the starting position of the row address in the DRAM logical address is shifted left by 1 bit to generate a 2 Mbyte DRAM corresponding to RAS0.
One bit (MA11) = “0” between the row address and the column address of the bank is added as a decoding condition.

Also for RAS1, the starting position of the row address in the DRAM logical address is shifted to the left by one bit, and the corresponding one bit (MA1
1) = “1” is added as a decoding condition.

When the decoding conditions for RAS0 and RAS1 are determined in this way, even-numbered pages (0, 2, 4, 6, ...) In the 4 Mbyte address range of 16 to 20 Mbytes in the 2 Mbyte DRAM bank of RAS0 are determined. ) Is assigned, and odd-numbered pages (1, 3, 5, 7, ...) Are assigned to the 2-Mbyte DRAM bank of RAS1. Therefore, when continuous access is performed in the range of 16 to 20 Mbytes, RAS0, RAS1, RAS0, RAS
Two DRAM banks are alternately accessed page by page in the order of 1, ...

As described above, the page interleaving determines the decoding condition of each RAS based on the bit string commonly existing in the address range of the interleave group and the predetermined bit string between the row address and the column address.
It can be realized only by setting it in the RAS decoder 122.

Initial setting processing for the memory control logic 120 such as setting of decoding conditions in the RAS decoder 122 is executed by the IRT routine of the BIOS ROM 14.

FIG. 7 shows the procedure of the initialization operation for the memory control logic 120 executed by the BIOS IRT routine.

When the system is powered on, the IRT routine first executes the memory type of each DRAM bank (bit width of each column address and row address).
And the memory size is detected according to the memory bank type (step S11). The bit width of each of the column address and the row address is the DRA to be tested.
This can be detected by executing a write / read compare test for a specific memory address in the M bank.

Details of the memory size detection processing operation performed in step S11 will be described later with reference to FIG.

Next, the IRT routine calls the DRT in the system.
The memory of the RAM bank is relocated (step S1)
2). In this memory relocation, as described in FIG.
The DRAM banks are arranged in descending order of memory size starting from the DRAM bank with the largest memory size, and each D
The address range to be assigned to the RAM bank is determined.

Next, as described with reference to FIG. 5, the IRT routine detects, for each address range assigned to each DRAM bank, a bit string commonly present only in the DRAM logical address values belonging to that range, and the common bit string is detected. Is determined as a decoding condition for each RAS line (step S13).

When the page interleave architecture is not used, the IRT routine sets the decode condition of each RAS line determined in step S13 in the internal register of the RAS decoder 122 as it is (step S).
17). Next, the IRT routine sets a control parameter that specifies the row address start position for each RAS line in the internal register of the row address / column address multiplexer 123, and also uses it in the internal register of the page hit determination circuit 126 for page hit determination. A control parameter for specifying the CPU address position to be set for each RAS line is set (step S18). The values of these control parameters are determined according to the memory bank type detected in step S11.

On the other hand, when the page interleave architecture is adopted, the IRT routine executes step S1.
A group capable of page interleaving is determined according to the DRAM map arranged in the memory size order in 2 (step S15). Next, the IRT routine changes the decoding condition of each RAS based on the bit string commonly existing in the address range of the page interleave group and the predetermined bit string between the row address and the column address (step S16).

After this, the IRT routine proceeds to step S1.
The decode condition of each RAS line determined in 6 is set in the internal register of the RAS decoder 122 (step S1).
7). Next, the IRT routine sets a control parameter that specifies the row address start position for each RAS line in the internal register of the row address / column address multiplexer 123, and also uses it in the internal register of the page hit determination circuit 126 for page hit determination. A control parameter for specifying the CPU address position to be set for each RAS line is set (step S18). The row address start position is determined based on the memory bank type detected in step S11 and the number of bits between the row address and the column address used as the decoding condition for page interleaving. The position of the CPU address used for the page hit determination is determined according to the memory bank type detected in step S11.

Next, referring to FIGS. 8 to 12, the DRA
The principle of the memory size detection process for M banks will be described.

First, referring to FIG. 8, the types of DRAM banks whose access can be controlled by one RAS will be described. The DRAM banks are roughly classified into four banks of type 1 to type 4, as shown in the figure.

The type 1 DRAM bank has a memory size of 2 Mbytes. This type 1 DRAM bank includes four 4M bit DRAM chips each having 512K (1K rows × 512 columns) × 8 bits, a row address bit width of 10 bits, and a column address bit width of 9 bits. is there.

The type 2 DRAM bank has a memory size of 4 Mbytes. This type 2 DRAM bank includes eight 4M bit DRAM chips each having a configuration of 1M (1K rows × 1K columns) × 4 bits, a row address bit width is 10 bits, and a column address bit width is 1 bit.
0 bits.

The type 3 DRAM bank has a memory size of 8 Mbytes. This type 3 DRAM bank is 2M (2K rows x 1K columns) x 16-bit 16M
It includes four bit DRAM chips, the row address bit width is 11 bits, and the column address bit width is 10 bits.

The type 4 DRAM bank has a memory size of 16 Mbytes. This type 4 DRAM bank consists of 4M (2K rows × 2K columns) × 4 bits 16
It includes eight M-bit DRAM chips, the row address bit width is 11 bits, and the column address bit width is 11 bits.

FIGS. 9, 10, and 11 show the memory configurations of the system memory 13, the additional memory 41, and the additional memory 42 of FIG. 1, respectively.

The system memory 13 has two 1 type 2
In the case of the M-byte DRAM bank, as shown in FIG.
The four DRAM chips in the AM bank are commonly connected to the RAS0 line and the CAS line, and the other four DRAM chips in the 2 Mbyte DRAM bank are the RAS1 line and the CA line.
Commonly connected to the S line. Further, all the chips in these two 2 Mbyte DRAM banks are connected in parallel to both the memory address bus 33 and the data bus 322.

RAS0 and RAS1 determine which of these two 2 Mbyte DRAM banks is addressed.
Of which is activated.

When the RAS0 line is activated, the lower 10 bits of the address value output on the memory address bus 33 at that time are used as the row address of the RAS0 line.
It is taken into each of the four chips connected to the line. After that, the four chips connected to the RAS0 line are connected to the memory address bus 33 when the CAS line is activated.
The lower 9 bits of the address value output above are fetched as a column address. RAS0 is defined by these 10-bit row address and 9-bit column address.
The same address of each of the four chips connected to the line is simultaneously addressed, and the DRAM bank corresponding to the RAS0 line is read / write accessed in units of 32 bits, that is, 8 bits per chip.

Similarly, when the RAS1 line is activated, the row address of the lower 10 bits of the address value output on the memory address bus 33 at that time is the R address.
It is taken into each of the four chips connected to the AS1 line. After that, the four chips connected to the RAS1 line take in the column address of the lower 9 bits of the address value output on the memory address bus 33 when the CAS line is activated. These 10-bit row address and 9-bit column address enable RA
The same memory location of each of the four chips connected to the S1 line is simultaneously addressed, and the DR corresponding to the RAS1 line in units of a total of 32 bits of 8 bits per chip
The AM bank is read / write accessed.

When the extension memory 41 is composed of one type 3 8-Mbyte DRAM bank,
As shown in FIG. 10, the 8-Mbyte DRAM
The four DRAM chips in the bank are RAS2 line and CA
Commonly connected to the S line. Further, all the chips in the 8-Mbyte DRAM bank are connected in parallel to both the memory address bus 33 and the data bus 322.

When the RAS2 line is activated, the lower 11 bits of the address value output on the memory address bus 33 at that time are used as the row address of the RAS2 line.
It is taken into each of the four chips connected to the line. After this, the four chips connected to the RAS2 line will have the memory address bus 33 when the CAS line is activated.
The lower 10 bits of the address value output above are fetched as a column address. By these 11-bit row address and 10-bit column address, RA
Corresponding storage locations of each of the four chips connected to the S0 line are simultaneously addressed, and the DRAM bank corresponding to the RAS2 line is read / write accessed in units of 32 bits, that is, 8 bits per chip.

When the additional memory 42 is composed of two 4 Mbyte DRAM banks of type 2,
One 4 Mbyte DRA as shown in FIG.
Eight DRAM chips in M bank are RAS 4 lines and C
The eight DRAM chips of the other 4 Mbyte DRAM bank are commonly connected to the AS line, and commonly connected to the RAS5 line and the CAS line. Further, all the chips in these 4 Mbyte DRAM banks are connected in parallel to both the memory address bus 33 and the data bus 322.

RAS4 and RAS5 determine which of these two 4 Mbyte DRAM banks is addressed.
Of which is activated.

When the RAS4 line is activated, the lower 10 bits of the address value output on the memory address bus 33 at that time are used as the row address of the RAS4 line.
It is taken into each of the eight chips connected to the line. After this, the eight chips connected to the RAS4 line are connected to the memory address bus 33 when the CAS line is activated.
The lower 10 bits of the address value output above are fetched as a column address. By these 10-bit row address and 10-bit column address, R
The same memory location of each of the eight chips connected to the AS4 line is simultaneously addressed, and the DRAM bank corresponding to the RAS4 line is read / write accessed in units of 32 bits, that is, 4 bits per chip.

Similarly, when the RAS5 line is activated, the lower 10 bits of the address value output on the memory address bus 33 at that time are connected to the RAS5 line as the row address. Is taken into each. After this, 8 connected to RAS5 line
One chip fetches the lower 10 bits of the address value output on the memory address bus 33 as the column address when the CAS line is activated. The same memory location of each of the eight chips connected to the RAS5 line is simultaneously addressed by the 10-bit row address and the 10-bit column address, and the 4-bit per chip makes a total of 32 bits to the RAS5 line. The corresponding DRAM bank is read / write accessed.

As described above, the relationship between the number of bits used as a row address and the number of bits used as a column address is different for each type of DRAM bank. The memory size of the DRAM bank connected to each RAS line is detected by utilizing the difference in the number of bits used as a row address and a column address.

The procedure of the memory size detection process executed in step S11 of the IRT routine will be described below with reference to the flowchart of FIG.

The IRT routine includes RAS0, RAS1,
The memory size detection processing of the DRAM banks connected to the RAS line is performed in the order of RAS2, .... The IRT routine first sets a predetermined decoding condition in the RAS decoder 122 so that only the activation of the RAS line to be inspected is permitted (step S21). In this case, the inspection target R
As a decoding condition for the AS line, a bit string common to the memory address values used in several memory accesses for detecting the memory size is used. In addition, all the other RAS lines except the RAS line to be inspected are different from the RAS line to be inspected so that the RAS lines are not activated by several memory accesses for detecting the memory size. A predetermined bit string is set as each decoding condition.

Next, in the IRT routine, the type 4 DRAM bank (column address CA = 11 bits, row address RA = 11 bits) having the largest number of column address bits among the type 1 to type 4 DRAM banks is inspected. Assuming that the DRAM bank is connected to the target RAS line, a write / read compare test is performed on the DRAM bank (step S22). In this case, the row / column address multiplexer 123 is set with a control parameter corresponding to the type 4 DRAM bank. In the write-read-compare test, write access of write address 00001000H (H indicates hexadecimal display) and read address 00000000H
Read access is performed, and it is checked whether or not the write data at that time and the read data match (step S2).
3).

If the DRAM bank actually connected to the RAS line to be inspected has the type 4 DR as expected.
In the case of the AM bank, the data can be normally written in the address 00001000H, so that the values of the write data and the read data do not match. On the other hand, inspection target R
When the DRAM bank actually connected to the AS line is a type 1, type 2, or type 3 bank having a column address number of 10 bits or less, the values of the write data and the read data match. This is for the following reason.

That is, since the setting corresponding to the DRAM bank of type 4 is made in step S22, the 11-bit row address RA (MA23, ..., And) output at the write access of the address 00001000H.
MA13) = 0000000000 and the 11-bit column address CA (MA12, ..., MA02)
= 10000000. In a DRAM bank in which the number of column addresses is 10 bits or less, the value "1" of the most significant bit MA12 of the 11-bit column address CA is ignored. Therefore, type 1, type 2,
Alternatively, when a type 3 bank is connected, the column address CA = 000 in the first row is obtained by the write access of the write address 00001000H.
Address specified by 0000000, that is, address 0
Data is written in 0000000H. As a result, the read data read by the read access of the read address 00000000H matches the write data.

Therefore, when a mismatch between the write data and the read data is detected in step S23, the DRAM bank connected to the RAS line to be inspected is the type 4 DRAM bank (CA = 11 bits, R
If it is determined that A = 11 bits and memory size = 16 Mbytes (step S24), and the match between the write data and the read data is detected, the inspection target R
The DRAM bank connected to the AS line has another type (type 1,
It is determined to be a type 2 or type 3) DRAM bank. In this case, the following step S25
The following processing is performed.

That is, this time, the IRT routine is the type 3 which has the next largest column address bit number after the type 4.
(Or type 2) memory configuration (column address CA
= 10 bits, row address RA = 11 bits), the DRA
A write / read compare test is performed on the M bank (step S25). In this write-read-compare test, a write access of write address 0000000080H and a read access of read address 00000000H are performed, and it is checked whether the write data and the read data at that time match (step S2).
6).

If the DRAM bank actually connected to the RAS line to be inspected is a type 1 DRAM bank whose column address number is 9 bits or less,
Since the most significant bit "1" of the column address is ignored as described above, the data is written to the address designated by the address 00000000H of the type 1 DRAM bank. As a result, the values of the write data and the read data match. Therefore, when a match between the write data and the read data is detected, the DRAM bank connected to the RAS line to be inspected is a type 1 DRAM bank (CA = 9 bits, RA = 10 bits, memory size =
It is determined to be 2 Mbytes) (step S27).

On the other hand, the type 2 or type 3 D having the 10-bit column address bit number as expected by the DRAM bank actually connected to the RAS line to be checked.
In the case of the RAM bank, data can be normally written in the address 00010000H, so that the values of the write data and the read data do not match. Therefore, when a mismatch between the write data and the read data is detected, the following processing from step S28 is performed in order to detect which type 2 or type 3 DRAM bank is connected. .

That is, the IRT routine, in this case, is a type 3 DRAM bank (column address CA = 1) having a large number of row address bits among these DRAM banks.
Assuming that 0 bit and row address RA = 11 bits) are connected, a write / read compare test is performed on the DRAM bank (step S28).

In this write-read-compare test, a write access of write address 00400000H and a read access of read address 00000000H are performed, and it is checked whether or not the write data and the read data at that time match (step S29).

If the DRAM bank actually connected to the RAS line to be inspected has the type 3 DR as expected.
In the case of the AM bank, the data can be normally written in the address 00400000H, so that the values of the write data and the read data do not match. On the other hand, inspection target R
If the DRAM bank actually connected to the AS line is a type 2 bank whose row address number is 10 bits, the values of the write data and the read data match. This is for the following reason.

That is, since the setting corresponding to the DRAM bank of type 3 is made in step S28, the 11-bit row address output at the time of address 00400000H write access is RA (MA22, ...,
MA12) = 10000000, and a 10-bit column address CA (MA11, ..., MA02)
= 0000000000. The number of row addresses is 10
In the bit type 2 DRAM bank, the value "1" of the most significant bit MA22 of the 11-bit row address RA is ignored. Therefore, when the type 2 bank is connected, the write address 0040000
By the write access of 0H, the data is written to the address specified by the column address CA = 0000000000000 in the first row, that is, the address 00000000H. As a result, the read address 00000
The read data read by the read access of 000H matches the write data.

Therefore, when the mismatch between the write data and the read data is detected in step S29, the DRAM bank connected to the RAS line to be inspected is the type 3 DRAM bank (CA = 10 bits, R
If it is determined that A = 11 bits and memory size = 8 Mbytes (step S30), and on the other hand that the match between the write data and the read data is detected, the inspection target RA
The DRAM bank connected to the S line is a type 2 DRAM bank (CA having 10 row address bits).
= 10 bits, RA = 10 bits, memory size = 4M
(Byte) is determined (step S31).

Next, the RAS decoder 12 described with reference to FIG.
2. Row address / column address multiplexer 12
3 and the page hit determination circuit 126 will be described in detail.

FIG. 13 shows a specific circuit configuration of the RAS decoder 122. The RAS decoder 13
As shown, it includes six RAS decoding circuits 51 to 56 corresponding to the RAS0 line to the RAS5 line, respectively. Each of these RAS decode circuits 51 to 56 checks the match / mismatch between the DRAM logical address (MA31: 02) and the corresponding decode condition, and when they match, the corresponding RAS line is energized and controlled at a predetermined timing. In this case, the 30-bit DRAM logical address (M
A31: 02) It is not necessary to look at all bit values, and MA26, MA25, MA2 can be selected according to conditions such as the type of DRAM bank to be supported and the maximum DRAM logical address space.
4, MA23, MA22, MA21, fly, MA1
Only 9 bits of 3, MA12 and MA11 are used for decoding.

Since the RAS decode circuits 51 to 56 have the same circuit structure, the circuit structure of the RAS decode circuit 51 will be described here as a representative.

The RAS decode circuit 51 includes a RAS set register 61, a RAS mask register 62, nine match / mismatch detection circuits 71 to 79, and nine mask circuits 71 to 71.
79 and an AND circuit 91.

The RAS set register 61 is used by the CPU 11
Is an I / O register that can be read / written by
A bit string indicating the decoding condition of the RAS0 line is set here. For example, the decoding condition of the RAS0 line is shown in FIG.
If it is decided as “00100X XX
1 ″ is set in the RAS set register 61 as the decoding condition of the RAS0 line. Here, X means a bit value (Don't Care) not related to the decoding condition.

The RAS mask register 62 is used by the CPU 11
Is an I / O register that can be read / written by
Here, mask data that specifies whether or not the determination result of the match / mismatch between the decode condition of the RAS0 line and the DRAM logical address is masked for each bit (“0” = masked, “1” = not masked). Is set. Here, masking means that the determination result of the bit is always matched regardless of the determination result of the corresponding 1 bit of the bit string of the decoding condition. Therefore, when “00100X XX1” is set as the decoding condition in the RAS set register 61 as described above, the mask data “111110 001” is set in the RAS mask register 62. As a result, the "X" bit in the decoding condition "00100X XX1" can be excluded from the decoding condition.

The match / mismatch detection circuits 71 to 79 detect the match / mismatch between the bits corresponding to the DRAM logical address and the decoding condition, respectively. Each of these match / mismatch detection circuits 71 to 79 can be realized by an exclusive OR gate. Nine mask circuits 71 to 79
Are corresponding match / mismatch detection circuits 71 to 79, respectively.
The detection result output of is masked.

As described above, the RAS decoder 122 is
This can be realized only by the logic for matching / mismatching data corresponding to the data size of 9 bits per RAS line of the book.

Next, referring to FIG. 14, row address /
A specific circuit configuration of the column address multiplexer 123 will be described.

The row address / column address multiplexer 123, as shown in FIG.
1, pattern decoder 202, row address selector 2
03, row address start position switching circuits 204 to 20
7, and row / column address selector 20
8.

The register file 201 is an I / O register group readable / writable by the CPU 11,
Six control parameters corresponding to the RAS0 to RAS5 lines are set here. Each control parameter is a row address start position of the DRAM bank connected to the corresponding RAS line, that is, which bi of the DRAM logical address.
Specifies whether t is the LSB of the row address.

Four bits MA11, MA12, MA13, and MA14 of the DRAM logical address may be used as the row address starting position, depending on the type of DRAM to be supported and the conditions of page interleaving. Each control parameter is composed of 4-bit data designating one of these four types of row address start positions. The control parameter "0001" specifies MA11, "0010" is MA12, and "0011" is MA.
13, MA0 is designated as "0100".

One of the six control parameters set in the register file 201 is the pattern decoder 20.
2 is read. Which control parameter is read is determined by the decoding result output of the RAS decoder 122. For example, R by the RAS decoder 122
When the AS0 line is activated, the control parameter corresponding to the RAS0 line is read from the register file 201.

The pattern decoder 202 decodes the control parameter read from the register file 201, and generates a selection signal for causing the selector 203 to select one of four kinds of row addresses according to the decoding result.

Row address start position switching circuit 204
Is M from the DRAM logical address MA31: 02).
1 with A11 as the row address start position (LSB)
One bit (MA21, ..., MA11) is taken out as a row address (RA10: 0). Similarly, the row address start position switching circuit 205 extracts a total of 11 bits (MA22, ..., MA12) with MA12 as the LSB, and the row address start position switching circuit 206 outputs MA.
A total of 11 bits with 13 as the LSB (MA23, ...,
MA13) is taken out, and the row address start position switching circuit 207 takes out a total of 11 bits (MA24, ..., MA14) with MA14 as the LSB as a row address.

These row address start position switching circuits 204 to 207 are composed of, for example, barrel shifters.

The row address selector 203 outputs 4 from the row address start position switching circuits 204 to 207 according to the selection signal from the pattern decoder 202.
One of the row addresses of the types is selected and output. The row address selected by the row address selector 203 is supplied to the row address / column address selector 208. A column address is also supplied to the row address / column address selector 208. As the column address, the lower 11 bits (MA12, ... MA02) of the DRAM logical address are always used.

Row address / column address selector 2
08 outputs the row address and the column address selectively onto the memory address bus 33 at the timing designated by the control signal from the timing control circuit 125 of FIG.

In row address / column address multiplexer 123, row address cutout operations by row address start position switching circuits 204 to 207 are performed in parallel with the decoding operation of RAS decoder 122. When the decoding result of the RAS decoder 122 is confirmed, one control parameter corresponding to the RAS line to be energized designated by the confirmed decoding result is read from the register file 201 and sent to the pattern decoder 202. . Then, the decoding operation by the pattern decoder 202 and the row address selecting operation of the row address selector 203 are executed according to the control parameters, whereby the row address to be used for DRAM access is determined.

Although it has been described here that all 11 bits of the row address (RA10: 0) are switched according to the RAS line by the row address start position switching circuits 204 to 207 and the row address selector 203, in reality, all of them are switched. It is not necessary to switch the row address bits of.

That is, the row address start position is MA1.
In any case of 1, MA12, MA13, and MA14, the 6 bits of MA14 to MA19 are commonly used, and therefore these bits can be excluded from the switching target. An example of the correspondence between the CPU address and the row address in this case is shown in FIG.

In FIG. 15, the lower 3 bits of the row address
Bits (RA2 to RA0) and upper 2 bits (RA10,
Only RA9) is the target of switching. By doing this, the 6 bits of MA14 to MA19 of the CPU address are set to the middle 6 bits of the row address (RA8 to RA3).
Can be directly sent to the row address / column address selector 208 as a row address start position switching circuit 204 to 207 and the row address selector 2.
03 can be realized only by the hardware configuration of 5 bits to be switched.

As described above, the circuit configuration of the row address / column address multiplexer 123 of FIG. 14 can significantly reduce the number of circuits required. But,
From the determination of the decoding result of the RAS decoder 122 to the determination of the row address to be used for DRAM access, the operation of the three circuit blocks (the operation of selecting and reading the control parameter to be used from the register file 201, the pattern) It is necessary to sequentially perform the decoding operation by the decoder and the row address selection operation by the row address selector 203). Therefore, the row address /
There is a problem that a relatively large delay occurs in the column address multiplexer 123.

FIG. 16 shows a second circuit configuration example of the row address / column address multiplexer 123. The configuration of FIG. 16 is improved as follows to reduce the delay in the row address / column address multiplexer 123.

That is, in the row address / column address multiplexer 123 of FIG.
Instead of the pattern decoder 202 and the row address selector 203, the six pattern decoders 202-1 to 202-corresponding to the lines RAS0 to RAS5, respectively.
6 and 6 row address selectors 203-1 and 203-1
03-6 is provided. Pattern decoder 202-
1 to 202-6 control the row address selection operation of the row address selectors 203-1 to 203-6 according to the RAS0 control parameter to the RAS5 control parameter of the register file 201, respectively.

Also, the row address selector 203
-1 to 203-6, the RAS decoder 122 decodes one of six types of row addresses (RAS0 row address to RAS5 row address) obtained by the row address selectors 203-1 to 203-6. A row address selector 209 for selecting according to the result is provided.

In this circuit structure, in parallel with the decoding operation of the RAS decoder 122, row address cutout operations by the row address start position switching circuits 204 to 207 and pattern decoders 202-1 to 202-2 are performed.
02-6 and row address selectors 203-1 to 20-20
The row address selection operation by 3-6 is performed. As a result, the 6 lines corresponding to the RAS0 to RAS5 lines can be provided without waiting for the decoding result of the RAS decoder 122 to be determined.
Type of row address (RAS0 row address to RAS5
Row address) can be generated.

When the decoding result of the RAS decoder 122 is confirmed, the row address selector 209 selects the row address corresponding to the RAS line to be energized which is designated by the confirmed decoding result.

Therefore, the circuit operation required from the determination of the decoding result of the RAS decoder 122 to the determination of the row address to be used for DRAM access is only the address selection operation by the address selector 209 at the final stage, The internal delay is greatly reduced.

In the structure of FIG. 16 as well, FIG.
As in the case of 4, it is not necessary to switch the bits of all row addresses.

FIG. 17 shows a specific circuit configuration of the page hit determination circuit 126 shown in FIG.

The page hit determination circuit 126 includes a register file 301, a page hit determination CPU address register 302, and a match determination circuit 30 as shown in the figure.
3, a mask circuit 304, and a match determination mask position register 305 are provided.

The register file 301 is an I / O register that is readable / writable by the CPU 11 and specifies whether or not the matching condition with the CPU address used for page hit determination is masked. Mask data (“0” = masked, “1” = not masked) is set as a control parameter corresponding to each of the RAS0 to RAS5 lines.

That is, in page hit determination, the CPU
Of the addresses (A31: 02), the remaining addresses excluding the in-page address, that is, the row address (page address) excluding the portion corresponding to the column address
And the RAS decoding address is the target. Since the part corresponding to the column address does not participate in page hit judgment, it is necessary to mask the judgment result for each bit used as the column address with mask data. Here, masking means that the determination results of the corresponding bits are always matched.

Actually, the mask data corresponding to each RAS line is not all bits of the column address, but A12,
Each of A11 and A10 is composed of 3-bit data indicating whether to mask or not. this is,
The match determination circuit 303 excludes bits lower than A10, which are always used as column addresses, regardless of the type of DRAM bank, from the match determination, and sets only higher bits after A10 as the target of the match determination. This is because each of the three bits A12, A11, and A10 is configured to be used as a part of the column address or not depending on the type of DRAM bank.

For example, a DRAM of type 1 on the RAS0 line
When a bank (the number of column address bits = 9 bits) is connected, only A10 among the three bits A12, A11, and A10 is used as a part of the column address. At this time, the mask data “110” corresponding to the RAS0 line is set in the register file 301.
One of the six mask data set in the register file 301 is read from the register file 301 and set in the match determination mask position register 305. Which mask data is read depends on RA
It is determined by the decoding result output of the S decoder 122. For example, when the RAS 0 line is energized by the RAS decoder 122, the mask data corresponding to the RAS 0 line is read from the register file 301.

The page hit determination CPU address register 302 holds 17 bits A26 to A11 of the CPU address (A31: 02) at the time of the previous memory access as a page hit determination CPU address. This page hit determination CPU address register 3
The contents of 02 are updated according to the CPU address (A31: 02) used in the memory access at that time when a bank miss or page miss occurs without a page hit. That is, when a bank miss or page miss occurs, the timing control circuit 125 generates a register update signal. In response to this register update signal, the C output on the CPU address bus at that time
The PU addresses (A26 to A11) are latched in the page hit determination CPU address register 302. As a result, the page hit determination CPU address register 3
The content of 02 is changed to the CPU address at the time of the memory cycle in which the bank miss or page miss occurs.

The coincidence determination circuit 303 compares the CPU address (A26 to A11) at the time of this memory access with the CPU address (A26 to A11) held in the page hit determination CPU address register 302 bit by bit. It is a comparator and outputs 17-bit data indicating the detection results of A26 to A11.

The mask circuit 304 masks the detection result outputs of A12, A11, and A10 among the detection results of A26 to A11 in accordance with the mask data of the match determination mask position register 305, and outputs all the detection results after masking. A page hit signal HIT is generated when a match is shown.

The match determination mask position register 305 stores
Mask data corresponding to the RAS line to be energized is set. The contents of the match determination mask position register 305 are updated to the mask data corresponding to the RAS line activated by the RAS decoder 122 when a bank miss or page miss occurs without a page hit. That is, when a bank miss or page miss occurs, the timing control circuit 125 generates a register update signal. In response to the register update signal, the mask data in the register file 301 selected by the RAS decoder 122 at that time is latched in the match determination mask position register 305. As a result, the contents of the match determination mask position register 305 are changed to the mask data corresponding to the RAS line activated at the memory cycle in which the bank miss or page miss occurs.

According to the page hit determination circuit 126 configured as described above, not the DRAM logical address but the CP
Using the U address, page hit determination is performed to determine whether or not the memory access this time is in the same bank and the same page as the previous memory access. The CPU address can be used for the page hit determination because, as described above, the unit of address conversion from the CPU address to the DRAM logical address by the address conversion circuit 121 is set to a value equal to or larger than the page size of the DRAM bank. Because. Therefore, the address translation operation and the page hit determination operation can be performed in parallel, the page hit determination can be performed at high speed, and the memory access speed can be increased.

Further, the timing control circuit 125 has a C
A timing control register 125 that can be read / written by the PU 11 is provided. The RAS of the RAS decoder 122 is stored in the timing control register 125a.
The information designating the decode timing and the information designating the page hit determination timing of the page hit determination circuit 126 are set, and the operation timings of the RAS decoder 122 and the page hit determination circuit 126 are determined according to the setting information.

Normally, the operation timing of these RAS decoder 122 and page hit determination circuit 126 is CP
Since it is fixedly determined by the delay of the address of U11, the clock of the bus, the process of the circuit used, etc., a design change is required whenever these conditions change. However, in this embodiment, since the operation timings of the RAS decoder 122 and the page hit determination circuit 126 can be changed by setting by software, it is not necessary to change the design even if the condition affecting the timing changes.

In addition, the timing control circuit 125 considers the case where a page hit should not be made even if the addresses match, such as when a refresh cycle comes in between. Is configured to be able to manage two states of "page accessible state" and "page inaccessible state". When the current state is the "page inaccessible state", the timing control circuit 125 invalidates the page hit signal.

The "page accessible state" means that the RAS from the previous access is still output.
A state other than the "page accessible state" is the "page inaccessible state". When the system is reset, the page is inaccessible.

After the access by the CPU 11, regardless of whether it is a read or a write, the "page accessible state" is set. The next DRAM access of the CPU 11 in the "page accessible state" is either a page hit, a bank miss or a page miss depending on the address. When a page hits, it can be processed at high speed.
Next CPU1 when in "page inaccessible state"
A DRAM access of 1 results in a bank miss regardless of its address.

The factors causing the "page inaccessible state" are the hold acknowledge HLDA state, DRAM shadow refresh, RAS timeout, and system reset. Therefore, the timing control circuit 125
Is the address strobe ADS signal from the CPU 11,
According to the HLDA signal, the DRAM refresh signal DRAM from the refresh timer, the system reset signal, and the like, two states of "page accessible state" and "page inaccessible state" are managed.

Further, the timing control circuit 125 uses the RAS
It has a built-in time-out circuit, so
S) If the RAS enabled state continues, the "page accessible state" shifts to the "page inaccessible state".

When the current state is the "page inaccessible state", the timing control circuit 125 uses the page hit determination CPU to invalidate the page hit signal.
The memory address value held in the address register 302 may be changed to a value that is not used for DRAM access.

Further, the timing control circuit 125 has a C
In order to support page mode access even when a bus master other than PU11 accesses the DRAM,
It has the following two modes and is configured to change the modes dynamically.

(Mode 1) This mode is based on the assumption that the CPU 11 and another bus master rarely access the same page. In response to the bus master switching, the "page accessible state" is set. Transition to "page inaccessible state" and all RAS
This is a mode in which is disabled. This allows
Precharge time when newly enabling RAS can be saved.

(Mode 2) In this mode, the CPU 11 and another bus master are supposed to access the same page. For example, the case where the CPU 11 immediately reads the data written by the bus master corresponds to this. In this mode, even if the bus master is switched, the RAS remains enabled without transitioning to the "page inaccessible state", so that high-speed access to the same page is possible.

One of these modes may be fixedly used, but if there are many address patterns that may be due to page hits during operation in mode 1, the mode shifts to mode 2, and during operation in mode 2 It is preferable to perform mode switching using the page hit result, such as shifting to mode 1 if there are often no page hits.

The page hit determination circuit 12 shown in FIG.
6, the page hit determination CPU address register 302 specifies the memory address from the CPU and the memory device whose memory attribute information of the memory address area corresponding to the memory address is different between the write access and the read access. Information indicating whether or not the memory access is performed and the cycle type information indicating whether the memory access at that time is a write access or a read access is also held. Retained memory address and CP at this memory access
The coincidence between the memory address from U and the retained cycle type information and the cycle type of the current memory access is added to the page hit determination condition by the coincidence determination circuit 303.

That is, when the memory device to be accessed differs between write access and read access,
The page hit judgment cannot be actually made only by the presence / absence of a match of the memory addresses. In this case, as a result, it takes a long time to determine the page hit, and it is not possible to take advantage of the high-speed page hit determination.

Therefore, as described above, in this embodiment, when the memory device to be accessed differs between the write access and the read access, the cycle type information of write or read is also added to the page hit determination condition. There is. Hereinafter, the configuration for that will be specifically described.

First, referring to FIG. 18, the CPU 11 managed by the memory area attribute table 127 of FIG.
The relationship between the memory address space of and the memory attribute information will be described.

The size of one address area managed by the memory area attribute table 127 is 16 Kbytes, and as shown in FIG. 18, the CPU memory address space is 00000000H to 0000FFFFH.
Is AREA00-AREA6 in order from 000000H
Defined as 3.

Of these AREA00 to AREA63,
8-bit attribute information as shown in FIG. 19 is set in each attribute register corresponding to AREA40 to AREA63 in which a plurality of types of memory devices including DRAM may be arranged. As shown in FIG. 19, of the 8-bit attribute information, 2 bits of bit7 and bit6 are read attribute information (READ ATTRIBU).
TE), 2 bits of bit5 and bit4 are write attribute information (WRITE ATTRIBUTE), and bit3 is D.
RAM write protect information (WP), bit2 and bi
2 bits of t1 are used as caching control information (CASH).

Read attribute information (READ ATTRIB
UTE) indicates the type of memory device to be read-accessed, and as shown in FIG. 20, by the combination of 2 bits of bit7 and bit6, DRAM, memory on the VL bus, PCI bus , Or the memory on the ISA bus is designated.
Write attribute information (WRITE ATTRIBUTE)
Indicates the type of memory device to be write-accessed, and as shown in FIG.
DRA is determined by the combination of 2 bits of 5 and bit 4.
M, memory on VL bus, memory on PCI bus, IS
One of the memories on the A bus is designated.

DRAM write protect information (WP)
22 indicates that the DRAM is specified as the memory device for the write access by the write attribute information.
As shown in, DRA depends on the contents of bit3.
Indicates whether or not write protection for M is performed.

The caching control information (CASH) is both DRA according to the read attribute information and the write attribute information.
When M is specified, it is for controlling the validity / invalidity of the caching operation of the RAM, and as shown in FIG. 23, the write is performed by the combination of 2 bits of bit2 and bit1. One of back cache enable, write through cache enable, and cache disable is designated. For example, VG
DR in which A BIOS and system BIOS are copied
For the AM area, the cache disable setting is made.

The page hit determination CPU address register 302 is loaded with the memory address from the CPU 11 together with the memory attribute information of the memory address area corresponding to the memory address from the memory area attribute table 127. The information indicating whether or not different memory devices are designated by and the cycle type information indicating whether the memory access at that time is a write access or a read access are held together. When the memory device to be accessed differs between write access and read access, the held memory address matches the memory address from the CPU at the time of this memory access, and the held cycle type information and this time The coincidence with the memory access cycle type is added to the page hit determination condition by the coincidence determination circuit 303.

Therefore, the memory attribute can be determined at high speed, and high-speed memory access that makes use of high-speed page hit determination can be realized.

Further, in addition to the above-mentioned information, the page hit determination CPU address register 302 stores D in the memory address area corresponding to the memory address from the CPU.
It is desirable to further hold the RAM write protect information (WP) and the caching control information (CASH). As a result, the page hit determination is made and at the same time, the type of cycle to be executed next can be determined.

That is, when it is determined that there is a page hit, at the same time, the cycle type is determined as follows.

1. Write page hit non-protect This is a cycle executed when the current memory access cycle is a write cycle and the held write protect information indicates non-write protect. Run in mode.

2. Write page hit protect This is a cycle executed when the current memory access cycle is a write cycle and the held write protect information indicates write protect, and CAS is not asserted. By this, write protection is realized.

3. Read page hit single This is a cycle executed when the current memory access cycle is a read cycle and the held cache control information indicates that the cache is invalid. The read cycle for reading data from the DRAM is Executed once in page mode.

4. Read page hit burst This is a cycle executed when the current memory access cycle is a read cycle and the held cache control information indicates that the cache is valid. The burst read cycle to read is executed in page mode.

Here, the write protect information and the cache control information are the same when the RAS is reissued for the page due to a bank miss or a page miss.
It is recorded together with the CPU address for page hit determination. This is because waiting for the decoding result of the write protect information and the cache control information will not be in time for the page hit confirmation time.

Therefore, the write protect information in the read cycle and the cache control information in the write cycle also have meaning.

If there is no page hit,
When a bank miss or a page miss is determined and the bank miss is determined, at the same time, the cycle type is determined as follows.

1. Write bank miss non-protection This is a cycle executed when the current memory access cycle is a write cycle and the write protect information corresponding to the current memory address indicates non-write protection. RAS for the bank is asserted, and the data write is executed by the early write.

2. Write bank miss protect This is a cycle executed when the current memory access cycle is a write cycle and the write protect information corresponding to the current memory address indicates write protect, and CAS is not asserted. Without this, write protection is realized.

3. Read bank miss single This is a cycle executed when the current memory access cycle is a read cycle and the cache control information corresponding to the current memory address indicates that the cache is invalid. R
AS is asserted and one read cycle for reading data from the DRAM bank is executed.

4. Read bank miss burst This is a cycle executed when the current memory access cycle is a read cycle and the cache control information corresponding to the current memory address indicates that the cache is valid. R
After AS is asserted, a burst read cycle for reading a plurality of consecutive data from the DRAM bank is executed.

Here, the write protect information and cache control information are decode signals defined for the page accessed this time, and are recorded together with the CPU address for page hit determination for the subsequent accesses. It

When a page miss is determined, at the same time, the cycle type is determined as follows.

1. Write page miss non-protection This is a cycle executed when the memory access cycle this time is a write cycle and the write protect information corresponding to the memory address this time indicates non-write protection. RAS for is re-asserted, and the data write is executed by the early write.

2. Write page miss protect This is a cycle executed when the current memory access cycle is the write cycle and the write protect information corresponding to the current memory address indicates the write protect, and CAS is not asserted. Without this, write protection is realized.

3. Read page miss single This is a cycle executed when the current memory access cycle is a read cycle and the cache control information corresponding to the current memory address indicates that the cache is invalid.
AS is reasserted and one read cycle for reading data from the DRAM bank is executed.

4. Read page miss burst This is a cycle executed when the current memory access cycle is the read cycle and the cache control information corresponding to the current memory address indicates that the cache is valid.
After AS is reasserted, a burst read cycle for reading a plurality of consecutive data from the DRAM bank is executed.

Here, the write protect information and the cache control information are decode signals defined for the page accessed this time, and are recorded together with the CPU address for page hit determination for the subsequent accesses. It

As described above, according to this embodiment, the page hit determination circuit 126 uses the CPU address instead of the DRAM logical address so that the current memory access is in the same bank and same page as the previous memory access. A page hit determination is performed to determine whether or not Therefore, the address translation operation and the page hit determination operation can be performed in parallel, the page hit determination can be performed at high speed, and the memory access speed can be increased.

By storing the memory attribute information together with the CPU address for page hit determination,
It is possible to determine the page hit at a higher speed and determine the next cycle type.

[0208]

As described above, according to the present invention, page hit determination can be executed at high speed.
The memory access speed can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a memory control logic in a system controller provided in the system of the embodiment.

FIG. 3 is a diagram showing a conversion operation from a CPU memory address space to a DRAM logical address space, which is executed by an address conversion circuit included in the memory control logic of FIG.

FIG. 4 shows a plurality of Ds provided in the system of the embodiment.
The figure which shows the DRAM memory map showing the state where the RAM bank was rearranged in the DRAM logical address space in order of memory size.

FIG. 5 shows a plurality of Ds provided in the system of the embodiment.
The figure which shows the decoding condition of each RAS line connected to a RAM bank.

FIG. 6 is a diagram showing decoding conditions of each RAS line adopted when realizing a page interleave architecture in the system of the embodiment.

FIG. 7 is an exemplary flowchart showing the procedure of an initialization process for the memory control logic executed by the IRT routine when the system of the embodiment is powered on.

FIG. 8 is a DRAM supported by the system of the embodiment.
The figure which shows an example of the kind of bank.

FIG. 9 is a diagram showing an example of a memory configuration of a system memory standardly mounted on the system board of the system of the embodiment.

FIG. 10 is a diagram showing an example of a memory configuration of an extension memory installed in an extension memory slot provided in the system of the embodiment.

FIG. 11 is a diagram showing an example of another memory configuration of the additional memory mounted in the expansion memory slot provided in the system of the embodiment.

12 is a flowchart showing the procedure of a memory size detection process for each DRAM bank, which is executed in the initialization process of the memory control logic of FIG. 7.

FIG. 13 is a RAS included in the memory control logic of FIG.
FIG. 6 is a circuit diagram showing an example of a specific configuration of a decoder.

14 is a circuit diagram showing an example of a specific configuration of a row address / column address multiplexer included in the memory control logic of FIG.

15 is a diagram for explaining a row address switching operation of the row address / column address multiplexer in FIG.

16 is a circuit diagram showing another example of a specific configuration of a row address / column address multiplexer included in the memory control logic of FIG.

FIG. 17 is a circuit diagram showing an example of a specific configuration of a page hit determination circuit included in the memory control logic of FIG.

FIG. 18 is an exemplary view showing a relationship between memory attribute information managed by the system of the embodiment and a CPU memory address space.

FIG. 19 is a diagram showing a format of memory attribute information of FIG. 18;

20 is a diagram showing the content of read attribute information included in the memory attribute information of FIG. 18;

FIG. 21 is a diagram showing the contents of write attribute information included in the memory attribute information of FIG. 18;

FIG. 22 is a DRAM included in the memory attribute information of FIG. 18;
The figure which shows the content of the write protect information.

23 is a diagram showing the content of caching control information included in the memory attribute information of FIG. 18;

[Explanation of symbols]

11 ... CPU, 12 ... System controller, 13 ... System memory, 21, 22 ... Expansion memory slot, 31
... CPU local bus, 33 ... Memory address bus, 4
1, 42 ... Expansion memory, 120 ... Memory control logic,
121 ... Address conversion circuit, 122 ... RAS decoder,
123 ... Row address / column address multiplexer, 124 ... CAS generation circuit, 125 ... Timing control circuit, 126 ... Page hit determination circuit, 51-56 ... R
AS decode circuit, 71 to 79 ... Match detection circuit, 81 to
89 ... Mask circuit, 91 ... AND circuit, 201, 301
... register file, 202 ... pattern decoder, 20
3 ... Row address selector, 204 to 207 ... Row address start position switching circuit, 208 ... Row address / column address selector, 302 ... Page hit determination C
PU address register, 303 ... Match determination circuit, 304
... mask circuit, 305 ... match determination mask position register.

Claims (7)

[Claims] 1. A plurality of DRAM banks to which a plurality of RAS signals are respectively assigned and which can be accessed independently of each other, and memory addresses from a CPU are converted into memory addresses from a CPU in a conversion unit of a page size of these DRAM banks or more.
Address conversion means for converting to a DRAM logical address continuously assigned to M banks, and a memory address from the CPU at the time of the last memory access is held, and the memory address and the memory address from the CPU at the time of this memory access And a page hit determination unit that outputs a page hit signal indicating that the current memory access is in the same bank and the same page as the previous memory access when they match, and the DRAM logic output from the address conversion unit. A RAS decoder that decodes an address and determines which RAS signal of the DRAM bank is to be output, wherein the RAS decoder performs RAS signal output control for DRAM page mode access when the page hit signal is output. And comprising Mori control system. 2. A page accessible state in which DRAM page mode access is possible and a page inaccessible state in which DRAM page mode access is not possible according to the hold acknowledge cycle, DRAM refresh cycle, RAS timeout or system reset of the CPU. 2. The memory control system according to claim 1, further comprising means for managing the two states, and invalidating the page hit signal when the current state is the page inaccessible state. 3. For each of a plurality of memory address areas forming a memory address space addressable by the CPU, information specifying the type of memory device to which read access is permitted and the type of memory device to which write access is permitted. Further comprising a memory attribute table in which memory attribute information including information designating a memory area is defined, and the page hit determination means is a memory address corresponding to the memory address from the CPU at the time of the last memory access. Information indicating whether the memory attribute information of the address area specifies different memory devices for write access and read access, and cycle type information indicating whether the memory access at that time is write access or read access Hold When the memory device to be accessed differs between the write access and the read access, the held memory address matches the memory address from the CPU at the time of the current memory access, and the cycle type information is held. 2. The page hit signal is output on condition that the cycle type of the current memory access matches.
The described memory control system. 4. The write protection information indicating whether or not write protection is performed for each of a plurality of memory address areas forming a memory address space addressable by the CPU, and whether or not a caching operation using a cache memory is valid. Further comprising a memory attribute table defining memory attribute information including cache information indicating whether the page hit determination means corresponds to the memory address from the CPU at the time of the last memory access together with the memory address. 2. The memory attribute information of the memory address area is held, and the type of cycle to be executed next is determined based on the page hit determination result and the held memory attribute information. The described memory control system. 5. A register configured to be programmable by the CPU, in which timing designation information for designating operation timing of each of the page hit determination means and the RAS decoder is set, the page hit determination means and the RAS. 2. The memory control system according to claim 1, wherein the operation timing of each decoder can be changed by setting by software. 6. A page accessible state in which DRAM page mode access is possible and a page inaccessible state in which DRAM page mode access is not possible according to the hold acknowledge cycle, DRAM refresh cycle, RAS timeout, or system reset of the CPU. And the current state is the page inaccessible state, the memory address value held in the page hit determination means is changed to DRA.
The memory control system according to claim 1, further comprising means for changing to a value that is not used for M access. 7. A page accessible state in which DRAM page mode access is possible and a page inaccessible state in which DRAM page mode access is not possible according to the hold acknowledge cycle, DRAM refresh cycle, RAS timeout or system reset of the CPU. All the R's of the RAS decoder for invalidating the page hit signal when the current state is the page inaccessible state.
State management means for disabling the AS signal output, wherein when the bus master accessing the DRAM bank switches between the CPU and another bus master other than the CPU, the page access is possible in response to the switching of the bus master. Has a first mode in which the state transits to a page inaccessible state and a second mode in which the state does not transit,
The state management means configured to selectively use the two modes is further provided.
The described memory control system.