JP3614956B2 - Memory control system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory control system, and more particularly to an improved memory control system for efficiently accessing a DRAM bank used as a main memory of a personal computer.
[0002]
[Prior art]
In recent years, various notebook-type or laptop-type portable personal computers that can be easily carried and operated by a battery have been developed. In this type of personal computer, it is desired to increase the operation speed, and recently, a high-performance microprocessor incorporating a large-scale cache has begun to be used as a CPU.
[0003]
When a microprocessor with a built-in cache is used as a CPU, the number of accesses to the main memory can be reduced, and the system operation performance can be improved to some extent.
[0004]
However, even if the CPU has a built-in cache, access to the main memory is not lost, and when a cache miss occurs, the CPU needs to execute a memory read / write cycle for the main memory. Therefore, in practice, in order to improve the system performance, it is indispensable to increase the execution speed of the memory read / memory write cycle by the CPU.
[0005]
As a main memory of a personal computer, a dynamic RAM (DRAM) is usually used. DRAM is characterized by low access speed but low cost compared to static RAM (SRAM). In order to solve this problem, in addition to improvements at the semiconductor technology level such as improvement of the DRAM chip itself, improvements at the memory architecture level by adopting page mode access, interleave control, etc. have been promoted recently.
[0006]
In order to perform these page mode access and interleave control, the memory control system normally incorporates logic for performing page hit determination. The page hit determination is to determine whether or not the memory access address generated by the CPU is obtained in the same page of the same DRAM bank as the access performed immediately before in the DRAM page mode access method. If they are the same page, high-speed access that does not require re-out of RAS (row address strobe) is possible.
[0007]
In a conventional memory control system, conversion from a CPU address to a DRAM logical address is performed first, then a DRAM bank to be accessed is selected, and the selected DRAM bank is accessed immediately before. Is checked by the RAS decoder. If they are the same bank, the row hit to the selected DRAM bank is compared with the row address of the previous access by the page hit determination circuit, and page hit determination is performed.
[0008]
[Problems to be solved by the invention]
As described above, conventionally, before page hit determination is performed, processing such as address translation and RAS decoding is required, and as a result, there is a problem that page hit determination takes time. For this reason, even when a page hit occurs, a wait cycle is required, and sufficient high-speed access cannot be realized.
[0009]
The present invention has been made in view of these points, and an object of the present invention is to provide a memory control system which can execute page hit determination at high speed and can realize high memory access speed.
[0010]
[Means for Solving the Problems]
In the memory control system according to the present invention, a plurality of DRAM banks to which a plurality of RAS signals are respectively assigned and accessed independently from each other, and a plurality of DRAM banks arranged discontinuously in the memory address space of the CPU are respectively provided. Address conversion means for converting a memory address from the CPU into a DRAM logical address in a conversion unit equal to or larger than the page size of the plurality of DRAM banks so that corresponding memory areas are continuously arranged in the DRAM logical address space. And the memory address from the CPU at the time of the previous memory access, and the memory address is compared with the memory address from the CPU at the time of the current memory access. Same bank and same page A page hit determining means for outputting a page hit signal indicating that, and a DRAM logical address output from the address converting means to determine which DRAM bank to output a RAS signal, A RAS decoder for performing RAS signal output control for DRAM page mode access when the page hit signal is output; , For each of a plurality of memory address areas constituting a memory address space addressable by the CPU, information for designating the type of memory device to which read access should be permitted and information for designating the type of memory device to which write access should be permitted A memory attribute table in which memory attribute information including The page hit determination means includes means for holding control information that is set by the CPU and that specifies a bit position in the memory address to be used for page hit determination for each DRAM bank; Means for changing a bit position in the memory address to be used for the page hit determination based on a decoding result of the RAS decoder and the control information. Whether the memory attribute information in the memory address area corresponding to the memory address together with the memory address from the CPU at the previous memory access designates a different memory device for write access and read access. Cycle type information indicating whether the memory access at that time is a write access or a read access. If the memory device to be accessed differs between the write access and the read access, the stored memory The page hit signal is output on condition that the address matches the memory address from the CPU at the time of the current memory access, and the cycle type information held matches the cycle type of the current memory access. It is characterized by that.
[0011]
In this memory control system, page hit determination means determines whether or not the current memory access is the same bank and the same page as the previous memory access by using the CPU address instead of the DRAM logical address. A determination is made. The CPU address can be used for page hit determination because the unit of address conversion from the CPU address to the DRAM logical address is set to a value equal to or larger than the page size of the DRAM bank. As a result, even if the DRAM logical address specifies the same page for the previous access and the current access, a page with a different CPU address is not specified. Therefore, the address translation operation and the page hit determination operation can be performed in parallel, the page hit determination can be performed at high speed, and the memory access speed can be increased.
[0012]
The page hit determination means designates a memory device in which the memory attribute information in the memory address area corresponding to the memory address is different between write access and read access together with the memory address from the CPU at the previous memory access. Information indicating whether or not the memory access is being performed and cycle type information indicating whether the memory access at that time is a write access or a read access, and the memory device to be accessed differs between the write access and the read access The page is subject to the condition that the held memory address matches the memory address from the CPU at the time of the current memory access, and the cycle type information being held matches the cycle type of the current memory access. Configured to output hit signal Rukoto is preferable.
[0013]
As a result, even when the memory devices to be accessed are different between the write access and the read access, the memory attribute can be determined at high speed, and high-speed memory access utilizing high-speed page hit determination is possible.
[0014]
Further, as memory attribute information, the write protect information indicating whether or not the write protection is performed and the cache information indicating whether or not the cache operation using the cache memory is valid are held together with the memory address in the page hit determination unit. Thus, the cycle to be executed next can be determined efficiently.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a computer system to which a memory control system according to an embodiment of the present invention is applied.
[0016]
This computer system is for realizing a notebook type or laptop type portable personal computer. On a system board 10, as shown in the figure, a CPU 11, a system controller 12, a system memory 13, a BIOS ROM 14, a real time A clock (RTC) 15, an interrupt controller (PIC) 16, a keyboard controller (KBC) 17, a display controller 18 and the like are mounted.
[0017]
On the system board 10, a CPU local bus (sometimes referred to as a processor bus) 31, a system bus 32 having specifications such as ISA / EISA / PCI, a memory address bus 33, and the like are disposed.
[0018]
Furthermore, this system is provided with two expansion memory connectors 21 and 22 for connecting an additional memory. FIG. 1 shows a state in which expansion memories 41 and 42 are connected to the expansion memory connectors 21 and 22, respectively.
[0019]
The expansion memories 41 and 42 are optional memories that are installed as necessary by the user to expand the system memory size, and are configured from, for example, a DRAM card, a DIMM or a SIMM memory module, or the like. These additional memories are usually composed of one or more DRAM banks.
[0020]
The CPU 11 is a microprocessor incorporating a large-scale cache memory, and is connected to the system controller 12 via a CPU local bus 31. The CPU local bus 31 is a signal group directly connected to the input / output pins of the microprocessor constituting the CPU 11. This includes a 32-bit data bus, a 32-bit address bus, and various status signal lines.
[0021]
The system controller 12 is connected between the CPU local bus 31 and the system bus 32, and controls all memories and I / O devices in the system in response to a request from the CPU 11. The system controller 12 is realized by one LSI constituted by a gate array, and a memory control logic lock for controlling the DRAM of the system memory 13 and the additional memories 41 and 42 is incorporated therein. .
[0022]
The system memory 13 is used as a main memory of this system, and is usually composed of one or more DRAM banks. The system memory 13 stores an operating system, an application program to be executed, various processing data, and the like.
[0023]
The system memory 13 is mounted on the system board 10 via a predetermined connector or directly. The system memory 13 is a 32-bit memory device, and its data port is connected to the 32-bit data bus of the CPU local bus 31, and the address input port is connected to the memory address bus 33. The memory address bus 33 is an address bus dedicated to the DRAM, and a physical address (row address / column address) of the DRAM is output from the system controller 12 on the memory address bus 33.
[0024]
Similarly, each of the expansion memories 41 and 42 is a 32-bit memory device, and its data port is connected to the 32-bit data bus of the CPU local bus 31 via the corresponding connectors 21 and 22, and the address input port is a memory address. It is connected to the bus 33.
[0025]
Further, two row address strobe signal lines (RAS lines: RAS0, RAS1) are connected to the system memory 13. Similarly, another two row address strobe signal lines (RAS lines: RAS2, RAS3) are connected to the expansion memory connector 21, and another two row address strobe signal lines (RAS) are also connected to the expansion memory connector 22. Lines: RAS4, RAS5) are connected.
[0026]
Further, a column address strobe signal line (CAS line) and other various control signal lines (write enable signal line WE, output enable signal line OE, etc.) are commonly connected to the system memory 13 and the additional memories 41 and 42, respectively. Has been.
[0027]
All DRAM banks in the system memory 13 and the additional memories 41 and 42 are arranged in the DRAM memory address space of the CPU 11. In this system, the decoding conditions for each RAS line are simplified, and the interleave arc Tech In order to make the best use of the char, these DRAM banks are arranged at a smaller address as the memory size increases.
[0028]
In the read / write access control of the system memory 13 and the additional memories 41 and 42, one of the RAS lines (RAS0 to RAS5) is set to the active state, and the DRAM bank connected to the active RAS line is the access target. Selected as DRAM bank. Such energization control of the RAS line is executed by the memory control logic of the system controller 12.
[0029]
FIG. 2 shows the configuration of the memory control logic.
[0030]
Memory control logic Reference numeral 120 denotes hardware logic that supports DRAM page mode access and page interleaving, and includes an address conversion circuit 121, a RAS decoder 122, a row address / column address multiplexer 123, a CAS generation circuit 124, a timing control circuit 125, and a page hit. A determination circuit 126 is included.
[0031]
The address conversion circuit 121 converts the CPU address (A31: 02) into a DRAM logical address (MA31: 02). This conversion is performed in order to continuously assign a plurality of DRAM memory areas distributed in the memory address space of the CPU 11 to a logical address space dedicated to DRAM access. An example of this address conversion operation is shown in FIG.
[0032]
That is, as shown in FIG. 3A, the memory address space of the CPU 11 usually includes a video RAM, a BIOS ROM, and various options in addition to a DRAM area such as a system memory area and a PM memory area. A reserved area (0A0000H to 0C0000H) for allocating ROM and the like is secured. The address conversion circuit 121 performs address conversion so that the addresses in the DRAM area immediately before and after the reserved area are continuous according to such a CPU memory map.
[0033]
When the VGA BIOS, system BIOS, etc. stored in the BIOS ROM are copied to the DRAM and used, as shown in FIG. 3B, the VGA BIOS area and the system BIOS area in the reserved area are used. The assigned CPU address is also converted into a DRAM logical address. Further, in the case of a CPU having a system management mode (SMM), a CPU address assigned to an SMRAM area used only in the SMM is also converted into a DRAM logical address.
[0034]
Such conversion from the CPU address to the DRAM logical address is performed in units of 16 Kbytes, for example. Therefore, the lower bit part (MA13: 02) of the DRAM logical address is equal to the lower bit part (A13: 02) of the CPU address even after the address conversion.
[0035]
The DRAM logical address (MA31: 02) obtained by the address conversion circuit 121 is used for addressing a DRAM bank in the system.
[0036]
The RAS decoder 122 decodes the DRAM logical address (MA31: 02) according to the decoding conditions of the RAS0 to RAS5 set in the internal register, and has a decoding condition that the DRAM logical address satisfies in the RAS0 to RAS5 lines. Select a line and activate it. The timing at which the RAS line is activated is controlled by a timing control signal CONT1 from the timing control circuit 125.
[0037]
The decoding operation of the RAS decoder 122 can be performed only by detecting a match / mismatch between the decode condition of each RAS line and the DRAM logical address. How the decoding conditions for each of the RAS0 to RAS5 lines are determined will be described in detail with reference to FIG.
[0038]
The row address / column address multiplexer 123 decomposes the DRAM logical address (MA31: 02) into a row address (RA) and a column address (CA) for addressing a DRAM bank to be accessed. In the internal register of the row address / column address multiplexer 123, a control parameter indicating the start bit position of the row address (RA) of each DRAM bank is set in advance. The operation of decomposing the row address (RA) and the column address (CA) is performed according to the control parameter corresponding to the DRAM bank to be accessed.
[0039]
The row address (RA) and the column address (CA) are output on the memory bus 33 in a time division manner. This output timing is controlled by a timing control signal CONT2 from the timing control circuit 125.
[0040]
The CAS generation circuit 124 controls the energization of the CAS line according to the timing control signal CONT3 from the timing control circuit 125.
[0041]
Taimin G The control circuit 125 controls the operations of the RAS decoder 122, the row address / column address multiplexer 123, and the CAS generation circuit 124 by generating the timing control signals CONT1 to CONT3. The generation operation of the timing control signal is controlled by the page hit signal HIT from the page hit determination circuit 126 or the like.
[0042]
The page hit determination circuit 126 sets the CPU address at the previous DRAM access to the page. hit It is held as a determination CPU address, and the presence or absence of a page hit is determined by comparing the CPU address with the CPU address at the next DRAM access. Here, the page hit means that the next DRAM access accesses the same page in the same DRAM bank as the previous one. When it is determined that a page hit has occurred, this is notified to the timing control circuit 125 by the page hit signal HIT.
[0043]
As described above, the page hit determination operation is performed based on the value of the CPU address, not the DRAM logical address. As a result, the address conversion operation and the page hit determination operation can be performed in parallel. The CPU address can be used for page hit judgment because the unit of address conversion from the CPU address to the DRAM logical address (16 Kbytes) is set to a value larger than the DRAM bank page size (up to about 4 Kbytes). Because. As a result, even if the DRAM logical address designates the same page for the previous access and the current access, the page having a different CPU address is not designated.
[0044]
For the determination of page hit, all upper addresses after the column address in the CPU address (A31: 02) are used. In the conventional method, it is determined whether or not DRAM access, DRAM access Then Contains the address that was used to determine the bank.
[0045]
The number of bits of the column address, that is, the page size is different for each DRAM bank to be accessed. For this reason, a control parameter for designating a bit to be used for page hit determination for each RAS line is set in the internal register of the page hit determination circuit 126 in advance, and the page hit is determined according to the control parameter corresponding to the DRAM bank to be accessed. A determination is made.
[0046]
The DRAM control timing by the memory control logic 120 is classified into cycle timings corresponding to the following three states.
[0047]
(1) Page hit
This means that the current DRAM access accesses the same page in the same DRAM bank as the previous time. In this case, access to the DRAM bank is controlled in the page mode. That is, only the column address and CAS line activation timing are controlled, and the RAS decoder 122 does not switch the RAS line. Further, the RAS line continues to be maintained in the active state even after the previous memory cycle is completed.
[0048]
(2) Bank miss
This means that the current DRAM access accesses a different DRAM bank. In this case, the RAS line is switched by the RAS decoder 122, and the DRAM bank is accessed in a normal DRAM access cycle. Further, the page hit determination CPU address held in the page hit determination circuit 126 is updated.
[0049]
(3) Page miss
This means that the current DRAM access accesses a different page in the same DRAM bank as the previous time. In this case, the RAS line same as the previous RAS line is set again to the active state by the RAS decoder 122, and the DRAM bank is accessed in a normal DRAM access cycle. Further, the page hit determination CPU address held in the page hit determination circuit 126 is updated.
[0050]
Next, the decoding conditions for each RAS line set in the RAS decoder 122 will be described with reference to FIGS.
[0051]
FIG. 4 shows an example of a DRAM memory map in the system. As shown in FIG. 1, in this DRAM memory map, two 2M byte DRAM banks are mounted on the system board 10 as the system memory 13, and one expansion memory 41 of the expansion memory connector 21 is provided. This corresponds to the case where the memory is constituted by 8 Mbyte DRAM banks and the expansion memory 42 of the expansion memory connector 22 is constituted by two 4 Mbyte DRAM banks.
[0052]
In this case, these DRAM banks are arranged in the descending order of memory size, that is, as shown in FIG. 4, an 8M byte DRAM bank, two 4M byte DRAM banks, and two 2M byte DRAM banks in total, 20M bytes. In the DRAM logical address space.
[0053]
In this memory arrangement, an address range of 0 to 8 Mbytes is assigned to the RAS2 line corresponding to the 8 Mbyte DRAM bank. An address range of 8 to 12 Mbytes is assigned to the RAS4 line corresponding to the first 4 Mbyte DRAM bank, and an address range of 12 to 16 Mbytes is assigned to the RAS5 line corresponding to the next 4 Mbyte DRAM bank. Further, an address range of 16 to 18 Mbytes is assigned to the RAS0 line corresponding to the first 2 Mbyte DRAM bank, and an address range of 18 to 20 Mbytes is assigned to the RAS1 line corresponding to the next 2 Mbyte DRAM bank. Since the RAS3 line is not used, no address range is assigned to the RAS3 line.
[0054]
At this time, the decoding conditions for each of the RAS0 to RAS5 lines are determined as shown in FIG.
[0055]
As a decoding condition for each of the RAS0 to RAS5 lines, a bit string that exists in common only for all DRAM logical address values (MA31: 02) belonging to the address range assigned to each RAS line is used.
[0056]
That is, the decoding condition of the RAS2 line is the upper 9 bits (MA31 to 23) of the DRAM logical address value (MA31: 02) = “0000 0000 0”. The lower 21 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of an 8 Mbyte DRAM bank connected to the RAS2 line.
[0057]
The decoding condition of the RAS4 line is the upper 10 bits (MA31 to 22) of the DRAM logical address value (MA31: 02) = “0000 0000 10”. The lower 20 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of a 4 Mbyte DRAM bank connected to the RAS4 line.
[0058]
The decoding condition of the RAS 5 line is the upper 10 bits (MA31 to 22) of the DRAM logical address value (MA31: 02) = “0000 0000 11”. The lower 20 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of a 4 Mbyte DRAM bank connected to the RAS5 line.
[0059]
The decoding condition of the RAS0 line is the upper 11 bits (MA31 to 21) of the DRAM logical address value (MA31: 02) = “0000 0001 000”. The lower 19 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of a 2 Mbyte DRAM bank connected to the RAS0 line.
[0060]
The decoding condition of the RAS1 line is the upper 11 bits (MA31 to 21) of the DRAM logical address value (MA31: 02) = “0000 0001 000”. The lower 19 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of a 2 Mbyte DRAM bank connected to the RAS0 line.
[0061]
As described above, a common bit string belonging to the address range corresponding to each RAS line is used as a decoding condition for each RAS line. For this reason, the RAS decoder 122 described above only needs to detect the coincidence / mismatch between the DRAM logical address value and the decoding condition for each RAS line, and the hardware configuration can be greatly simplified as compared with the conventional case. It becomes possible.
[0062]
Next, decoding conditions for each RAS line when the page interleave architecture is adopted will be described.
[0063]
In the case of page interleaving, the five DRAM banks mapped as shown in FIG. 4 are classified into bank groups capable of page interleaving. Each bank group includes a combination of banks that have adjacent memory address ranges and the same total memory size. Such grouping is performed in order from the youngest DRAM logical address.
[0064]
That is, in the example of FIG. 4, the total memory size of two 4 Mbyte DRAM banks allocated to the address range subsequent to the address range (0 to 8 Mbytes) of RAS2 8 Mbyte DRAM bank is 8 Mbytes. One page interleave group is configured by three banks corresponding to RAS2, RAS4, and RAS5.
[0065]
Since the RAS1 2M byte DRAM bank is allocated to the address range subsequent to the RAS0 2M byte DRAM bank address range (16 to 8M bytes), another page interleave is performed by the two banks corresponding to the RAS0 and RAS1. A group is formed.
[0066]
In this case, the decoding conditions for each RAS line are changed as shown in FIGS.
[0067]
That is, the decoding conditions of RAS2, RAS4, and RAS5 of group 1 are common to all DRAM logical address values (MA31: 02) belonging to the total 16 Mbyte address range (0 to 16 Mbytes) allocated to group 1. An existing bit string and a bit string between a column address (in-page address) and a row address (page address) of a DRAM bank corresponding to each of RAS2, RAS4, and RAS5 are used.
[0068]
That is, as shown in FIG. 6, in the address range of a total of 16 Mbytes allocated to RAS2, RAS4, and RAS5, the upper 8 bits (MA31-24) of the DRAM logical address value (MA31: 02) = “0000 0000” is It exists in common and does not exist in group 2. Therefore, (MA31 to 24) = “0000 0000” is used as a common decoding condition for RAS2, RAS4, and RAS5.
[0069]
For RAS2, the start position of the row address in the DRAM logical address is shifted left by 1 bit, and 1 bit (MA12) = “0” between the row address and the column address of the 8-Mbyte DRAM bank corresponding to RAS2 is decoded. Added as a requirement.
[0070]
For each of RAS4 and RAS5, the start position of the row address in the DRAM logical address is shifted by 2 bits to the left, and 2 bits (MA13, 12) between the row address and the column address of the corresponding 4M-byte DRAM bank. A value is added as an address condition. Two bits are used because the memory sizes of RAS4 and RAS5 are half of the memory size of RAS2.
[0071]
That is, for RAS4, 2 bits (MA13, 12) = “01” between the row address and the column address of the 4 Mbyte DRAM bank corresponding to RAS4 are added as a decoding condition, and RAS5 corresponds to RAS5. 2 bits (MA13, 12) = “11” between the row address and the column address of the 4 Mbyte DRAM bank to be added are added as an address condition.
[0072]
When the decoding conditions of RAS2, RAS4, and RAS5 are determined in this way, an even page (0, 2, 4, 6,...) In the address range of 0 to 16 Mbytes is allocated to the 8 Mbyte DRAM bank of RAS2. , RAS4 4M byte DRAM bank is assigned a part of odd pages (1, 5, 9,...) In the 0-16M byte address range, and RAS5 4M byte DRAM bank is 0-16M byte. The remaining odd pages (3, 7, 11,...) In the address range are assigned.
[0073]
Therefore, when continuous access is performed in the range of 0 to 16 Mbytes, the three DRAM banks are alternately accessed in page units in the order of RAS2, RAS4, RAS2, RAS5, RAS2,.
[0074]
On the other hand, the decoding conditions of RAS0 and RAS1 of group 2 are as follows.
[0075]
That is, the decoding conditions for RAS0 and RAS1 are as follows: a bit string that is commonly present in all DRAM logical address values (MA31: 02) belonging to the total 4 Mbyte address range (16 to 20 Mbytes) allocated to group 2; A bit string between a column address and a row address of a DRAM bank corresponding to each of RAS0 and RAS1 is used.
[0076]
In the address range of a total of 4 Mbytes assigned to RAS0 and RAS1, the upper 10 bits (MA31 to 22) of the DRAM logical address value (MA31: 02) = “0000 0001 00” exist in common. Does not exist. Therefore, (MA31 to 22) = “0000 0001 00” is used as a common decoding condition for RAS0 and RAS1.
[0077]
As for RAS0, the start position of the row address in the DRAM logical address is shifted 1 bit to the left, and 1 bit (MA11) = “0” between the row address and the column address of the 2 Mbyte DRAM bank corresponding to RAS0. Is added as a decoding condition.
[0078]
Also for RAS1, the start position of the row address in the DRAM logical address is shifted left by 1 bit, and 1 bit (MA11) = “1” between the row address and the column address of the corresponding 2M-byte DRAM bank is set as the decoding condition. Added.
[0079]
When the decoding conditions of RAS0 and RAS1 are determined in this way, even-numbered pages (0, 2, 4, 6,...) In the 16-20 Mbyte 4 Mbyte address range are allocated to the 2 Mbyte DRAM bank of RAS0 Thus, odd-numbered pages (1, 3, 5, 7,...) Are allocated to the 2 Mbyte DRAM bank of RAS1. Therefore, when continuous access is performed in the range of 16 to 20 Mbytes, the two DRAM banks are alternately accessed in page units in the order of RAS0, RAS1, RAS0, RAS1,.
[0080]
As described above, the page interleaving determines the decoding condition of each RAS based on the bit string that is commonly present in the address range of the interleave group and the predetermined bit string between the row address and the column address, and uses the RAS decoder 122 for determining the RAS decoding condition. It can be realized just by setting to.
[0081]
Initial setting processing for the memory control logic 120 such as setting of decoding conditions in the RAS decoder 122 is executed by an IRT routine of the BIOS ROM 14.
[0082]
FIG. 7 shows the procedure of the initial setting operation for the memory control logic 120 executed by the BIOS IRT routine.
[0083]
When the system is powered on, the IRT routine first checks the memory type of each DRAM bank (the bit width of each column address and row address), and detects the memory size according to the memory bank type (step S11). The bit width of each of the column address and the row address can be detected by executing a write / read compare test for a specific memory address of the DRAM bank to be tested.
[0084]
Details of the memory size detection processing operation performed in step S11 will be described later with reference to FIG.
[0085]
Next, the IRT routine performs memory relocation of the DRAM bank in the system (step S12). In this memory rearrangement, as described with reference to FIG. 4, the memory addresses are arranged in ascending order from the DRAM bank having the largest memory size, and the address range to be assigned to each DRAM bank is determined according to the arrangement.
[0086]
Next, as described with reference to FIG. 5, the IRT routine detects, for each address range assigned to each DRAM bank, a bit string that exists in common only in the DRAM logical address value belonging to that range, and uses the common bit string as the RAS line. Each decoding condition is determined (step S13).
[0087]
When the page interleave architecture is not used, the IRT routine sets the decoding conditions of each RAS line determined in step S13 as they are in the internal register of the RAS decoder 122 (step S17). Next, the IRT routine sets a control parameter for designating the row address start position for each RAS line in the internal register of the row address / column address multiplexer 123, and also uses the internal register of the page hit determination circuit 126 for page hit determination. A control parameter for designating the position of the CPU address to be set for each RAS line is set (step S18). The values of these control parameters are determined according to the memory bank type detected in step S11.
[0088]
On the other hand, when the page interleave architecture is adopted, the IRT routine determines a page interleaveable group according to the DRAM map arranged in the memory size order in step S12 (step S15). Next, the IRT routine changes the decoding condition of each RAS based on a bit string that exists in common in the address range of the page interleave group and a predetermined bit string between the row address and the column address (step S16).
[0089]
Thereafter, the IRT routine sets the decoding condition of each RAS line determined in step S16 in the internal register of the RAS decoder 122 (step S17). Next, the IRT routine sets a control parameter for designating the row address start position for each RAS line in the internal register of the row address / column address multiplexer 123, and also uses the internal register of the page hit determination circuit 126 for page hit determination. A control parameter for designating the position of the CPU address to be set for each RAS line is set (step S18). The row address start position is determined based on the memory bank type detected in step S11 and the number of bits between the row address and the column address used as decoding conditions for page interleaving. Further, the position of the CPU address used for page hit determination is determined according to the memory bank type detected in step S11.
[0090]
Next, the principle of the memory size detection process of the DRAM bank will be described with reference to FIGS.
[0091]
First, the types of DRAM banks that can be controlled by one RAS will be described with reference to FIG. As shown in the figure, the DRAM banks are roughly divided into four banks of type 1 to type 4.
[0092]
Type 1 DRAM banks have a memory size of 2 Mbytes. This type 1 DRAM bank includes four 4M bit DRAM chips of 512K (1K rows × 512 columns) × 8 bits, the row address bit width is 10 bits, and the column address bit width is 9 bits. is there.
[0093]
Type 2 DRAM banks have a memory size of 4 Mbytes. This type 2 DRAM bank includes eight 1M (1K rows × 1K columns) × 4 bit 4Mbit DRAM chips, with a row address bit width of 10 bits and a column address bit width of 10 bits. is there.
[0094]
Type 3 DRAM banks have a memory size of 8 Mbytes. This type 3 DRAM bank includes four 16M bit DRAM chips of 2M (2K rows × 1K columns) × 8 bits, the row address has a bit width of 11 bits and the column address has a bit width of 10 bits. is there.
[0095]
Type 4 DRAM banks have a memory size of 16 Mbytes. This type 4 DRAM bank includes 8 16M bit DRAM chips each having 4M (2K rows × 2K columns) × 4 bits. The row address has a bit width of 11 bits and the column address has a bit width of 11 bits. is there.
[0096]
9, FIG. 10, and FIG. 11 show the memory configurations of the system memory 13, the expansion memory 41, and the expansion memory 42 of FIG. 1, respectively.
[0097]
When the system memory 13 is constituted by two 2M byte DRAM banks of type 1, as shown in FIG. 9, the four DRAM chips of one 2M byte DRAM bank are connected to the RAS0 line and the CAS line. The four DRAM chips of the other 2M byte DRAM bank are commonly connected to the RAS1 line and the CAS line. All the chips in these two 2M byte DRAM banks are connected in parallel to both the memory address bus 33 and the data bus 322.
[0098]
Which of these two 2M byte DRAM banks is addressed is determined by which of RAS0 and RAS1 is activated.
[0099]
When the RAS0 line is energized, the lower 10 bits of the address value output on the memory address bus 33 at that time are taken into the four chips connected to the RAS0 line as row addresses. Thereafter, the four chips connected to the RAS0 line take in the lower 9 bits of the address value output on the memory address bus 33 as the column address when the CAS line is energized. The same address of each of the four chips connected to the RAS0 line is simultaneously addressed by these 10-bit row address and 9-bit column address, and a DRAM corresponding to the RAS0 line in units of 32 bits of 8 bits per chip. The bank is read / write accessed.
[0100]
Similarly, when the RAS1 line is energized, the low-order 10-bit row address of the address value output on the memory address bus 33 at that time is taken into the four chips connected to the RAS1 line, respectively. It is. Thereafter, the four chips connected to the RAS1 line take in the column address of the lower 9 bits of the address value output on the memory address bus 33 when the CAS line is energized. With these 10-bit row address and 9-bit column address, the same storage location of each of the four chips connected to the RAS1 line is addressed simultaneously, corresponding to the RAS1 line in units of 32 bits, 8 bits per chip. The DRAM bank to be read is accessed for read / write.
[0101]
When the expansion memory 41 is composed of one type 3 8M byte DRAM bank, as shown in FIG. 10, the four DRAM chips of the 8M byte DRAM bank are connected to the RAS2 line and the CAS line. Commonly connected. All chips in the 8 Mbyte DRAM bank are connected in parallel to both the memory address bus 33 and the data bus 322.
[0102]
When the RAS2 line is energized, the lower 11 bits of the address value output on the memory address bus 33 at that time are taken into the four chips connected to the RAS2 line as row addresses. Thereafter, the four chips connected to the RAS2 line take in the lower 10 bits of the address value output on the memory address bus 33 as the column address when the CAS line is energized. With these 11-bit row address and 10-bit column address, the corresponding storage locations of each of the four chips connected to the RAS0 line are simultaneously addressed, and RAS2 is in units of 32 bits, 8 bits per chip. The DRAM bank corresponding to the line is read / write accessed.
[0103]
When the expansion memory 42 is constituted by two 4M byte DRAM banks of type 2, as shown in FIG. 11, the eight DRAM chips of one 4M byte DRAM bank are connected to the RAS 4 line and the CAS line. 8 DRAM chips of the other 4 Mbyte DRAM bank are commonly connected to the RAS 5 line and the CAS line. All chips in these 4 Mbyte DRAM banks are connected in parallel to both the memory address bus 33 and the data bus 322.
[0104]
Which of these two 4M byte DRAM banks is addressed is determined by which of RAS4 and RAS5 is activated.
[0105]
When the RAS4 line is energized, the lower 10 bits of the address value output on the memory address bus 33 at that time are taken into the eight chips connected to the RAS4 line as row addresses. Thereafter, the eight chips connected to the RAS4 line take in the lower 10 bits of the address value output on the memory address bus 33 as the column address when the CAS line is energized. With these 10-bit row address and 10-bit column address, the same storage location of each of the 8 chips connected to the RAS4 line is addressed simultaneously, and the 4 bits per chip, a total of 32 bits, is assigned to the RAS4 line. The corresponding DRAM bank is read / write accessed.
[0106]
Similarly, when the RAS5 line is energized, the lower 10 bits of the address value output on the memory address bus 33 at that time are taken into the eight chips connected to the RAS5 line as row addresses, respectively. It is. Thereafter, the eight chips connected to the RAS 5 line take in the lower 10 bits of the address value output on the memory address bus 33 as the column address when the CAS line is energized. With these 10-bit row address and 10-bit column address, the same storage location of each of the 8 chips connected to the RAS5 line is addressed at the same time. The corresponding DRAM bank is read / write accessed.
[0107]
As described above, the relationship between the number of bits used as a row address and the number of bits used as a column address differs for each type of DRAM bank. The memory size of the DRAM bank connected to each RAS line is detected by utilizing the difference in the number of bits used as the row address and the column address.
[0108]
Hereinafter, the procedure of the memory size detection process executed in step S11 of the IRT routine will be described with reference to the flowchart of FIG.
[0109]
The IRT routine performs memory size detection processing of the DRAM bank connected to the RAS line in the order of RAS0, RAS1, RAS2,. The IRT routine first sets a predetermined decoding condition in the RAS decoder 122 so that only the activation of the RAS line to be inspected is permitted (step S21). In this case, as a decoding condition of the inspection target RAS line, a common bit string is used for a memory address value used in several memory accesses performed for memory size detection. Further, all the RAS lines other than the inspection target RAS line are different from the inspection target RAS line so that the RAS lines are not energized by several memory accesses performed for memory size detection. A predetermined bit string is set as each decoding condition.
[0110]
Next, in the IRT routine, the type 4 DRAM bank (column address CA = 11 bits, row address RA = 11 bits) having the largest number of column addresses among the type 1 to type 4 DRAM banks is checked. As a result, a write / read / compare test is performed on the DRAM bank (step S22). In this case, a control parameter corresponding to a type 4 DRAM bank is set in the row address / column address multiplexer 123. In the write / read compare test, a write access at a write address 00001000H (H indicates hexadecimal display) and a read access at a read address 00000000H are performed, and it is checked whether or not the write data at that time matches the read data. (Step S23).
[0111]
If the DRAM bank actually connected to the RAS line to be inspected is a type 4 DRAM bank as expected, data can be normally written to the address 00001000H, so the values of the write data and read data are Disagreement. On the other hand, if the DRAM bank actually connected to the RAS line to be inspected is a type 1, type 2, or type 3 bank whose column address number is 10 bits or less, the values of the write data and read data Match. This is due to the following reason.
[0112]
That is, since the setting corresponding to the type 4 DRAM bank is made in step S22, the 11-bit row address RA (MA23,..., MA13) output at the time of the write access of the address 00001000H is 00000000000000. Bit column address CA (MA12,..., MA02) = 10000000000000. In a DRAM bank having 10 or less column addresses, the value “1” of the most significant bit MA12 of the 11-bit column address CA is ignored. Therefore, when Type 1, Type 2, or Type 3 banks are connected, the write address of write address 00001000H causes the address specified by column address CA = 0000000000000 in the first row, that is, address 00000000H. Data is written. Thereby, the read data read by the read access of the read address 00000000H matches the write data.
[0113]
Therefore, when a mismatch between the write data and the read data is detected in step S23, the DRAM bank connected to the RAS line to be inspected is the type 4 DRAM bank as expected (CA = 11 bits, RA = 11 bits). On the other hand, if a match between the write data and the read data is detected, the DRAM bank connected to the inspection target RAS line has the number of column address bits. Is determined to be a DRAM bank of another type (type 1, type 2, or type 3) of 10 bits or less. In this case, the following processing after step S25 is performed.
[0114]
In other words, the IRT routine now has a type 3 (or type 2) memory configuration (column address CA = 10 bits, row address RA = 11 bits) having the number of column address bits next to type 4 and the RAS line to be examined Assuming that the DRAM bank is connected, a write / read compare test is performed on the DRAM bank (step S25). In this write / read compare test, a write access at the write address 008000000H and a read access at the read address 00000000H are performed, and it is checked whether or not the write data at that time matches the read data (step S26).
[0115]
If the DRAM bank actually connected to the RAS line to be inspected is a type 1 DRAM bank having a column address number of 9 bits or less, the most significant bit “1” of the column address as described above. Is ignored, data is written to the address specified by the address 00000000H of the type 1 DRAM bank. As a result, the values of the write data and the read data match. Therefore, when a match between the write data and the read data is detected, the DRAM bank connected to the inspection target RAS line is a type 1 DRAM bank (CA = 9 bits, RA = 10 bits, memory size = 2 Mbytes). ) (Step S27).
[0116]
On the other hand, if the DRAM bank actually connected to the RAS line to be examined is a type 2 or type 3 DRAM bank having a 10-bit column address bit number as expected, data is normally written to the address 00010000H. Therefore, the values of the write data and the read data do not match. Therefore, when a mismatch between the write data and the read data is detected, the following processing after step S28 is performed in order to detect which type 2 or type 3 DRAM bank is connected. .
[0117]
That is, the IRT routine assumes that a type 3 DRAM bank (column address CA = 10 bits, row address RA = 11 bits) having a large number of row address bits is connected among the DRAM banks. Then, a write / read compare test is performed on the DRAM bank (step S28).
[0118]
In this write / read compare test, a write access of the write address 00400000H and a read access of the read address 00000000H are performed, and it is checked whether or not the write data and the read data match at that time (step S29).
[0119]
If the DRAM bank actually connected to the RAS line to be inspected is a type 3 DRAM bank as expected, data can be normally written to the address 00400000H, so the values of the write data and read data are Disagreement. On the other hand, when the DRAM bank actually connected to the inspection target RAS line is a type 2 bank whose row address number is 10 bits, the values of the write data and the read data match. This is due to the following reason.
[0120]
That is, since the setting corresponding to the type 3 DRAM bank is made in step S28, the 11-bit row address output at the time of address access 00000000H write access is RA (MA22,..., MA12) = 10000000000000. Bit column address CA (MA11,..., MA02) = 0000000000000. In a type 2 DRAM bank with 10-bit row addresses, the value “1” of the most significant bit MA22 of the 11-bit row address RA is ignored. Therefore, when a type 2 bank is connected, data is written to the address designated by the column address CA = 0000000000000 in the first row, that is, address 00000000H, by the write access of the write address 00400000H. Thereby, the read data read by the read access of the read address 00000000H matches the write data.
[0121]
Therefore, when a mismatch between the write data and the read data is detected in step S29, the DRAM bank connected to the RAS line to be inspected is the type 3 DRAM bank as expected (CA = 10 bits, RA = 11 bits). On the other hand, if a match between the write data and the read data is detected, the DRAM bank connected to the inspection target RAS line has the number of row address bits. Is a 10-bit type 2 DRAM bank (CA = 10 bits, RA = 10 bits, memory size = 4 Mbytes) (step S31).
[0122]
Next, specific circuit configurations of the RAS decoder 122, the row address / column address multiplexer 123, and the page hit determination circuit 126 described with reference to FIG. 2 will be described.
[0123]
FIG. 13 shows a specific circuit configuration of the RAS decoder 122. As illustrated, the RAS decoder 13 includes six RAS decode circuits 51 to 56 corresponding to the RAS0 line to the RAS5 line, respectively. Each of these RAS decode circuits 51 to 56 checks whether or not the DRAM logical address (MA31: 02) matches with the corresponding decode condition, and controls the corresponding RAS line at a predetermined timing when they match. In this case, it is not actually necessary to see all the bit values of the 30-bit DRAM logical address (MA31: 02). From conditions such as the type of DRAM bank to be supported and the maximum DRAM logical address space, MA26, MA25, MA24, Only 9 bits of MA23, MA22, MA21, and MA13, MA12, MA11 are used for decoding.
[0124]
Since the RAS decode circuits 51 to 56 all have the same circuit configuration, the circuit configuration of the RAS decode circuit 51 will be described as a representative here.
[0125]
The RAS decode circuit 51 includes a RAS set register 61, a RAS mask register 62, nine match / mismatch detection circuits 71 to 79, nine mask circuits 71 to 79, and an AND circuit 91.
[0126]
The RAS set register 61 is an I / O register that can be read / written by the CPU 11, and a bit string indicating the decoding condition of the RAS0 line is set here. For example, when the decoding condition of the RAS0 line is determined as shown in FIG. 5, “00100X XX1” is set in the RAS set register 61 as the decoding condition of the RAS0 line. Here, X means a bit value (Don't Care) not related to the decoding condition.
[0127]
The RAS mask register 62 is an I / O register that can be read / written by the CPU 11. Here, whether or not the determination result of coincidence / mismatch between the decoding condition of the RAS0 line and the DRAM logical address is masked for each bit. Is set (“0” = mask, “1” = do not mask). Here, masking means that the determination result of the bit always matches regardless of the determination result of the corresponding 1 bit of the bit string of the decoding condition. Therefore, when “00100X XX1” is set as the decoding condition in the RAS set register 61 as described above, the mask data “111110 001” is set in the RAS mask register 62. Thereby, the bit of “X” in “00100X XX1” of the decoding condition can be excluded from the decoding condition.
[0128]
Match / mismatch detection circuits 71 to 79 detect match / mismatch between the corresponding bits of the DRAM logical address and the decode condition, respectively. Each of these match / mismatch detection circuits 71 to 79 can be realized by an exclusive OR gate. The nine mask circuits 71 to 79 mask the detection result outputs of the corresponding match / mismatch detection circuits 71 to 79, respectively.
[0129]
As described above, the RAS decoder 122 can be realized only by logic for matching / mismatching data corresponding to a data size of 9 bits per RAS line.
[0130]
Next, a specific circuit configuration of the row address / column address multiplexer 123 will be described with reference to FIG.
[0131]
As shown in the figure, the row address / column address multiplexer 123 includes a register file 201, a pattern decoder 202, a row address selector 203, row address start position switching circuits 204 to 207, and a row address / column address selector 208. .
[0132]
The register file 201 is a group of I / O registers that can be read / written by the CPU 11, and six control parameters corresponding to the RAS0 to RAS5 lines are set therein. Each control parameter specifies the row address start position of the DRAM bank connected to the corresponding RAS line, that is, which bit of the DRAM logical address is to be the LSB of the row address.
[0133]
There is a possibility that four bits of the DRAM logical addresses MA11, MA12, MA13, and MA14 are used as the row address start position depending on the type of DRAM to be supported and the page interleaving condition. Each control parameter is composed of 4-bit data designating one of these four types of row address start positions. The control parameter “0001” specifies MA11, “0010” specifies MA12, “0011” specifies MA13, and “0100” specifies MA14.
[0134]
One of the six control parameters set in the register file 201 is read by the pattern decoder 202. Which control parameter is read out is determined by the decoding result output of the RAS decoder 122. For example, when the RAS 0 line is energized by the RAS decoder 122, the control parameter corresponding to the RAS 0 line is read from the register file 201.
[0135]
The pattern decoder 202 decodes the control parameter read from the register file 201, and generates a selection signal for causing the selector 203 to select one of the four types of row addresses according to the decoding result.
[0136]
The row address start position switching circuit 204 sets a total of 11 bits (MA21,..., MA11), where MA11 is a row address start position (LSB), from the DRAM logical address MA31: 02) as a row address (RA10: 0). Take out. Similarly, the row address start position switching circuit 205 takes out a total of 11 bits (MA22,..., MA12) with MA12 as LSB, and the row address start position switching circuit 206 has a total of 11 bits (MA23,... With MA13 as LSB). .., MA13), and the row address start position switching circuit 207 extracts a total of 11 bits (MA24,..., MA14) with MA14 as LSB as a row address.
[0137]
These row address start position switching circuits 204 to 207 are constituted by, for example, a barrel shifter.
[0138]
The row address selector 203 selects and outputs one of the four types of row addresses output from the row address start position switching circuits 204 to 207 in accordance with a selection signal from the pattern decoder 202. The row address selected by the row address selector 203 is supplied to the row address / column address selector 208. The row address / column address selector 208 is also supplied with a column address. As the column address, the lower 11 bits (MA12,... MA02) of the DRAM logical address are always used.
[0139]
The row address / column address selector 208 selectively outputs a row address and a column address onto the memory address bus 33 at a timing specified by a control signal from the timing control circuit 125 of FIG.
[0140]
In the row address / column address multiplexer 123, row address cutout operations are performed by the row address start position switching circuits 204 to 207 in parallel with the decode operation of the RAS decoder 122. When the decoding result of the RAS decoder 122 is confirmed, one control parameter corresponding to the RAS line to be activated designated by the confirmed decoding result is read from the register file 201 and sent to the pattern decoder 202. . Then, the decoding operation by the pattern decoder 202 and the row address selection operation of the row address selector 203 are executed according to the control parameter, thereby determining the row address to be used for DRAM access.
[0141]
Here, the description has been made so that all 11 bits of the row address (RA10: 0) are switched in accordance with the RAS line by the row address start position switching circuits 204 to 207 and the row address selector 203. There is no need to switch the bits.
[0142]
That is, in any case where the row address start position is MA11, MA12, MA13, and MA14, the 6 bits MA14 to MA19 are used in common, and therefore these bits can be excluded from the switching target. An example of the correspondence between the CPU address and the row address in this case is shown in FIG.
[0143]
In FIG. 15, only the lower 3 bits (RA2 to RA0) and the upper 2 bits (RA10, RA9) of the row address are to be switched. In this way, the 6 bits of MA14 to MA19 of the CPU address can be sent directly to the row address / column address selector 208 as the middle 6 bits (RA8 to RA3) of the row address. Each of 204 to 207 and the row address selector 203 can be realized only by a hardware configuration for 5 bits to be switched.
[0144]
As described above, the circuit configuration of the row address / column address multiplexer 123 of FIG. 14 can greatly reduce the number of circuits required. However, the operation of the three circuit blocks (the operation of selecting and reading out the control parameter to be used from the register file 201) until the row address to be used for DRAM access is determined after the decoding result of the RAS decoder 122 is determined. The decoding operation by the pattern decoder and the row address selection operation by the row address selector 203) must be performed sequentially. Therefore, there is a problem that a relatively large delay occurs in the row address / column address multiplexer 123.
[0145]
FIG. 16 shows a second circuit configuration example of the row address / column address multiplexer 123. The configuration shown in FIG. 16 is improved as follows in order to reduce the delay in the row address / column address multiplexer 123.
[0146]
That is, in the row address / column address multiplexer 123 of FIG. 16, instead of the pattern decoder 202 and the row address selector 203 of FIG. 14, six pattern decoders 202-1 to 202- corresponding to the RAS0 to RAS5 lines, respectively. Six and six row address selectors 203-1 to 203-6 are provided. The pattern decoders 202-1 to 202-6 control the row address selection operations of the row address selectors 203-1 to 203-6 according to the RAS0 control parameter to the RAS5 control parameter of the register file 201, respectively.
[0147]
Further, in the next stage of the row address selectors 203-1 to 203-6, one of six types of row addresses (RAS0 row address to RAS5 row address) obtained by the row address selectors 203-1 to 203-6 is provided. A row address selector 209 is provided for selecting one according to the decoding result of the RAS decoder 122.
[0148]
In this circuit configuration, in parallel with the decoding operation of the RAS decoder 122, row address cutout operations by the row address start position switching circuits 204 to 207, pattern decoders 202-1 to 202-6, and a row address selector 203-1. The row address selection operation by .about.203-6 is performed. Thus, six types of row addresses (RAS0 row address to RAS5 row address) respectively corresponding to the RAS0 to RAS5 lines can be generated without waiting for the determination of the decoding result of the RAS decoder 122.
[0149]
When the decoding result of the RAS decoder 122 is confirmed, the row address corresponding to the RAS line to be activated designated by the confirmed decoding result is selected by the row address selector 209.
[0150]
Therefore, the circuit operation required from the determination of the decoding result of the RAS decoder 122 to the determination of the row address to be used for DRAM access is only the address selection operation by the address selector 209 in the final stage, and the internal delay is reduced. It is greatly reduced.
[0151]
In the configuration of FIG. 16, it is not necessary to switch the bits of all the row addresses as in the case of FIG.
[0152]
FIG. 17 shows a specific circuit configuration of the page hit determination circuit 126 of FIG.
[0153]
The page hit determination circuit 126 is provided with a register file 301, a page hit determination CPU address register 302, a match determination circuit 303, a mask circuit 304, and a match determination mask position register 305 as shown in the figure.
[0154]
The register file 301 is an I / O register that can be read / written by the CPU 11. Here, mask data (whether or not to match the matching condition with the CPU address used for page hit determination) is specified. “0” = mask, “1” = do not mask) is set as a control parameter corresponding to each of the RAS0 to RAS5 lines.
[0155]
That is, in the page hit determination, for the RAS decoding, the row address (page address) excluding the remaining address excluding the in-page address, that is, the portion corresponding to the column address, from the CPU address (A31: 02). Address is targeted. Since the portion corresponding to the column address is not involved in the page hit determination, the determination result for each bit used as the column address needs to be masked with mask data. Here, masking means that the determination result of the corresponding bit always matches.
[0156]
Actually, the mask data corresponding to each RAS line is composed of 3-bit data indicating whether or not to mask A12, A11, and A10, not all the bits of the column address. This is because the match determination circuit 303 excludes bits lower than A10 that are always used as column addresses regardless of the type of DRAM bank from the match determination, and only the higher bits after A10 are subject to match determination. This is because each of the three bits A12, A11, and A10 is used as a part of the column address depending on the type of DRAM bank.
[0157]
For example, when a type 1 DRAM bank (number of column address bits = 9 bits) is connected to the RAS0 line, only A10 is used as part of the column address among the three bits A12, A11, and A10. The At this time, mask data “110” corresponding to the RAS 0 line is set in the register file 301. One of the six mask data set in the register file 301 is read from the register file 301 and set in the match determination mask position register 305. Which mask data is read out is determined by the decoding result output of the RAS decoder 122. For example, when the RAS 0 line is energized by the RAS decoder 122, mask data corresponding to the RAS 0 line is read from the register file 301.
[0158]
The page hit determination CPU address register 302 holds 17 bits A26 to A11 of the CPU address (A31: 02) at the previous memory access as the page hit determination CPU address. The contents of the page hit determination CPU address register 302 are updated according to the CPU address (A31: 02) used for memory access at that time when a bank miss or page miss occurs without a page hit. That is, when a bank miss or page miss occurs, the timing control circuit 125 generates a register update signal. In response to the register update signal, the CPU address (A26 to A11) output on the CPU address bus at that time is latched in the page hit determination CPU address register 302. As a result, the content of the page hit determination CPU address register 302 is changed to the CPU address at the memory cycle in which a bank miss or page miss occurs.
[0159]
The coincidence determination circuit 303 is a comparator that compares the CPU address (A26 to A11) at the time of the current memory access with the CPU address (A26 to A11) held in the page hit determination CPU address register 302 for each bit. , A26 to A11 are output 17-bit data indicating the detection results.
[0160]
The mask circuit 304 masks the detection result outputs of A12, A11, and A10 among the detection results of A26 to A11 according to the mask data of the coincidence determination mask position register 305, and the detection result outputs after masking all indicate a match. Sometimes a page hit signal HIT is generated.
[0161]
In the coincidence determination mask position register 305, mask data corresponding to the RAS line to be energized is set. The contents of the match determination mask position register 305 are updated to mask data corresponding to the RAS line activated by the RAS decoder 122 when a bank miss or page miss occurs without a page hit. That is, when a bank miss or page miss occurs, the timing control circuit 125 generates a register update signal. In response to this register update signal, the mask data in the register file 301 selected by the RAS decoder 122 at that time is latched in the coincidence determination mask position register 305. As a result, the contents of the coincidence determination mask position register 305 are changed to mask data corresponding to the RAS line activated during the memory cycle in which a bank miss or page miss occurs.
[0162]
According to the page hit determination circuit 126 configured as described above, it is determined whether or not the current memory access is the same bank and the same page as the previous memory access by using the CPU address instead of the DRAM logical address. Page hit determination is performed. The CPU address can be used for page hit determination because the unit of address conversion from the CPU address to the DRAM logical address by the address conversion circuit 121 is set to a value larger than the page size of the DRAM bank as described above. Because. Therefore, the address translation operation and the page hit determination operation can be performed in parallel, the page hit determination can be performed at high speed, and the memory access speed can be increased.
[0163]
The timing control circuit 125 is provided with a timing control register 125 that can be read / written by the CPU 11. In the timing control register 125a, information specifying the RAS decoding timing of the RAS decoder 122 and information specifying the page hit determination timing of the page hit determination circuit 126 are set, and the RAS decoder 122 and the page hit are determined according to the setting information. The operation timing of the determination circuit 126 is determined.
[0164]
Normally, the operation timing of the RAS decoder 122 and the page hit determination circuit 126 is fixedly determined by the address delay of the CPU 11, the bus clock, the process of the circuit being used, etc., so that each time these conditions change. A design change is required. However, in this embodiment, since the operation timing of the RAS decoder 122 and the page hit determination circuit 126 can be changed by setting by software, it is not necessary to change the design even if the condition affecting the timing changes.
[0165]
Further, the timing control circuit 125 considers a case where a page hit should not be determined even if the addresses match, as in the case where a refresh cycle is inserted, etc. Two states of “page accessible state” and “page inaccessible state” can be managed. When the current state is the “page inaccessible state”, the timing control circuit 125 invalidates the page hit signal.
[0166]
“Page accessible state” means that the RAS from the previous access has been issued. A state other than the “page accessible state” is a “page inaccessible state”. When the system is reset, the page is inaccessible.
[0167]
After the CPU 11 accesses, it becomes “page accessible state” regardless of whether it is read or write. The next DRAM access of the CPU 11 when in the “page accessible state” is either a page hit, a bank miss, or a page miss depending on the address. When a page hit occurs, it can be processed at high speed. The next DRAM access of the CPU 11 in the “page inaccessible state” results in a bank miss regardless of the address.
[0168]
The factors causing the “page inaccessible state” are the hold acknowledge HLDA state, DRAM shadow refresh, RAS timeout, and system reset. Therefore, the timing control circuit 125 determines whether the “page accessible state” and the “page inaccessible state” are in accordance with the address strobe ADS signal, the HLDA signal from the CPU 11, the DRAM refresh signal DRAM from the refresh timer, the system reset signal, and the like. Manage one state.
[0169]
Further, the timing control circuit 125 has a built-in RAS timeout circuit, and shifts from the “page accessible state” to the “page inaccessible state” when the RAS enabled state continues for a certain time (tRAS) or longer.
[0170]
When the current state is the “page inaccessible state”, in order to invalidate the page hit signal, the timing control circuit 125 uses the memory address value held in the page hit determination CPU address register 302 as the DRAM. You may change into the value which is not used for access.
[0171]
Further, the timing control circuit 125 has the following two modes to support page mode access even when a bus master other than the CPU 11 accesses the DRAM, and is configured to dynamically change these modes. ing.
[0172]
(Mode 1)
This mode assumes that the CPU 11 and other bus masters rarely access the same page. In response to the bus master switching, the “page accessible state” to the “page inaccessible state”. In this mode, all RAS are disabled. Thereby, it is possible to save precharge time when RAS is newly enabled.
[0173]
(Mode 2)
This mode is a mode that assumes usage in which the CPU 11 and another bus master access the same page. For example, this corresponds to the case where the CPU 11 immediately reads the data written by the bus master. In this mode, even if the bus master is switched, the RAS is kept enabled without shifting to the “page inaccessible state”, so that high-speed access to the same page is possible.
[0174]
One of these modes may be used in a fixed manner. However, if there are many address patterns that cannot be obtained because of a page hit during operation in mode 1, the mode shifts to mode 2, and no page hit occurs during operation in mode 2. It is preferable to perform mode switching using the page hit result, such as shifting to mode 1 if there are many cases.
[0175]
In the page hit determination circuit 126 of FIG. 17, the page hit determination CPU address register 302 stores the memory address information from the CPU along with the memory address information corresponding to the memory address from the CPU. Information indicating whether a different memory device is specified for access and cycle type information indicating whether the memory access at that time is write access or read access are also held, and access is performed by write access and read access. When the target memory device is different, the stored memory address matches the memory address from the CPU at the time of the current memory access, and the stored cycle type information and the cycle type of the current memory access Match determination circuit 3 3 have been added to the page hit determination conditions by.
[0176]
That is, when the memory devices to be accessed are different between the write access and the read access, the page hit determination cannot actually be performed only by whether or not the memory addresses match. In this case, as a result, the page hit determination takes time, and the merit of the high-speed page hit determination cannot be utilized.
[0177]
Therefore, as described above, in this embodiment, when the memory devices to be accessed are different between the write access and the read access, the cycle type information of write or read is also added to the page hit determination condition. Hereinafter, the configuration for that purpose will be specifically described.
[0178]
First, with reference to FIG. 18, the relationship between the memory address space of the CPU 11 managed by the memory area attribute table 127 of FIG. 17 and the memory attribute information will be described.
[0179]
The size of one address area managed by the memory area attribute table 127 is 16K bytes. As shown in FIG. 18, the CPU memory address spaces 00000000H to 0000FFFFH are defined as AREA00 to AREA63 in order from 000000H. .
[0180]
Among these AREA00 to AREA63, 8-bit attribute information as shown in FIG. 19 is set in each attribute register corresponding to AREA40 to AREA63 in which a plurality of types of memory devices including DRAM may be arranged. . As shown in FIG. 19, of the 8-bit attribute information, 2 bits of bit 7 and bit 6 are read attribute information (READ ATTRIBUTE), 2 bits of bit 5 and bit 4 are write attribute information (WRITE ATTRIBUTE), and bit 3 is Two bits of DRAM write protect information (WP), bit2 and bit1 are used as caching control information (CASH).
[0181]
The read attribute information (READ ATTRIBUTE) indicates the type of memory device to be read-accessed. As shown in FIG. 20, the combination of two bits of bit 7 and bit 6 is used on the DRAM and VL buses. A memory, a memory on the PCI bus, or a memory on the ISA bus is designated. The write attribute information (WRITE ATTRIBUTE) indicates the type of memory device to be write-accessed. As shown in FIG. 21, the combination of bit 5 and bit 4 on the DRAM and VL buses. A memory, a memory on the PCI bus, or a memory on the ISA bus is designated.
[0182]
The DRAM write protect information (WP) indicates whether or not write protection is performed on the DRAM according to the contents of bit 3 as shown in FIG. 22 when the DRAM is designated as a write access target memory device by the write attribute information. Indicate.
[0183]
The caching control information (CASH) is for controlling the validity / invalidity of the caching operation of the RAM when both the read attribute information and the write attribute information specify the DRAM, and is shown in FIG. As shown in the figure, any one of write back cache enable, write through cache enable, and cache disable is specified by the combination of two bits of bit2 and bit1. For example, the cache disable setting is made for the DRAM area where the VGA BIOS and the system BIOS are copied.
[0184]
In the page hit determination CPU address register 302, memory attribute information of the memory address area corresponding to the memory address is read from the memory area attribute table 127 together with the memory address from the CPU 11, and write access differs from read access. Information indicating whether or not a memory device is designated and cycle type information indicating whether the memory access at that time is a write access or a read access are held together. When the memory device to be accessed differs between write access and read access, the retained memory address matches the memory address from the CPU at the time of the current memory access, and the retained cycle type information and this time This match with the memory access cycle type is added to the page hit determination condition by the match determination circuit 303.
[0185]
Accordingly, the memory attribute can be determined at high speed, and high-speed memory access utilizing high-speed page hit determination becomes possible.
[0186]
Further, the page hit determination CPU address register 302 further holds DRAM write protect information (WP) and caching control information (CASH) in the memory address area corresponding to the memory address from the CPU in addition to the above information. It is desirable to keep it. Thereby, the page hit determination is made, and at the same time, the type of cycle to be executed next can be determined.
[0187]
That is, when it is determined that a page hit occurs, at the same time, the cycle type is determined as follows.
[0188]
1. Light page hit unprotected
This is a cycle executed when the current memory access cycle is a write cycle and the held write protect information indicates non-write protect, and writing to the DRAM is executed in page mode. .
[0189]
2. Light page hit protection
This is a cycle that is executed when the current memory access cycle is a write cycle, and the held write protect information indicates write protect, and CAS is not asserted. Realized.
[0190]
3. Lead page hit single
This is a cycle that is executed when the current memory access cycle is a read cycle and the cache control information being held indicates that the cache is invalid. The read cycle for reading data from the DRAM is 1 in page mode. Executed once.
[0191]
4). Lead page hit burst
This is a cycle that is executed when the current memory access cycle is a read cycle and the cache control information being held indicates that the cache is valid, and a burst read cycle for reading a plurality of continuous data from the DRAM Is executed in page mode.
[0192]
Here, the write protect information and the cache control information are recorded together with the CPU address for page hit determination when RAS is issued again for the page due to a bank miss or page miss. This is because waiting for the decoding result of the write protect information and the cache control information is not in time for the page hit decision time.
[0193]
Therefore, the write protect information at the read cycle and the cache control information at the write cycle are also meaningful.
[0194]
If no page hit occurs, it is determined whether a bank miss or a page miss occurs. When a bank miss is determined, the cycle type is determined at the same time as follows.
[0195]
1. Write bank miss unprotected
This is a cycle executed when the current memory access cycle is a write cycle and the write protect information corresponding to the current memory address indicates non-write protect, and RAS to another DRAM bank is asserted. Then, data writing is executed by early write.
[0196]
2. Write bank miss protection
This is a cycle executed when the current memory access cycle is a write cycle and the write protect information corresponding to the current memory address indicates write protect, and CAS is not asserted. Write protection is realized.
[0197]
3. Lead bank miss single
This is a cycle executed when the current memory access cycle is a read cycle, and the cache control information corresponding to the current memory address indicates cache invalidity, and RAS for another DRAM bank is asserted. A read cycle for reading data from the DRAM bank is executed once.
[0198]
4). Lead bank miss burst
This is a cycle executed when the current memory access cycle is a read cycle and the cache control information corresponding to the current memory address indicates that the cache is valid, and RAS for another DRAM bank is asserted. Thereafter, a burst read cycle for reading a plurality of continuous data from the DRAM bank is executed.
[0199]
Here, the write protect information and the cache control information are decode signals defined for the page accessed this time, and are recorded together with the CPU address for page hit determination for subsequent access.
[0200]
When a page miss is determined, the cycle type is determined at the same time as follows.
[0201]
1. Write page miss unprotected
This is a cycle executed when the current memory access cycle is a write cycle and the write protect information corresponding to the current memory address indicates non-write protect, and RAS for the same DRAM bank is asserted. The data is written by early write.
[0202]
2. Write page miss protection
This is a cycle executed when the current memory access cycle is a write cycle and the write protect information corresponding to the current memory address indicates write protect, and CAS is not asserted. Write protection is realized.
[0203]
3. Lead page miss single
This is a cycle executed when the current memory access cycle is a read cycle, and the cache control information corresponding to the current memory address indicates cache invalidity, and RAS for the same DRAM bank is reasserted. Then, a read cycle for reading data from the DRAM bank is executed once.
[0204]
4). Lead page misburst
This is a cycle executed when the current memory access cycle is a read cycle and the cache control information corresponding to the current memory address indicates that the cache is valid, and RAS for the same DRAM bank is reasserted. After that, a burst read cycle for reading a plurality of continuous data from the DRAM bank is executed.
[0205]
Here, the write protect information and the cache control information are decode signals defined for the page accessed this time, and are recorded together with the CPU address for page hit determination for subsequent access.
[0206]
As described above, according to this embodiment, the page hit determination circuit 126 uses the CPU address instead of the DRAM logical address to determine whether the current memory access is the same bank and the same page as the previous memory access. Page hit determination is performed to determine whether or not. Therefore, the address translation operation and the page hit determination operation can be performed in parallel, the page hit determination can be performed at high speed, and the memory access speed can be increased.
[0207]
Further, by holding the memory attribute information together with the CPU address for page hit determination, it is possible to determine the page hit more quickly and determine the next cycle type.
[0208]
【The invention's effect】
As described above, according to the present invention, the page hit determination can be executed at high speed, and the memory access speed can be increased.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.
FIG. 2 is an exemplary block diagram showing memory control logic in a system controller provided in the system according to the embodiment;
3 is a diagram showing a conversion operation from a CPU memory address space to a DRAM logical address space, which is executed by an address conversion circuit included in the memory control logic of FIG. 2;
4 is a diagram showing a DRAM memory map showing a state in which a plurality of DRAM banks provided in the system of the embodiment are rearranged in the DRAM logical address space in order of memory size; FIG.
FIG. 5 is a diagram showing decoding conditions for RAS lines connected to a plurality of DRAM banks provided in the system of the embodiment;
FIG. 6 is a diagram showing decoding conditions for each RAS line employed when the page interleave architecture is realized in the system of the embodiment;
FIG. 7 is an exemplary flowchart illustrating a procedure of an initial setting process for a memory control logic which is executed by an IRT routine when the system of the embodiment is powered on.
FIG. 8 is a diagram showing an example of the types of DRAM banks supported by the system of the embodiment.
FIG. 9 is a diagram showing an example of a memory configuration of a system memory mounted as standard on the system board of the system according to the embodiment;
FIG. 10 is a diagram showing an example of a memory configuration of an additional memory installed in an expansion memory slot provided in the system of the embodiment.
FIG. 11 is a diagram showing an example of another memory configuration of an additional memory installed in an expansion memory slot provided in the system according to the embodiment;
12 is a flowchart showing a procedure of memory size detection processing of each DRAM bank executed in the initial setting processing of the memory control logic of FIG. 7;
13 is a circuit diagram showing an example of a specific configuration of a RAS decoder included in the memory control logic of FIG. 2;
14 is a circuit diagram showing an example of a specific configuration of a row address / column address multiplexer included in the memory control logic of FIG. 2;
15 is a view for explaining row address switching operation of the row address / column address multiplexer of FIG. 14; FIG.
16 is a circuit diagram showing another example of a specific configuration of a row address / column address multiplexer included in the memory control logic of FIG. 2;
17 is a circuit diagram showing an example of a specific configuration of a page hit determination circuit included in the memory control logic of FIG. 2;
FIG. 18 is an exemplary view showing the relationship between memory attribute information managed by the system of the embodiment and a CPU memory address space;
FIG. 19 is a diagram showing a format of memory attribute information in FIG. 18;
20 is a view showing the contents of read attribute information included in the memory attribute information of FIG. 18;
FIG. 21 is a view showing the contents of write attribute information included in the memory attribute information of FIG. 18;
22 is a view showing the contents of DRAM write protect information included in the memory attribute information of FIG. 18;
FIG. 23 is a view showing the contents of caching control information included in the memory attribute information of FIG. 18;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... CPU, 12 ... System controller, 13 ... System memory, 21, 22 ... Expansion memory slot, 31 ... CPU local bus, 33 ... Memory address bus, 41, 42 ... Additional memory, 120 ... Memory control logic, 121 ... Address Conversion circuit 122 ... RAS decoder 123 ... Row address / column address multiplexer 124 ... CAS generation circuit 125 ... Timing control circuit 126 ... Page hit decision circuit 51-56 ... RAS decode circuit 71-79 ... Match detection Circuits 81-89 Mask circuit 91 AND circuit 201, 301 Register file 202 Pattern decoder 203 Row address selector 204-207 Row address start position switching circuit 208 Row address / column address Selec , 302 ... page hit determination CPU address register, 303 ... match determining circuit, 304 ... masking circuit, 305 ... matching determination mask location register.

Claims (4)

A plurality of DRAM banks each assigned a plurality of RAS signals and independently accessible;
The memory area corresponding to each of the plurality of DRAM banks that are discontinuously arranged in the memory address space of the CPU is continuously arranged on the DRAM logical address space so as to be equal to or larger than the page size of the plurality of DRAM banks. Address conversion means for converting a memory address from the CPU into a DRAM logical address in conversion units;
The memory address from the CPU at the previous memory access is held, the memory address is compared with the memory address from the CPU at the current memory access, and if they match, the current memory access is the same bank as the previous memory access. And page hit determination means for outputting a page hit signal indicating the same page;
A RAS decoder that decodes a DRAM logical address output from the address conversion means and determines which DRAM bank to output a RAS signal. When the page hit signal is output, a DRAM page mode access and RAS decoder for RAS signal output control for,
For each of a plurality of memory address areas constituting a memory address space addressable by the CPU, information for designating the type of memory device to which read access is permitted and information for designating the type of memory device to which write access is permitted A memory attribute table in which memory attribute information including
The page hit determination means has means for holding control information for setting the bit position within the memory address to be used for page hit determination set by the CPU for each DRAM bank, and the RAS decoder based on the decoded result and the control information, a memory address from the page hit the saw including a means for changing the bit position in the memory address to be used for the determination, and CPU at the previous memory access Together, information indicating whether or not the memory attribute information in the memory address area corresponding to the memory address designates a different memory device for write access and read access, and the memory access at that time is for write access and read access. Cycle type information that indicates which When the memory device to be accessed is different between the memory access and the read access, the held memory address matches the memory address from the CPU at the time of the current memory access, and the held cycle type information A memory control system that outputs the page hit signal on condition that the current memory access cycle type matches . The memory attribute information further includes write protect information indicating whether or not write protection is performed for each of a plurality of memory address areas constituting a memory address space addressable by the CPU,
The page hit determination means includes
If the current memory access cycle is a write cycle and it is determined that the page hit is a write hit, and the held write protect information indicates non-write protect, the write access is executed by DRAM page mode access. If the current memory access cycle is a write cycle and the held write protect information indicates write protect when it is determined that a page hit occurs, the column address strobe signal is not activated. The memory control system according to claim 1, wherein the type of cycle to be executed next is determined based on a page hit determination result and the held memory attribute information. The memory attribute information further includes cache control information indicating whether or not a caching operation using a cache memory is valid for each of a plurality of memory address areas constituting a memory address space addressable by the CPU,
The page hit determination means includes
If it is determined that this is a page hit, the current memory access cycle is If the cache control information that is held is a cache invalid and the cache control information held indicates that the cache is invalid, the read cycle is executed once by DRAM page mode access and it is determined that a page hit occurs. When the access cycle is a read cycle and the cache control information held indicates that the cache is valid, a page hit is performed so that a burst read cycle for reading a plurality of continuous data is executed by DRAM page mode access. 2. The memory control system according to claim 1, wherein a type of a cycle to be executed next is determined based on the determination result and the held memory attribute information. A plurality of DRAM banks each assigned a plurality of RAS signals and independently accessible;
Address conversion means for converting a memory address from the CPU into a DRAM logical address continuously assigned to the plurality of DRAM banks in a conversion unit equal to or larger than the page size of the DRAM bank;
The memory address from the CPU at the previous memory access is held, the memory address is compared with the memory address from the CPU at the current memory access, and if they match, the current memory access is the same bank as the previous memory access. And page hit determination means for outputting a page hit signal indicating the same page;
A RAS decoder that decodes a DRAM logical address output from the address conversion means and determines which DRAM bank to output a RAS signal. When the page hit signal is output, a DRAM page mode access A RAS decoder for performing RAS signal output control for
For each of a plurality of memory address areas constituting a memory address space that can be addressed by the CPU, information for designating the type of memory device to which read access is permitted and information for designating the type of memory device to which write access is permitted A memory attribute table in which memory attribute information including
The page hit determination means includes
Information indicating whether or not the memory attribute information in the memory address area corresponding to the memory address specifies different memory devices for write access and read access together with the memory address from the CPU at the previous memory access Cycle type information indicating whether the memory access at that time is write access or read access is held, and if the memory device to be accessed differs between write access and read access, the held memory address and this time The page hit signal is output on condition that the memory address from the CPU at the time of memory access matches and the cycle type information held matches the cycle type of the current memory access. Memory control system.

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