JPH09127203A - Logical integrated circuit and failure test method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test the failure of wiring without controlling a logic circuit by determining mismatch of signal between a reset input terminal and FF reset input terminal. SOLUTION: Input signal to a reset input terminal 21 is varied from L to H and from H to L and then the logical value at test output terminal 26 is observed. If reset failure (failure of wiring 30-32) is not present, all input signals to an exclusive OR circuit 25 have identical logical value and the output at terminal 26 goes L at all times. At the time of reset failure, input logical value to the reset terminal R of FF 16-18 connected with failed wiring does not vary and logical mismatch takes place for any one of input signals L, H from the terminal 21. The circuit 25 detects the mismatch and outputs the signal H from the terminal 26 which thereby means the occurrence of reset failure. Consequently, the failure of the wiring 30-32 can be determined by simply varying the input signal from the terminal 21 from L to H or from H to L without controlling the logic circuits 10-15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit, and more particularly to a logic integrated circuit (for example, an application specific IC (ASIC)) having a sequential circuit in the logic integrated circuit.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a configuration around a sequential circuit of a conventional logic integrated circuit. In the figure, 10 to 1
Reference numeral 5 is a logic circuit, 16 to 18 are flip-flops (hereinafter referred to as FFs) forming a sequential circuit, 20 is a clock input terminal, 21 is a reset input terminal, 22 to 24 are output terminals of the logic circuits 13 to 15, respectively. Is the wiring from the reset terminal R of the FF16 to the point a in FIG. 2, 31 is the FF17
Wiring from the reset terminal R to the point b in FIG. 2, 32 is F
The wiring is from the reset terminal R of F18 to point b in FIG.

Conventionally, as test data for performing a functional test of a logic integrated circuit, reset data is usually only operated at the beginning of the test data for stabilizing the operation of each flip-flop at the start of the test, and the test start is started. Even if it is not reset at times, it may operate normally. For example, a 0 stuck-at fault in which the wirings 30 to 32 are short-circuited to GND occurs, and each FF 16 to which a sequential circuit is formed.
It was easy to remain as a reset failure undetected failure such that the reset terminal R of 18 did not function (reset operation did not work).

For this reason, it is necessary to test this reset failure. To test this reset failure,
First, the logic circuits 10 to 12 are controlled from input terminals (not shown) or the like, all the outputs of the logic circuits 10 to 12 are set to "H", and are input to the data terminals D of the FFs 16 to 18, respectively. A rising clock signal is input from the terminal 20 to set the outputs Q of the FFs 16 to 18 to the logical value "H", which is the reverse of the reset state.

Then, a reset signal (reset = “H”) is inputted from the reset input terminal 21 and each FF1
The logic values output from the output terminals Q of 6 to 18 are transmitted to the output terminals 22 to 24 by controlling the logic circuits 13 to 15 from the input terminals (not shown) and the like, and are output to the output terminals 22 to 24. The reset failure can be determined by checking the logical value.

As a judgment of this reset failure, if
When the wirings 30 to 32 of the reset terminal R of any one of the FFs 16 to 18 are out of order, a logic value "H" opposite to the reset state is output from the output terminal and the wiring of the reset terminal R is not out of order. In this case, a discrepancy with the output value in this case occurs, so that a failure in which the reset terminal R does not function is detected. Further, the test of the wiring of the set terminal S of the FF is performed in the same manner as the test of the wiring of the reset terminal R.

[0007]

However, in the conventional logic integrated circuit, the logic circuits 10 to 15 are controlled depending on the number of FFs forming the sequential circuit, the scale of the LSI circuit including the sequential circuit, the complexity of the logic, and the like. Is difficult to do,
There is a problem in that the number of test patterns increases and the time spent for the test increases, which imposes a burden on production.

[0008]

A logic integrated circuit according to the present invention includes a plurality of flip-flops, a plurality of preceding logic circuits connected to the input sides of the plurality of flip-flops, and an output side of the plurality of flip-flops. A plurality of subsequent logic circuits connected to each other, a reset input terminal for inputting reset signals of a plurality of flip-flops, a signal input to the reset input terminal and a signal input to a reset terminal of the plurality of flip-flops are input. An exclusive OR circuit and a test output terminal that outputs the output signal of the exclusive OR circuit are provided, and the signal input to the reset input terminal and the reset terminals of the plurality of flip-flops are input by the exclusive OR circuit. The discrepancy between the generated signals is determined, and the result is output to the test output terminal.

[0009]

1 is a circuit diagram showing the configuration of a sequential circuit peripheral of a logic integrated circuit according to an embodiment of the present invention. In the figure, 25 is an exclusive OR circuit (Exclusive OR gate) whose inputs are connected to the reset input terminal 21 and the reset terminals R of the FFs 16 to 18, and 26.
Is a test output terminal connected to the output of the exclusive OR circuit, and other configurations are similar to those of the conventional example.

Next, the reset failure detection operation of this embodiment will be described. First, the input of the reset input terminal 21 is changed from the logical value “L” to “H” and from “H” to “L”. Then, the logical value output to the test output terminal 26 at this time is observed.

To determine the reset failure, first, a normal circuit without reset failure (in this case, the wiring 30
~ 32 is not a failure), all the signals input to the exclusive OR circuit have the same logical value, so that the output of the test output terminal 26 is always the logical value "L". It

However, if the wirings 30 to 32 have a "L" or "H" failure and a reset failure has occurred,
Since the logical value input to the reset terminal R of the FF to which the faulty wiring is connected does not change, the logical value is either "L" or "H" of the signal input from the reset input terminal 21. A mismatch will occur, and at that time, the output of the exclusive OR circuit 25 becomes "H", and the logical value output from the test output terminal 26 is "H".
Becomes That is, when the logic value "H" is output from the test output terminal 26, it means that a reset failure has occurred.

In this embodiment, the reset input terminal 21
Since the reset failure is determined by the output of the exclusive OR circuit 25 to which the input signal of the above and the signal input to the reset terminal R of each FF 16 to 18 are input, without controlling the logic circuits 10 to 15. , Reset input terminal 2
It is possible to determine the reset failure only by changing the input from 1 to the logical value "L" to "H" and "H" to "L".

In this embodiment, the reset input terminal 21 and the reset R of each of the FFs 16 to 18 are also wired to the exclusive OR circuit 25. However, if the wiring is abnormal such as 0 stuck-at fault. If the error occurs, the failure of the wiring to the exclusive OR circuit 25 can be determined by testing the output signal of the test output terminal 26 and the output signals of the output terminals 22 to 24 in the functional test.

In this embodiment, the failure of the wiring to the reset terminal R of the FF has been described. However, when the FF having the set terminal S is used, the same applies to the failure of the wiring to the set terminal S. , FF that inputs the set signal to the set terminal of the FF and each FF
Alternatively, the signal input to the set terminal S of 1 may be input to the exclusive OR circuit to determine the set failure.

[0016]

As described above, according to the present invention, the exclusive OR circuit determines whether the signals input to the reset input terminal and the signals input to the reset terminals of the plurality of flip-flops do not match. Since the result is output to the test output terminal, the wiring failure from the reset input terminal to the reset terminals of multiple flip-flops can be tested without controlling the logic circuit by the signal output to the test output terminal. It has the effect of being able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration around a sequential circuit of a logic integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration around a sequential circuit of a conventional logic integrated circuit.

[Explanation of symbols]

 10-15 logic circuit 16-18 flip-flop 20 clock input terminal 21 reset input terminal 22-24 output terminal 25 exclusive OR circuit 26 test output terminal 30-32 wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/088 H03K 19/00

Claims (8)

[Claims] 1. A plurality of flip-flops, a plurality of logic circuits connected to either the input side or the output side of the plurality of flip-flops, and a reset input terminal for inputting a reset signal of the plurality of flip-flops. In the failure test method of the logic integrated circuit having, the reset signal is intermittently input to the reset input terminal, and the signal input to the reset input terminal and the signal input to the reset terminals of the plurality of flip-flops are A failure test method for a logic integrated circuit, comprising determining a mismatch and testing a failure of a wiring from the reset input terminal to the reset terminals of the plurality of flip-flops. 2. A plurality of flip-flops, a plurality of pre-stage logic circuits connected to the input sides of the plurality of flip-flops, a plurality of post-stage logic circuits connected to the output sides of the plurality of flip-flops, In a failure test method for a logic integrated circuit having a reset input terminal for inputting reset signals of a plurality of flip-flops, the reset signal is intermittently input to the reset input terminal, and a signal input to the reset input terminal and A failure of a logic integrated circuit characterized by determining a mismatch of signals input to reset terminals of the plurality of flip-flops and testing a failure of a wiring from the reset input terminal to the reset terminals of the plurality of flip-flops. Test method. 3. A plurality of flip-flops, a plurality of logic circuits connected to either the input side or the output side of the plurality of flip-flops, and a reset input terminal for inputting a reset signal of the plurality of flip-flops. In a failure testing method of a logic integrated circuit having a set input terminal for inputting set signals of the plurality of flip-flops, the reset signal is intermittently input to the reset input terminal, and the reset signal is input to the reset input terminal. Based on the disagreement between the signal and the signal input to the reset terminals of the plurality of flip-flops, a failure of the wiring from the reset input terminal to the reset terminals of the plurality of flip-flops is tested, and the set input terminal is input. A set signal and the set terminals of the plurality of flip-flops. Fault test method of a logic integrated circuit, characterized in that to determine the mismatch issue, testing the failure of the wiring from the set input terminal to a set terminal of said plurality of flip-flops. 4. A plurality of flip-flops, a plurality of pre-stage logic circuits connected to the input sides of the plurality of flip-flops, a plurality of post-stage logic circuits connected to the output sides of the plurality of flip-flops, In a failure testing method of a logic integrated circuit, comprising: a reset input terminal for inputting reset signals of a plurality of flip-flops; and a set input terminal for inputting set signals of the plurality of flip-flops, wherein the reset signal is applied to the reset input terminal The signals are input intermittently, and the discrepancy between the signal input to the reset input terminal and the signal input to the reset terminals of the plurality of flip-flops is discriminated, and from the reset input terminal to the reset terminals of the plurality of flip-flops. Test the wiring for failure, and set signal input to the set input terminal and A failure of a logic integrated circuit characterized by testing a failure of a wiring from the set input terminal to the set terminals of the plurality of flip-flops based on a mismatch between signals input to the set terminals of the plurality of flip-flops. Test method. 5. A plurality of flip-flops, a plurality of logic circuits connected to either the input side or the output side of the plurality of flip-flops, and a reset input terminal for inputting a reset signal of the plurality of flip-flops. An exclusive OR circuit to which a signal input to the reset input terminal and a signal input to the reset terminals of the plurality of flip-flops are input, and a test output terminal that outputs an output signal of the exclusive OR circuit A logic integrated circuit comprising: 6. A plurality of flip-flops, a plurality of pre-stage logic circuits connected to the input sides of the plurality of flip-flops, a plurality of post-stage logic circuits connected to the output sides of the plurality of flip-flops, A reset input terminal for inputting reset signals of a plurality of flip-flops; an exclusive OR circuit to which a signal input to the reset input terminal and a signal input to reset terminals of the plurality of flip-flops are input; And a test output terminal for outputting an output signal of the exclusive OR circuit. 7. A plurality of flip-flops, a plurality of logic circuits connected to either the input side or the output side of the plurality of flip-flops, and a reset input terminal for inputting a reset signal of the plurality of flip-flops. A set input terminal for inputting a set signal of the plurality of flip-flops, a first exclusive logic to which a signal input to the reset input terminal and a signal input to a reset terminal of the plurality of flip-flops are input An OR circuit, a second exclusive OR circuit to which the signal input to the set input terminal and the signal input to the set terminals of the plurality of flip-flops are input, and the first exclusive OR circuit First to output the output signal of
And a second output terminal for outputting the output signal of the second exclusive OR circuit.
And a test output terminal of the logic integrated circuit. 8. A plurality of flip-flops, a plurality of pre-stage logic circuits connected to the input sides of the plurality of flip-flops, a plurality of post-stage logic circuits connected to the output sides of the plurality of flip-flops, A reset input terminal for inputting reset signals of a plurality of flip-flops, a set input terminal for inputting set signals of the plurality of flip-flops, a signal input to the reset input terminal and a reset terminal of the plurality of flip-flops A first exclusive OR circuit to which an input signal is input; and a second exclusive OR circuit to which the signal input to the set input terminal and the signal input to the set terminals of the plurality of flip-flops are input An OR circuit and a first output circuit for outputting an output signal of the first exclusive OR circuit
And a second output terminal for outputting the output signal of the second exclusive OR circuit.
And a test output terminal of the logic integrated circuit.