JP3218294B2 - Logic integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit,
In particular, the present invention relates to a logic integrated circuit that can obtain a high fault detection rate with a small number of test patterns by applying a scan path.

[0002]

2. Description of the Related Art A conventional logic integrated circuit is provided with a scan path as one of the measures for facilitating a test (fault detection test) so that a high fault detection rate can be obtained by a scan operation even if the number of test patterns is small. Was.

[0003]

In this conventional method, it is essential to provide a function for controlling the scanning operation on the tester side, and even if the tester has a scanning operation function, the test pattern validity to be used is checked. However, there is a problem that the actual situation is that it is difficult to verify and that there is no effective means.

Accordingly, although the present invention applies the scan path method, the validity of the test pattern can be easily verified using a method different from the normal scan path operation, and a test pattern having a high failure detection rate can be obtained. It is an object of the present invention to provide a logic integrated circuit that can be easily manufactured.

[0005]

According to the present invention, there is provided a logic integrated circuit comprising: an execution control signal for selectively controlling three execution modes of a normal mode, a shift mode, and a test mode; An exclusive OR circuit that inputs a signal appropriately selected from signals that are difficult to detect in the external output terminal or two or more signals that are appropriately selected from signals that are difficult to detect in the external output terminal A data input of a normal operation is selected in a normal mode by a multi-input exclusive-OR circuit for inputting a signal and the execution control signal.
A selector circuit for selecting the output of F and selecting the output of the exclusive OR circuit or the multi-input exclusive OR circuit in the test mode.

[0006] Or, failure detection is difficult and usually "1"
Only two or more frequent signals are appropriately collected and input to an AND circuit, and the output of the AND circuit is input to an exclusive OR circuit or a multi-input exclusive OR circuit.

[0007] Or, it is difficult to detect a failure and usually "0"
Only two or more frequently occurring signals are appropriately collected and input to an OR circuit, and the output of the OR circuit is input to an exclusive OR circuit or a multi-input exclusive OR circuit.

[0008]

According to the above arrangement, when the test mode is executed by the execution control signal, the exclusive OR circuit has the F / F at the preceding stage.
An output of F and a signal appropriately selected from signals that are difficult to detect in the external output terminal check are input. In the case of a multi-input exclusive OR circuit, a signal is appropriately selected from signals that are difficult to detect in a fault. The received two or more signals are input, and the output is selected by a selector circuit to be a scan path output.

Further, the exclusive OR circuit or the multi-input exclusive OR circuits, and is difficult to fault detection, only frequent signal is normally "1", and logical processing collected appropriately 2 or more Te or and difficult to fault detection, since the input to the processing logic sum collected by frequent signal is normally "0" as appropriate 2 or more, the check of the external output terminal of the failure detection difficult internal circuit Signal failure detection becomes possible.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a logic integrated circuit diagram of a first embodiment of the present invention.

In the figure, a random logic circuit 1 shows a scan path circuit and a circuit other than the main part of the present invention. The clock signal 3 and the output of the selector circuit 4 are input to a flip-flop (hereinafter referred to as F / F) 2.
The selector circuit 4 selectively outputs the data signal 6 in the normal mode by the execution control signal 5 for selecting three execution modes of the normal mode, the shift mode and the test mode, and selectively outputs the input signal from the F / F2 in the shift mode. In the test mode, the input signal from the exclusive OR circuit 7 is selectively output.

The exclusive OR circuit 7 outputs the output of the F / F2,
A signal 8 which is an internal signal of the random logic circuit 1 and which is appropriately selected from signals whose failure is difficult to detect by checking the external output terminal 9 is input.

Next, the operation of this embodiment will be described. In the normal mode (when performing a general operation), the F / F 2 takes in the data signal 6 selected by the selector circuit 4 at the timing of the clock signal 3 and performs the original functional operation. Shift mode (mode for setting desired data to F / F2, extracting contents of F / F2, etc.) F
/ F2 captures the output signal of the preceding F / F2 selected by the selector circuit 4 according to the timing of the clock signal 3. By repeating this for the number of F / F2,
Desired data can be set in all F / F2 or all F / F2
/ F2 can be extracted. In the test mode (mode for testing for the presence or absence of a failure), the F / F 2 outputs the output of the preceding F / F 2 and the internal signal of the random logic circuit 1 through the selector circuit 4 and the exclusive OR circuit 7 in accordance with the timing of the clock signal 3. The result of the exclusive OR with the signal 8 that is difficult to detect is selected as appropriate. As a result, the information of the signal 8, which is normally difficult to detect a failure, is also taken out on a scan path after a predetermined clock and shifted to be taken out from the final stage F / F2 to an external terminal without fail. Tested for accuracy.

FIG. 2 shows a logic integrated circuit according to a second embodiment of the present invention.

Since the second embodiment is almost the same as the first embodiment, the description will focus on the parts that are particularly different.
The selector circuit 4 selects and outputs the input signal from the multi-input exclusive OR circuit 17 in the test mode, and operates the same as in the first embodiment in other modes. The multi-input exclusive-OR circuit 17 inputs the output signal of the previous stage F / F 2 and the internal signal of the random logic circuit 1 and two or more appropriately selected failure-detectable signals 18, and outputs an error of all inputs. A detection parity signal is output. The number of the signals 18 does not need to be a fixed number, and may be one at some places.

FIG. 3 is a diagram showing a part of a logic integrated circuit diagram showing a third embodiment of the present invention.

In the figure, the output of the NAND gate 21 is normally "1" frequently (assuming that the frequencies of "1" and "0" of all five inputs to the gate are equal, "1" output with a probability of 31/32). ) And the output of the OR gate 22 also has a high frequency of "1". Two or more signals which are output from such gates and are difficult to detect at the external output terminal 9 even if the output has a failure are collected by the AND gate 23 and input to the exclusive OR circuit 7 as a takeout signal 8. In this case, AN
D gate 23 is the same even if it is a NAND gate,
The effect remains the same.

FIG. 4 is a diagram showing a part of a logic integrated circuit diagram showing a fourth embodiment of the present invention.

In the figure, the output of the AND gate 31 is normally "0" frequently, and the output of the NOR gate 32 is also frequently "0". An OR gate 33 collects two or more signals output from such gates and the like, which are difficult to detect even if there is a failure in the output, and inputs the signal 8 to the exclusive OR circuit 7. In this case, the OR gate 33 is N
The same applies to the OR gate, and the effect is not changed at all. In the third and fourth embodiments of FIGS. 3 and 4, the signal 8 taken out to the exclusive OR circuit 7 is an input. Circuit 17
It is clear that the extraction signal 18 may be input to the second input terminal.

[0021]

As described above, according to the present invention, a signal inside a logic circuit, which is difficult to detect a failure at an external output terminal, is inserted into a scan path path through an exclusive OR circuit to perform a shift operation. Checking the F / F output at the final stage of the campus has the effect of enabling failure detection with a very high probability.

[Brief description of the drawings]

FIG. 1 is a logic integrated circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a logic integrated circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a logic integrated circuit diagram according to a third embodiment of the present invention.

FIG. 4 is a logic integrated circuit diagram according to a fourth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Random logic circuit 2 Flip-flop 3 Clock signal 4 Selector circuit 5 Execution control signal 6 Data signal 7 Exclusive-OR circuit 8, 18 Failure-detection difficult signal 9 External input terminal 17 Multiple-input exclusive-OR circuit 21 NAND gate 22 , 33 OR gate 23, 31 AND gate 32 NOR gate

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28 G06F 11/22 H01L 21/66

Claims (3)

(57) [Claims] 1. An execution control signal for selectively controlling three execution modes of a normal mode, a shift mode, and a test mode in a synchronous sequential circuit;
Failure detection difficult signal in the output and the external output terminal check
An exclusive-OR circuit for inputting a data signal during normal operation in the normal mode by the execution control signal, selecting an output of the F / F in the previous stage on the scan path in the shift mode, and selecting the output in the test mode. logic integrated circuit, characterized in that a selector circuit for selecting the output of the exclusive OR circuit. 2. A input to the AND circuit by two or more collected frequent signal which is difficult to fault detection and usually "1", the output of the logical product circuit to one of the exclusive OR circuit 2. The logic integrated circuit according to claim 1, wherein the input is the other input and the other input is the output of the F / F at the preceding stage on the scan path. 3. Enter only high failure detection frequent is difficult and usually "0" signal to two or more collected OR circuit, the output of said logical Liwa circuit to one of the exclusive OR circuit 2. The logic integrated circuit according to claim 1, wherein the input is the other input and the other input is the output of the F / F at the preceding stage on the scan path.