JPH09120991A - Forming metal fills and interconnects for narrow apertures using a crystallographically oriented liner layer - Google Patents

Abstract

(57) Abstract: Aluminum sputter, which has a large aspect ratio formed in a dielectric layer and is particularly effective for filling a contact, and also effective for forming an interconnect having high resistance to electromigration.・ Provide a process. The liner layer is deposited by high density plasma PVD, such as is performed using an inductively coupled plasma. The first underlayer of the liner layer is a Ti layer. The second lower layer comprises TiN. The third lower layer contains Ti, but T
It is desirable to gradually change from iN to Ti. The aluminum layer on top of the liner layer is 320-50 depending on the liner layer.
It makes it possible to carry out the hottest part of the aluminum deposition at relatively low temperatures in the range of 0 ° C, preferably in the range of 350-420 ° C, but at the same time a narrow plug
The holes will also be filled and the TiN need not be annealed to form an effective barrier to diffusion into the silicon.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to the manufacture of semiconductor devices. In particular, the invention relates to filling contacts, vias, or other apertures in an insulating layer in a semiconductor integrated circuit with metal and depositing metal lines interconnecting the contacts and vias.

[0002]

BACKGROUND OF THE INVENTION Modern integrated circuits (ICs) increasingly require vertical interconnects that extend through apertures etched in intervening dielectric layers. I
Reducing the lateral dimension of C requires increasing the aspect ratio of the vertical interconnect, that is, making the interconnect narrower and deeper. It is also necessary to wire these contacts and vias to each other by interconnecting the wire lines in the horizontal direction to achieve the required complex electrical paths. A typical fabrication process is to deposit a dielectric layer on a horizontal interconnect layer of semiconductor or patterned metal, and photolithographically deposit a plug hole or other structure from above the semiconductor or horizontal interconnect layer. Forming the dielectric layer so that it extends to its bottom overlying the layer, and
It is necessary to somehow deposit a conductive material on the plug hole, ie the dielectric layer, and at the same time deposit a material for the horizontal interconnect on the dielectric layer.

Whether it is a memory or a logic circuit,
Alternatively, as with any other device, a typical integrated circuit requires a semiconductor silicon substrate in which various regions of different conductivity, doping type, or doping order are formed. Also, the order of doping must be strictly controlled. As described above, one or more dielectric layers are deposited on a silicon substrate, holes are formed in each layer by etching, and then the holes are filled to form a silicon substrate, or Any wiring pattern layer formed above the deposited dielectric layer will, in any event, form vertical interconnections to the underlying layers. The upper metal wiring layer is typically deposited at the same time as the vertical interconnects below it. When the bottom is connected to a silicon substrate by a vertical interconnect, it is called a contact because it makes contact with the silicon substrate, and between the metal and the silicon it avoids excessive contact resistance, so it has a suitable stable contact. Ohmic resistance must be formed. If this interconnection connects its bottom with the metal in the multi-layer metallization structure, it is called. Contacts or vias may also be referred to as plugs or vertical interconnects, but interconnects are assumed to be horizontal interconnects unless otherwise specified. And contacts generally minimize their surface area,
It is round or almost square. However, other holes
It may be formed in the shape of a trench having a narrow width and a long length, and these trenches need to be further filled with a metal.

When the aspect ratio of the holes to be filled is large,
Severe problems will arise. Aspect ratio is the depth-to-width ratio of plugs formed in a dielectric layer or other type of layer. In the case of a trench, the width that determines the aspect ratio is the minimum lateral dimension. As the density of components in integrated circuits increases, the width of contacts, vias, trenches, and other apertures decrease, but the minimum dielectric thickness to electrically isolate the stack layers in the integrated circuit. Is required, so its depth does not become too shallow. Therefore, the aspect ratio is increasing. Older technologies were generally limited to filling contacts, vias, and trenches with aspect ratios of 0.5: 1 or less. Modern technologies utilize aspect ratios up to about 2: 1. Advanced technology must adapt to aspect ratios of 5: 1 or greater.

As usual, if the majority of the conductive material filling the plugs or trenches is metal, then the metal may also react with the underlying layers or be caused by metal-silicon contacts. If there is the potential for harmful interdiffusion, the aperture must be coated with a diffusion barrier layer prior to metal deposition, and the barrier layer is filled with a thicker amount of metal. . The barrier layer is currently titanium nitride (Ti) because it has moderate conductivity and is compatible with both silicon and aluminum when subjected to some additional treatment.
N) is the most commonly used.

In the hole-filling process, almost inevitably,
A metal layer of laterally varying thickness will be deposited over the dielectric layer and the holes. As a result, usually
It will be necessary to planarize the metal layer as part of the hole filling process so that subsequent processing can be performed on relatively planar surfaces. A corrugated substrate can defocus the projected pattern, so a flat surface is especially required for photolithography. A flat surface is also desirable to provide underneath the thin interconnect lines that tend to break when placed over large vertical steps.

Physical vapor deposition (PVD) is a well-known method in integrated circuit fabrication, both for filling the apertures with metal and for depositing planar metal for horizontal interconnects. Applied as an example of the latest PVD system in Santa Clara, California
Materials, Inc. Available from End
There is the uraRPVD System. Standard PVD
In the process, a metal target of the metal composition for which deposition is desired to be placed is placed in the plasma reaction chamber in relatively close proximity to the wafer on which the metal is to be deposited. The space between the target and the wafer is filled with decompressed argon. By applying a sufficiently negative DC bias to the wafer on the metal target, argon gas is released and the argon gas
A plasma is formed. The resulting positive argon ions in the plasma are strongly attracted to the negatively biased target and impact the target with high energy, causing atoms or atomic clusters of the target material to be ejected from the target. Will be
That is, the target is sputtered.
At least some of the sputtered atoms are substantially deposited on the wafer by an impact process. Examples of sputtered metals are aluminum and titanium.

PVD is a process called reactive sputtering in which titanium is sputtered from a nearly pure titanium target and reacts with nitrogen gas (or plasma) that fills the intervening space between the target and the wafer.
It is used to perform sputter deposition of compounds such as TiN. The titanium atoms at these relatively low pressures are surface-reacted with nitrogen after being deposited on the wafer, so the wafer will be sputtered with TiN. For this process, see 19
Solid State Technology in January 1993
No. 73-76, 78, 79, 82 by Pramanik et al., "Barrier Me.
tals for UL. SI: Deposition
and Manufacturing ".

Returning specifically to the sputter deposition of aluminum on the plug aperture, FIG. 1 shows a substrate 100 which is assumed to comprise a surface portion of crystalline silicon or polysilicon. By overlaying the dielectric layer 102 on the substrate 100, a field oxide or interlevel dielectric is formed. In the latest silicon processing,
Dielectric layer 102 is typically formed by thermal growth of SiO ₂ or plasma enhanced chemical vapor deposition (PECVD), although the use of silicate glass, as well as other insulators such as organic dielectrics. Is also possible.

A patterned upper metal interconnect horizontal plane that allows electrical access through the dielectric layer 102 is formed over the dielectric layer 102 and is used for silicon, such as the source or drain of a MOS transistor. In order to make contact with a specific limited part of the board,
The contact hole 104 is formed by photolithography, and is further etched into the dielectric layer 102 to extend to the silicon substrate 100.
Alternatively, the substrate 100 could be the lower metal interconnect horizontal, in which case the holes 104, called via holes, would be the lower metal horizontal dielectric layer 11.
Since the metal line is formed so as to cover the metal line formed on the 0, the metal line and another metal line in the upper metal horizontal plane are in electrical contact with each other. As yet another alternative, a trench aperture can be formed in the dielectric layer 102, which aperture extends a relatively long distance in the plane, out of the example, but shown. As described above, the width is relatively narrow, resulting in a large aspect ratio.

FIG. 2 shows the result of the standard low temperature aluminum sputtering performed on the contact hole 104 having a relatively large aspect ratio. The PVD process forms a flat aluminum layer 106 over the horizontal portion of the dielectric layer 102. But standard PV
In the case of D, a nearly isotropic bombardment pattern of aluminum atoms occurs, and in the low temperature process, the sputtered aluminum will adhere to the wafer relatively close to the collision position. As a result, the aluminum layer 106 will form an overhang 108 near the upper corner 110 of the contact hole 104. Once formed, the overhang 108 shields the bottom wall 112 of the contact hole 104, preventing the hole from being filled by significant deposition by direct sputtering. The lower part of the sidewall 114 of the contact hole 104 is not oriented suitable for deposition by an isotropic pattern.

If the standard PVD process continues, overhang 108, as shown in the cross-sectional view of FIG.
Merge with each other to form a bridge 112 over the contact hole 104, which causes a void in the aluminum deposited in the contact hole 104. Although the effect is exaggeratedly shown in FIG. 3, the inclusion of voids lowers the contact conductivity and introduces a reliability problem. Also, as is clear from FIG. 3, the recesses 116 are likely to be formed in the aluminum layer sputter deposited on the contacts. Even if the formation of voids 114 is avoided, the planarity of the deposited metal is still inadequate.

When the aspect ratio is 1: 1 or slightly higher, the void and planarization problems can be solved by the reflow process. Aluminum tends to move or flow at temperatures near or above 480 ° C, and minimizing surface energy causes aluminum to move and fill non-planar areas, resulting in complete contact. , And the aluminum layer 106 is planarized, as shown in FIG. 4, but the residual recess 118 will probably remain. By maintaining the temperature of the substrate 100 at 480 ° C. or higher, reflow can be continuously performed during sputter deposition. Alternatively, a high temperature reflow can be performed after the low temperature PVD process.

A typical Al hole-filling PVD deposition of a cold hot process, which will be described in more detail below, first requires a short, high power, low temperature seed layer deposition. PVD deposition of the remaining layers is then performed for a long time with low power and high temperature. The temperature in the latter step is sometimes called the reflow temperature. All aluminum was deposited at low temperature, then
It is possible to reflow the deposited layer at high temperatures without simultaneously depositing any more aluminum, but this process is time consuming and introduces void-like discontinuities in the intermediate structure. there is a possibility.

However, reflow is not a complete solution. First, the reflow temperature tends to be rather high, consuming most of the heat budget for complex chips. In fact, the required reflow temperature is
It may eliminate some low temperature materials contained in already formed layers. Advanced dielectrics such as fluorinated silicon oxide or organic polymers such as polyimide or paralene require maximum processing temperatures below 400 ° C. Second, the reflow cannot avoid voids if the plug becomes too narrow, such as an aspect ratio of 2: 1 or more, so the exemplary geometry is marginal, reflow has utility. .

Reflow cannot fill a plug having a large aspect ratio. This is because such geometries prevent full deposition of material on the plug holes prior to strong shadowing. The high temperature of the reflow process also has the effect of bundling small amounts of aluminum into hemispherical grains. The grains are of a size sufficient to result in a smooth film that evenly covers the surface by coalescing before effectively closing the plug holes,
It will never grow. Wetting can be described in relation to the relative magnitude of the surface tension of the free surface of aluminum and the surface tension between the aluminum and the substrate. Aluminum wets Ti well and TiN reasonably well, but poorly with SiO ₂ . Above 250 ° C, aluminum dewetting on SiO ₂ occurs, but the exact temperature depends on initial conditions among other parameters. That is, aluminum causes dewetting below the temperature at which aluminum flows, so reflowing aluminum is easy by separating the wetting and flowing situations unless further steps are taken. Be blocked by.

One of the processes intended to overcome this problem in the narrow plug filling problem is called coherent deposition. Particles of metal, such as aluminum, sputtered from the target are passed through a collimator with a vertical aperture having a fairly large aspect ratio. As a result, only particles that have moved substantially perpendicular to the major plane of the collimator and thus the major plane of the substrate are free to pass through the collimator. That is, the isotropic impact pattern of the sputtered particles is altered to a nearly vertical pattern, allowing the particles to penetrate deeper into the aperture without forming shadowing overhangs. However, this process is less efficient because the rest of the particles will stick to the sides of the collimator aperture and to the flat matrix portion of the collimator that forms the aperture, losing much of the sputtered aluminum. bad. The associated process, called long throw, increases the separation between the target and the substrate so that the PVD trajectory is more vertical. However, since long-throw PVD uses only particles that are nearly vertically sputtered, its sputter rate decreases proportionally.

In a combined process of coherent deposition and reflow, an initial coherent deposition of aluminum is performed at a relatively low substrate temperature, eg 150 ° C., to form a seed layer in the plug holes. It At that temperature, reflow is less likely to occur, and the atoms stick to the first colliding position of the plug bottom 112 (see FIG. 2). Due to the parallelization, the overhang 108 does not occur. The geometry for collimated beam deposition on the sidewalls 114 is not preferred, but considering backscattering from the plug bottom 112 is sufficient to produce a thin, fairly uniform layer.

Collimating low temperature PVD does not continue long enough to fill plug holes due to its uneconomical deposition rate. Instead, after a stable seed layer is deposited in the plug hole, the wafer will
From the coherent PVD chamber to the standard isotropic (ie
Transferred to a (non-coherent) PVD chamber, a standard PVD process performs isotropic deposition of aluminum at a high rate and the substrate temperature eventually rises to a temperature sufficient for reflow of the deposited aluminum. The newly deposited aluminum wets the seed layer that has already been deposited, so the deposited aluminum simply flows as a plug-filling layer without forming voids, smoothing the exposed layer to a nearly flat surface. To

It has been found that it is possible to obtain very similar results in a cold hot standard isotropic PVD process in which both a seed layer and a high temperature reflow layer are sequentially deposited.

As an example of achievable results, when using reflow to fill an aperture of 1.2 μm depth and an aspect ratio of about 1: 1 with aluminum, a substrate temperature of 480 ° C.
If so, the aluminum will planarize in about 3-4 minutes. However, when the width of the 1.2 μm deep plug was reduced to 0.5 μm or less, that is, when the aspect ratio was 2: 1 or more, the reflow limited the effectiveness. Even with the initial plug deposition by coherent PVD, a standard isotropic deposition process performed at an acceptable low reflow temperature takes too long to fill high aspect ratio holes.

Increasing the substrate temperature during high temperature deposition promotes and accelerates aluminum planarization, but when the substrate becomes too hot, the seed layers coalesce into globules, forming a conformal film layer. Prevent. Furthermore, P
Above a certain substrate temperature for VD, other materials that have already been deposited can be dimensionally distorted or thermally degraded.

Another known method of filling high aspect ratio holes is to ionize at least some of the atoms sputtered from the target and then electrically attract the ionized target atoms to the substrate. Will be required. According to the electric field controlled movement of sputtered ions,
Adjustments to the electric field allow the sputtered atoms or clusters to move approximately perpendicular to the substrate plane. This causes the sputtered material to reach the bottom of the plug hole as well as the bottom of the sidewalls and will not collect at the upper edge of the plug hole.

For example, in US Pat. No. 5,178,739, Barnes et al. Provide a hollow cylindrical sputter target located between an edge sputter target and a substrate, all of which are contained within a vacuum chamber. Has been
A sputter deposition system is described. A magnet is placed outside the vacuum chamber, but adjacent the cylindrical target, to increase the amount of material sputtered from the target by increasing the density of the argon plasma adjacent the cylindrical target. ing. RF power is inductively coupled into the vacuum chamber between the target and the wafer to create a plasma adjacent to the target. When a high level of RF power is coupled into the plasma, a high density plasma (HDP) is created, increasing the portion of the target atoms that will be ionized during transfer to the wafer. The pedestal supporting the wafer, and thus the wafer, is electrically DC biased to attract the ionized target atoms. The bias amount of the wafer determines the energy and directivity when the target atom collides with the wafer. Therefore,
The design of the ionized PVD process produces a small angular divergence of the ionized target atoms after passing through the plasma sheath adjacent to the wafer, which uniformly fills the bottom of the high aspect ratio, plug-like aperture. It is given as you can. As described below, other methods can be used to implement the HDP-PVD process.

As is known, it is possible to fill deep holes by ionizing deposition of metals, but this technique clearly has a lower deposition rate than standard PVD, so its economy of use. Loss of power, higher power requirements, and the device is more expensive than standard PVD devices. Despite these shortcomings, many people have found that ionizing PVD is required to fill holes with aspect ratios greater than about 2: 1, and other techniques such as standard PVD and coherent PVD followed by reflow. Then
We believe that we cannot meet the demands of the industrial world, which continues to shrink the IC line width.

A further problem arises when the aluminum filling the contact hole is a contact that needs to make electrical contact with the underlying silicon. When aluminum and silicon are in direct physical contact, aluminum diffuses into the silicon and severely disturbs its semiconductor properties. Therefore, a barrier layer must be formed between the silicon and the contact filler. A typical solution is to deposit a Ti / TiN barrier layer in the contact holes before filling the plug holes with aluminum. However, Ti / TiN
The barrier layer is deposited by PVD, but the resulting TiN is relatively porous so that aluminum can still diffuse into it. as a result,
PV in an oxygen-containing environment, as disclosed by Ngan et al. In US Pat. No. 5,378,660.
Ti / TiN layer by D deposition at 450 ° -480 ° C,
Alternatively, if possible, it was common practice to anneal at a somewhat higher temperature. By this process, T
Oxygen is "stuffed" into the iN micropores, which prevents diffusion of aluminum.

Typically, a layer of Ti or a Ti compound such as TiN will wet the aluminum so that it will not form beads on it and will more easily flow on it. Wetting facilitates the filling of narrow plug holes at moderate temperatures. However, if TiN deposited by PVD is packed with oxygen, its wetting properties are significantly degraded. To avoid this effect, Ong described in US Pat.
It is proposed to deposit another wetting layer of Ti or a Ti-containing material on top of the iN barrier layer. This process is more fully shown in the flow chart of FIG. In step 120, standard PV
The D process is used to first deposit a Ti layer and then a TiN layer thereon. In step 122, the wafer is generally moved to an independent anneal chamber and annealed in an oxygen environment. Step 1
At 24, the wafer is returned to the PVD chamber and a Ti layer sputter deposited. At step 126, the wafer is sent to another PVD chamber, where a sputter deposition of an aluminum layer is performed in a first cold step, followed by a hot reflow step.

The Ong process appears to provide sufficient hole filling for the currently contemplated plugs and contacts. However, the process is overly complex and requires at least two PVD depositions of Ti or TiN split by annealing in oxygen. It would be highly desirable to provide a simpler process for filling high aspect ratio plugs.

For many applications, such as vertical interconnects, the aluminum deposited to fill the contacts or fills is also simultaneously deposited on the planar surface of the dielectric layer 102. Not shown but usually TiN
Once the anti-reflective coating has been deposited by
This thin aluminum layer is photolithographically patterned as shown in the orthographic view of FIG. 6 and has a predetermined shape, such as an exemplary interconnect 130 connecting two underlying contacts or 132,134. Although the wiring patterns of (1) and (2) form interconnection lines that link different elements, one or both of 132 and 134 can be connected to an overlying layer.

In the case of advanced integrated circuits, the wiring pattern is
It can be extremely dense. Therefore, the interconnection lines are relatively thin. However, due to its fineness, the required level of current flowing through the interconnect between the electrical elements results in a relatively high current density in the interconnect. It is a well-known problem that the high current density in aluminum causes the electromigration of aluminum away from the hot spot, such as that caused by localized small defects 136. But,
This movement removes material from the hot spot 136, thus reducing the cross-sectional area of the interconnect at that point and further facilitating electromigration. As shown in FIG. 7 in an orthographic view, electromigration causes hot spots around the small defect 136 to appear in the interconnect 130.
Will result in a broken point 138 of the
The electrical connection between the two plugs 132,134 can be destroyed. Therefore, electromigration introduces a failure mechanism that results in the aluminum interconnect being broken after a period of use.

As is well known, the deposition of aluminum on TiN with some type of crystallographic orientation results in:
Electric transfer is reduced. Proceedings IEEE VMIC Confe
rence, June 27-29, 1995 (104/95/0443), p. 443, `` The e
ffect of reactive-sputtered TiN on electromig
"Ration of Al alloy metallization" shows these results by Kim et al. Journal of Ele
ctronic Materials, vol.22, 1993, pp.589-596 `` Relati
onship Between Texture and Electromigration L
"Ifetime in Sputtered Al-1% Si Thin Films" provides a thorough study of its impact by Campbell et al. Journal of Applied Physics, vol.7
9, 1996, pp.2409-2417, `` The role of texture in
the electromigration behavior in pure aluminu
In "m films," Knorr et al. relate electromigration to the crystallographic orientation of deposited aluminum films. Of note, according to Knorr et al.
The point is that the ion content in one of the methods for depositing aluminum is 1 to 2%. Journal of Applied
Physics, vol.74, 1993, pp. 5391-5394, `` Correlation
between stress voiding of Al (Si) (Cu) metallizat
ions and crystal orentation of alumimum grain ''
Describes a similar dependence on crystallographic orientation for different failure modes by Kordic et al. Regardless, whatever plug fill process is developed, it is highly desirable to be able to integrate it with the planar process and satisfactorily reduce electromigration in the interconnect.

[0032]

SUMMARY OF THE INVENTION It is therefore an object of the present invention, inter alia, to provide a method of filling contacts, vias and other apertures having a large aspect ratio with metal or other material.

Another object is to provide such a method which is economical and which exhibits a high deposition rate.

Yet another object is to provide such a hole filling process that is compatible with the co-deposition of horizontal metal interconnect planes.

Yet another object is to provide a method of depositing a planar metal layer of excellent crystallographic quality.

The above and other objects will become apparent upon an understanding of the specification and claims.

[0037]

The present invention is particularly useful for filling high aspect ratio apertures and for depositing planar metal layers that will later form interconnects. It can be summarized as a method of performing metal deposition by (physical vapor deposition). This process is preferably standard PVD, which results in high deposition rates.
Included is depositing the liner layer by a PVD process utilizing high density plasma (HDP) followed by PVD deposition of aluminum utilizing the process.
The liner layer includes 1-3 unique underlayers. The first underlayer, which is preferably a refractory metal such as Ti, is deposited, especially when the metal is connected to the underlying silicon, and contains Ti. The second important layer is
Includes refractory compounds, especially refractory nitrides such as TiN, which, when deposited by HDP-PVD, will form smoother, denser crystalline structures. The third lower layer contains an upper portion of a refractory metal such as Ti, which can be graded from TiN in the lower portion. It performs two functions. By forming it, the spatter for the next wafer
The target is cleaned and its refractory metal surface facilitates reflow within the narrow aperture. To fill the holes, in a two-step process,
That is, standard PVD deposits the interconnect metal, where aluminum is desirable in today's applications, in a first cold deposition and then a hot deposition, but at relatively low temperatures. It is possible to work in one or two rooms within range. The resulting crystallographic properties of aluminum enhance its resistance to electromigration. In addition, the HDP TiN layer followed by Al deposition does not require planarization and may be applied to other structures that benefit from enhanced resistance to electromigration due to the improved crystallographic structure. Is possible.

[0038]

It has been discovered that filling a plug having a high aspect ratio can be facilitated by pre-coating the interior of the plug hole or other aperture with a liner layer. Liner deposition is performed by physical vapor deposition (PVD) using high density plasma. The so-formed liner layer is characterized by its strong crystallographic orientation, high density, surface smoothness, and increased wettability with respect to post-deposited metals such as aluminum. The liner layer is a standard P for filling the aperture.
The VD process promotes the flow of the deposited material and the filling process can be carried out at relatively low temperatures, significantly below 500 ° C and even below 400 ° C. Preferably, the liner layer is formed under the titanium nitride. No oxygen anneal or other oxygen treatment of titanium nitride is required to act as a barrier layer. If the underlying material to be electrically contacted is silicon, a titanium nitride underlayer can be deposited over the titanium underlayer, which can be silicided by silicon in a high temperature anneal. The two-sided layer of titanium silicide substantially reduces the electron-barrier height metal-semiconductor interface and thus produces a good ohmic contact. The topmost underlayer of titanium cleans the nitrogen target and promotes reflow into the narrower plug.

For example, we have found that the metal layer on top of aluminum has two steps: cold hot P.
It has also been found for hole filling that deposition by VD processing is preferred. Even hot deposition, preferably 350
It can be carried out at relatively low temperatures in the range of ° C to 420 ° C or even lower.

The sectional view of FIG. 8 shows, for example, a silicon substrate 1.
A dielectric layer 142 of silicon dioxide formed on 44
3 illustrates an embodiment of the present invention including a contact 140 therethrough.
The illustrated contact 140 through the dielectric layer 142 is
Dielectric layer 14 having a typical thickness 148 of 1.2 μm
It has a typical width 146 of 0.25 μm through 2. The contacts 140 are shown to a roughly constant ratio, but the layers filled in the contacts have a somewhat exaggerated thickness for clarity. In particular, the layer thickness on the contact sidewall 152 is greatly exaggerated. The contact dimensions described above result in an aspect ratio of about 5: 1 of the contact 140, which is an important neighborhood for the present invention. Plugs of these dimensions can be used with CF _{4 in} HDP oxide etch chambers available from Applied Materials.
Alternatively, it is known that etching can be performed with C ₂ F ₆ . However, such equal-sized plugs or trench-like fillings present a significant technical problem at this time.

According to the present invention, a PVD process using a high density plasma is used to contact the dielectric layer 142 before the metal layer 156, which is preferably aluminum or an aluminum alloy, is deposited in the contact 140 by a PVD process. Used to coat liner layer 150 on both sides 152 and bottom 154 of 140. Although liner layer 150 performs an additional function in the present invention, it is often referred to as a barrier layer. In general, since the liner layer 150 is simultaneously coated on the top surface 158 of the dielectric 142, the metal layer 156 not only fills the contact hole 140, but also flattenes the dielectric layer 156 through which the liner layer 150 intervenes. It extends laterally over the body surface 158. Therefore, the liner layer and the coater layer 150, 15
6 can be photolithographically defined to form metal-like surface features that interconnect to interlock with contacts 140.

Metal layer 156 can be functionally distinguished from either liner layer 150 or the underlying layers.
The liner layer and its underlying layers act as a lateral thin film in that it is expected to conduct across a small dimension of the film, namely its thickness. Therefore, the liner layer and the underlying layer need to be electrically conductive,
Its conductivity value is not critical, and certainly titanium nitride and even titanium show significantly less conductivity than aluminum. However, the metal layer is expected to conduct in a direction along the major dimension of the body. The main dimensions are
It can be the depth of the plug or the vertical size of the interconnect. In either case, the low resistance of the metal layer is important, especially in the case of interconnections.

Theory of HDP-PVD and Pressure Dependence The present invention is not limited by the theory we believe to explain its effects, but the description below includes some of our understanding of the mechanism of the invention. There is.

HDP-PV preferred for liner layer
Particles sputtered by D treatment are 10% to 100%
It is believed to be fully or partially ionized in the ionizing portion in the range of. The ionization portion is primarily controlled by the RF power level and the pressure of the process gas. The ionization fraction is usually not measured directly, but the degree of ionization is monitored by visual inspection of scanning electron micrographs (SEM) showing the resulting packing of narrow plugs.
In addition, the ionized sputtered particles are attracted to the electrostatically DC biased substrate, which effectively covers the bottom of the narrow plug hole and is used to coat both sides with a thinner layer. It seems that you can do it. It is understood that the DC bias of the substrate can be achieved with the RF bias of the substrate hole forming a DC self-bias. Indeed, DC bias is not preferred due to the charge formed on the dielectric portion of the wafer.

It is believed that the high density plasma fills substantially the entire internal volume and has an average ionization density of greater than 10 ¹¹ cm ^-3 . A plasma that substantially fills a volume is not expected to fill the boundary layer (sheath), nor is it expected to fill a shadowed volume, such as the volume behind a small aperture. Volume-filling requirements limit plasma densities above 10 ¹¹ cm ⁻³ but are not considered HDP sources because the plasma density is very small when averaged over the entire volume of the plasma. Imposed to distinguish. For example, a standard magnetron sputter source has a very high plasma density in the erosion track near the target, but the density is very low even a short distance from the target. A preferred method of measuring plasma density is
`` Journal of Vacuum Science and
Technology A "(Vol. 11, pp 152-156) by the use of Langmuir probes as described in the paper" Langmuir probes for RF induction plasmas "by Hopwood et al. Such high density plasma can be achieved by a number of methods, some examples of which are given below.

When the particles are sputtered from the target, the particles are usually neutral. The particles can be ionized as they pass through a high density plasma interposed between the target and the substrate. The resulting metal sputter ions can be directed onto the substrate by biasing the substrate appropriately. Further, substrate bias can be used to control the projection energy of metal ions, thus providing a tool to achieve denser, smoother films.

Two ionization processes can result in the ionization of sputtered atoms as they pass through the dense plasma and interact with the particles within the plasma particles. The collision of sputtered atoms with electrons in the plasma can ionize the sputtered atoms if the electrons have an energy greater than the ionization potential of the atoms. The ionization potentials of some commonly sputtered metals are shown in Table 1.

[0048]

[Table 1] In the second ionization process, collisions of sputtered atoms with metastable neutrons of the background gas can also ionize sputtered atoms in a process known as Penning ionization. Argon is the most commonly used background gas in sputtering. Since argon has a metastable energy of about 12 eV, metastable atoms can be a significant source of ionization.

The preferred PVD plasma reactor, described in detail below in connection with FIG. 10, produces a high density plasma with an induction coil connected to an RF power supply, wound around the sides of the chamber. The RF power supplied through the coil, usually via an axial magnetic field, is normally in azimuth inside the chamber and forms an electric field strong enough to cause decomposition of the background gas (argon). The coil and plasma may be considered a transformer if the coil is a primary winding and the plasma is a one-turn secondary winding. The current induced in this secondary winding is mainly composed of circulating electrons.

Since the plasma density is usually linearly dependent on the RF power applied to the coil, doubling the RF power doubles the plasma density. However, the DC power applied to the target tends to reduce the plasma density and the electron energy in the plasma drops as more sputtered atoms are added to the plasma. Therefore, the ionization fraction of sputtered atoms increases when increasing RF power and decreases when increasing DC target power.

The probability of ionization of sputtered metal atoms depends on both the plasma density as well as the length of time the metal atoms spend in the plasma. In a typical low pressure sputter, sputtered atoms are emitted from a target that has significant energy on the order of 1 to 10 eV. Thus, sputtered atoms travel rapidly toward the target, resulting in a low probability of ionization. The ionization probability is
Collisions can be dramatically increased by ensuring collisions of sputtered atoms with particles in the plasma that both reduce energy and randomize directions. The collision probability is increased by operating the plasma at higher gas pressures. Once the energy of an ion is reduced, its velocity perpendicular to the wafer surface can be increased by the substrate bias.

Experiments were performed in which atoms were sputtered from a titanium target in an argon background gas into an aperture having a high aspect ratio. Bottom coverage was measured at various argon pressures. The bottom coverage compares the thickness of metal deposited at the bottom of the aperture with the thickness deposited on a flat surface. The result, shown by line 159 in FIG. 9, is at 10 mTorr and below,
It shows that the bottom coverage is less than 20%. The bottom coverage increased above 10 mTorr and was about 50% at 30 mTorr. It is expected that the dependency will approach the asymptote at about 50 mTorr. These data indicate that the pressure during sputtering should be above 10 mTorr, preferably above 30 mTorr. These values are based on the aperture geometry, target material,
And about 1 mTorr and 100 m depending on the chamber design
A preferred pressure range between Torr is expected.

The directionality of the sputtered atoms projecting onto the substrate is determined by the substrate bias, and for deep hole filling the velocity component perpendicular to the wafer plane should be much larger than the parallel component. The electrostatic attraction of the substrate bias increases by the vertical component, while high voltage operation reduces the parallel component as well as the vertical component before the electrostatic attraction. Even in the absence of a specific substrate bias, there is a difference between the plasma potential and the floating potential of the wafer, so that the projected ions are directional. The floating potential is on the order of -2V. The plasma potential was not measured, but from 10V to 30
V order is expected. Any potential difference between the substrate and the plasma, which is usually neutral, appears only in the thin boundary layer between the conducting plasma and the substrate.
This boundary layer is known as a plasma sheath with a width of less than 1 mm for high density plasmas.

Contact Structure The first embodiment of the liner layer 150 includes three underlayers. The materials provided for this example do not include all of the possible materials used in the present invention.

The first underlayer 160 comprises titanium which is sputtered from a titanium target during the sputtering process and is partially or fully ionized. First lower layer 16
The 0 may be silicided with the underlying silicon 144 by a high temperature anneal step. If the underlying substrate is a metal, such as a metal interconnect, then it is not so much needed.

The second lower layer 162 contains a titanium compound, preferably titanium nitride. Preferably, titanium nitride is reactively sputtered. In this process, titanium is sputtered from a titanium target and also ionized. Titanium reacts with the nitrogen gas filling the plasma reaction chamber to reduce the pressure and the reactive compound titanium nitride is coated on the wafer.

The third underlayer 164 is a graded layer of sputter deposited material that begins as titanium nitride and ends as relatively pure titanium. This underlayer 164 has a TiN _x layer (where x varies from about 1 to 0 in atomic percent), although its composition can also be designated as Ti _y N _x, where y ≧ x. ) Is often referred to.

The thickness is 5 to 100 nm, preferably 40 to
Although in the range of 80 nm, the total thickness of liner layer 150 is about 80 when measured on flat top surface 158.
nm. Three lower layers 1 with ionized PVD
The formation of 60, 162, 164 ensures that it covers some of the side surface 162 and, in particular, the bottom 154 of the contact hole 140. The HPD-PVD deposited liner layer 150 facilitates effective filling of the contact holes 140 with aluminum and conveniently facilitates the highly oriented crystalline structure within the deposited metal. 3
Looks like it has two characteristics.

First, the liner layer 150 HPD-
PVD deposition, ie titanium layer 160 consisting mainly of elements
Both and the reactively sputtered titanium nitride underlayer 162 provide high bottom coverage in depositing the layer over the bottom 154 of the contact 140. It is believed that the ionization of at least a substantial portion of the sputtered particles causes the particles to be attracted at an angle that is at right angles to the surface of the wafer 144, and thus can penetrate deeply into the deep and narrow contact hole 140. The coating of sidewalls 152 is less effective, but still occurs due to the coverage of about 10%.

Second, HPD-PVD deposition yields a liner layer 150 with a very smooth surface. This effect is believed to occur with titanium and titanium nitride substrates 160, 162. Scanning electron micrographs show that the titanium nitride portion of the so-deposited liner layer has a dense crystalline structure with a very smooth surface, with the crystalline structure exhibiting a high material density. Both effects have about 1 in contrast to reflow when the average thermal energy is very low.
It is believed to result from ionized sputtered particles striking the substrate with a relatively high energy of 0 eV. SEM
4-5, the surface of which has conventionally sputtered layers
about 1.5 nm RMS, which is about one third of the conventional value of nm
It has a surface roughness of (root mean square).
The surface roughness is obtained by visually inspecting the SEM cross section of the surface,
And the average surface level and the top and bottom surface excursions are both determined. The deviation RMS value is
Determined by normal statistical sampling. High density means that the HPD deposited titanium nitride is not porous and therefore does not need to be annealed to fill any porous passages. That is, titanium nitride, such as HDP deposited, provides an effective barrier layer.

Third, the so-formed liner layer 150 exhibits a high degree of wettability with post-deposited materials, especially aluminum and its alloys. Due to the strong wettability at the interface between the liner layer and the aluminum, the surface tension on the exposed surface of the aluminum is low enough that the aluminum does not become beaded and thus the wettability is low for the aluminum in a short time. It is advantageous for the temperature to flow along the wall of the contact hole 140. Wettability is less than that provided by titanium, but even the titanium nitride underlayer provides good wetting and does not require oxygen stuffing.

Further, if the underlying material is silicon, liner layer 150 performs two additional functions.
The titanium nitride portion of the liner layer serves as a barrier layer between the aluminum and silicon substrate 144,
Therefore, aluminum is prevented from migrating into the silicon and affecting its sensitive semiconductor properties. The silicon substrate 144 can be a polysilicon level, line, or other feature, but it can also be a doped crystalline region that forms part of the transistor where the doping concentration is important. Also, the bottom titanium underlayer 160 can be silicided for the silicon substrate 144. That is, after the titanium is deposited on the silicon, typically after depositing the first two underlayers of the liner layer, the wafer holds the titanium layer together with a portion of the silicon underlayment near the interface. 600 ° C to diffuse and form alloy regions with graded components
Alternatively, it may be annealed at a sufficiently high temperature, or higher. The silicidation aids in ohmic contact formation by reducing the energy barrier at the interface.

The metal layer 156, along with the liner layer 150 of the components described above, can be deposited by a conventional PVD process, and the reflow process performed at a relatively low temperature and for a relatively short period of time comprises: The contact 140 can be further filled without the formation of voids. Preferably, the aluminum deposit has a short initial cold deposit followed by a longer hot deposit, as detailed below.
It is a one-step PVD process. More data will be presented later, but actual reflow temperatures below 480 ° C and as low as 350 ° C were confirmed, lower temperature limits due to many material combinations and reasonable reflow periods to 320 ° C. Is expected to be For example, reflow at 390 ° C for 2 minutes, or 350 for 10 minutes.
Reflow at ℃ fills the contact hole. Therefore, contrary to some proposals in the prior art, ionization deposition is not required for all plug fills. And the lower reflow temperature then allows PVD to be performed after the temperature sensitive element has already been formed. Standard PVD deposition for bulk metal deposition is highly preferred due to its higher deposition rate, greatly increasing the throughput possible with the system. Similarly, the metal layer 156
The use of standard PVD for depositing PVD significantly reduces the cost and complexity of PVD systems. HDP-PVD Chamber An example of a HDP-PVD plasma chamber is shown in FIG. Vacuum chamber 170 encloses a space containing a sputter target 172 and a substrate pedestal 174 supporting a wafer 176 being processed. Sputter target 17
2 forms part of the wall of the vacuum chamber 170, but is electrically insulated from the rest. A rotating array of sputter magnets 178 located behind the target 172 forms a magnetron target assembly that forms a strong plasma adjacent the target 172 to increase the sputter rate. The DC power supply 180 negatively biases the sputter target 172 with respect to the substrate pedestal 174 so that the target 172 acts as a cathode and the chamber wall 170 acts as an anode. The negative voltage partially maintains the argon plasma inside the vacuum chamber 170 and thus the target 172.
Attract the ionized argon atoms so that they strike the target 172 with sufficient energy to sputter particles therefrom. An RF power source 182 is connected to the substrate pedestal 174 to DC direct bias the pedestal 174 with respect to the plasma and thus control the energy of the particles impinging on the wafer 176.

To achieve a high density plasma, the induction coil 186 includes a target cathode 172 and a pedestal anode 1.
Another RF power source 188 is connected between both ends of the coil 186, which encloses a space between the coil 186 and the coil. The coil 186 inductively couples a large amount of RF energy into the plasma. The exact shape of the walls of the vacuum chamber 170 and the coil 186 are not critical to the invention and FIG. 10 is only represented schematically.
Thus, although the coil 186 is shown to be inside the vacuum chamber 170, it is possible to place the coil outside the cylindrical dielectric wall that forms one side of the vacuum chamber 170, and other coils. Shapes and arrangements are possible.

We believe that the additional energy supplied to the plasma by the coil 186 results in significant ionization of the sputtered particles passing through the plasma. We also found that part of the ionization is the induction coil 18
It is further believed that it will increase with the ratio of the RF power delivered to 6 and the DC power delivered to target cathode 172. Ratios of RF power to DC power in the range of 20-60% may be required for other geometries, although ratios up to 200% may be required, but the HDP-PVD chamber geometry used. Seems to be favorable for shape.
The effect of ionization becomes more significant as the DC self-bias generated by the RF power source 182 on the substrate pedestal increases to attract more ionized particles into the plug holes.

In the absence of control gas supplied to the chamber, the vacuum pump system 190 brings the base pressure inside the vacuum chamber 170 to a strong vacuum, preferably 10 ⁻⁷ Torr and typically about 2 × 10 ⁻⁸ Torr. maintain. Nitrogen and argon are each mass flow controller 196 by computerized chamber controller 200, which can be coupled to a system controller via bus 202.
Each source 192, 19 in an amount controlled through
4 to the chamber 170. As described in more detail below, plug filling is done during chamber 1 during HDP sputtering.
Very dependent on the pressure maintained at 70, the pressure is 0.1 mT
It is between orr and 60 mTorr, preferably 30 mTorr or more.

Keible US Pat. No. 4,844,775
Similar HD, such as the system described by No.
P-PVD systems are known. More precisely defined process parameters are described in the experimental examples, but the system used in the experiments described below is described in some more detail. The experimental system is capable of processing 8-inch (200 mm) wafers. Although alloying titanium with a target is well known, the target 17
The second active portion is mainly formed of titanium or titanium for sputter deposition of titanium nitride. Target 172
Has a diameter of 14 inches (35.5 cm) and is separated from pedestal 174 by about 5 inches (12.7 cm). The target 172 can absorb electric power up to DC power of about 24 kW, but in the experiment, the DC power is about 3
Limited to between 5 and 5 kW. The coil 186 has three turns and is constructed of a 0.25 inch (6.4 mm) diameter metal tube through which cooling water passes, although other shapes are readily employed. Its RF source 188 operates in the 2-4 MHz range with a typical RF power of 1.5 kW, although other frequencies such as the standard 13.56 MHz can be used.

Inductively bound HDP-PV of FIG.
D system is preferable, but it can form high density plasma,
Other HDP-PV capable of ionizing sputtered materials
The D system is also known. Such PVD systems are referred to herein by ECR (Electron Cyclotron Resonance) or by reference, as described by US Pat. No. 4,911,814 by Matsuoka, which is hereby incorporated by reference. It incorporates a helicon type coupling device such as that described by Campbell by U.S. Pat. No. 4,990,229. Other forms of providing a plasma of sufficient density to ionize the sputtered particles are possible.

The HDP-PVD reactor is contrasted with the standard PVD reactor. Currently practiced commercial PVD processes, such as those performed in the Endura PVD system available from Applied Materials, Inc., are more standard PVD processes.
Brought by processing. This standard PVD system includes a target that is DC biased with respect to the wafer to both excite the plasma and attract the ionized argon sputter ions to the target. Thus, the target, however, sputters particles from the target that remain largely neutral. The standard PVD reaction chamber does not generate a high density plasma, and the commercial version differs from the HDP-PVD chamber of FIG. 10 in that there is no induction coil 186 and RF source 182 for the pedestal 174. Instead, the pedestal remains electrically floating with respect to the target 172 and is isolated from ground. The aforementioned Applied Materials, Inc. Endura system is not considered a high density plasma system, and no means are specifically provided to ionize the flux of sputtered metal particles. 10% metal sputtered particles, i.e. ionized parts
It is estimated to be less than 1% and typically less than 1% in standard PVD systems. The present invention allows the all-metal layer 156 to be deposited in a HDP-PVD system, but HDP-PVD typically deposits material at a much lower rate than conventional PVD, and also more expensive reactors. In addition, such uniform processing suffers from low throughput as it is needed.

Cluster Tool Sputtering is a process that requires a very high vacuum and many sputtered layers are immediately degraded in the presence of small amounts of oxygen. Therefore, some, if not all of the steps of the present invention are preferably performed in a multi-chamber cluster tool such as the endura platform 210 shown in FIG. The Endura platform is functionally described in US Pat. No. 5,186,718 by Tepman et al., And early multi-chamber cluster tools were developed by Maydan.
Further details are provided by U.S. Pat. No. 4,951,601. The Endura platform is used by the previously cited patent Ong.
The three above cited patents are incorporated herein by reference.

The wafer is loaded into the system 210 by two independently operated loadlock chambers 212, 214 configured to transfer wafers into and out of the system from wafer cassettes loaded in their respective loadlock chambers. Has been done. The pressure in the first wafer transfer chamber 216, to which the load lock may be selectively connected via a slit valve not shown, may be from the atmosphere of the cassette or some low pressure to eg 10
It can be adjusted between moderately low pressures in the range of ^-3 to 10 ^-5 Torr. After pumping down the first transfer chamber 216 and the selected load lock chambers 212 and 214, the first transfer chamber 2
The first robot 218 at 16 transfers the wafer from the cassette to one of the two wafer placers 220, 222 and then to the degassing placement chamber 224. The first robot 218 then feeds the wafer into an intermediately located plasma preclean chamber 224, from which the second robot 228 preferably feeds 10 ^-7 torr and typically 2x Torr.
Secondly maintained at a significantly lower pressure, less than 10 ^-8 torr
The wafer is transferred to the transfer chamber 230. The second robot 228 is provided with a reaction chamber arranged around the periphery thereof, for example, a slit valve (not shown), which causes the second transfer chamber 23 to move.
For example, two HDP-Ps selectively opened for 0
VD chambers 232, 234 and two standard PVD chambers 236, 238, etc. are selectively transferred to or from. After the low pressure PVD treatment, the second robot 22
8 transfers the wafer to a cooling chamber 240 located in the middle, from which the first robot 218 takes the wafer and transfers it to the standard PVD chamber 242. P
The VD chamber 242 is connected to the PD surrounding the second transfer chamber 230.
A titanium nitride layer of controlled thickness and permittivity that functions as an anti-reflective coating (ARC) on the metal layer just deposited in the VD chamber is deposited on the wafer. The ARC layer is
Facilitates photolithography of highly reflective metal layers. After the ARC deposition, the wafer has two load locks.
It is transferred to one of the cassettes 12 and 214. Other shapes of cluster tools and associated chambers are possible.

The entire system is a system controller 250, which may be a personal computer, workstation, minicomputer, or other similar digital controller that communicates with the system and its various chambers, valves, and robots through control bus 202. Is computer controlled by. Although shown as a single component, it may include a single master controller and several sub-controllers such as the chamber controller 200 shown in FIG. 10 associated with various chambers and robots. The process of the present invention may be carried on a medium 254 such as a floppy disk, optical CD-ROM, magnetic tape, or other similar medium on which a program or recipe is recorded in a conventional manner. Ultimately commanded by the system controller 250 by the programs and methods loaded into the system controller 250 by the loading means. On the other hand, the loading means is locally connected to the terminal or the program or recipe is a communication protocol (protocol).
s) may include a communication link 256 that is remotely connected to the system supplier's or maintainer's office through a data link transferred in accordance with

Contact Processing A typical process for forming the contacts of the present invention in the underlying silicon layer refers to the contact structure of FIG. 8, the HDP-PV chamber of FIG. 10, and the process steps of FIG. 12 simultaneously. Will be explained from now on. The wafer is processed prior to the steps of the present invention to form the desired silicon surface structure, eg, lateral MOS transistor.
The dielectric layer 142 is deposited on the silicon substrate 144, and in step 270, the contact hole 140 is
Etched through dielectric layer 142 to reach silicon 144. All these processes are well known and are performed in standard semiconductor processing equipment for etching, CVD (chemical vapor deposition), photolithography, photoresist stripping, and other well known processes. Since the contact hole 140 is deep and narrow enough,
It is speculated to have a high aspect ratio that is difficult to fill by standard PVD processing.

After completion of the portions other than PVD in the structure illustrated in FIG. 8, the partially processed wafer 176 is:
It is transferred to the multi-chamber cluster tool 210 of FIG. The multi-chamber cluster tool 210 has the advantage and its oxidizing effect of allowing all of the PVD steps to be performed without exposing the wafer to the atmosphere. In the treatment described below, the oxygen partial pressure in the low pressure PVD region in and around the second transfer chamber 230 is lower than 10 ⁻⁷ Torr, preferably lower than 5 × 10 ⁻⁷ Torr, and most preferably 5 ×. It should be run well below 10 ^-8 Torr. Oxygen loading probably enhances the barrier properties of the HDP growth liner layer but reduces its wetting properties. As previously mentioned, the various chambers of the cluster tool 210 perform pretreatments on the wafer 176 including placement, degassing, and plasma preclean, similar to a post PVD step of depositing an antireflective coating. These steps are well known and are not directly included in the present invention and will not be detailed here.

For liner layer deposition, wafer 176
Is placed on the pedestal 174 of the HDP-PVD reaction chamber. For the deposition of a cemented carbide layer of titanium, PVD target 172 is formed of titanium or a titanium alloy.

To begin the first HDP sputter step 262 for the liner layer, the HDP-PVD chamber is pumped down and filled with argon at reduced pressure. The cathode and coil power supplies 180, 188 are turned on to form a high density argon plasma and the anode power supply 18
2 is powered up to direct current self bias the wafer 176. Argon sputters the target 172,
The resulting titanium particles passing through the dense plasma are at least partially ionized. Waha 1
The self-bias on 76 causes the ionized titanium particles to impinge on the wafer 176 in a direction substantially perpendicular to the original plane of the wafer, thus reducing the coverage of the side surfaces 152, but having contact holes with a high aspect ratio. It provides a high coverage of the bottom 154 of 160. Titanium also covers the liner layer 150, and in particular the flat top 158 of the dielectric layer 142 in forming the first underlayer 160, which is a cemented carbide layer. A typical deposition forms a flat surface layer of titanium with a thickness of 20 nm and a thickness of 14 nm.
Layer having a thickness of 1.2 μm is formed on the bottom 154 of the contact hole 140 having a width of 1.2 μm and an aspect ratio of 5: 1. That is, the bottom coverage is about 70%.
Other titanium thicknesses can be used with the present invention. A minimum thickness of about 2 nm is preferred for the bottom of the aperture. Thicknesses greater than 50 nm can be used, but that seems uneconomical for most current applications.

After the titanium underlayer 160 of the liner layer 150 is deposited, the bond between titanium and silicon is silicided by step 264, which is standard PVD.
Chambers 236, 238 or, preferably, separate R
Performed in one of a TP (rapid heat treatment) chamber, a metal anneal chamber (which can be heated by a lamp-irradiated susceptor), and a furnace, which need not be installed, but are all Can be mounted on the Endura platform. Silicide is not needed for vias that do not contact silicon. The silicidation is performed in a non-nitric oxide environment at about 600 as disclosed in the above cited patents of Nagan et al.
Above ℃, preferably from about 750 ℃ to 850 ℃
Includes annealing at ° C. To minimize the overall heating cost, silicidation is preferably performed by a rapid thermal anneal RTP. The silicidation can be delayed until after the deposition of the nitriding underlayer, but is delayed until after the deposition of the top titanium underlayer because the hot nitrogen-rich silicidation environment converts titanium to titanium titanium. Should not

In the second HDP sputter step 266 for the liner layer, nitrogen is also introduced into the same HDP-PVD chamber to form an argon nitrogen mixture. As the high density plasma is continued, the sputtered titanium is partially ionized. Titanium reacts with nitrogen during the deposition process and is deposited on the wafer as titanium nitride. A typical deposition forms a flat surface layer of titanium nitride having a thickness of 80 nm and a layer having a thickness of about 54 nm at the bottom of the narrow contact hole 140, ie a bottom coverage of 68%. . The minimum thickness of titanium nitride at the bottom of the hole is expected to be about 10 nm. The maximum thickness depends on several factors. For a narrow aperture, it should be much smaller than the aperture width to allow space for metal fill. For narrower apertures, thicker titanium nitride increases total resistivity. Therefore, in most situations, thicknesses greater than 200 nm are counterproductive.

In the third HDP sputter step 268 for the liner layer, the nitrogen supply to the same HDP-PVD chamber is stopped while the high density plasma continues, and the other layers of titanium are lined up with the liner layer 150. Sputter-deposited to form a third underlayer 164. However, the transition from reactive sputter to pure titanium sputter of titanium in a nitrogen environment is associated with higher nitrogen content near the interface.
(x ≈ 1) and the other is substantially pure titanium (x ≈ 0)
Resulting in a titanium nitride underlayer 162 of a graded layer of TiN _x . A typical deposition is 10 nm at the surface and 6 n at the bottom of the contact hole for a bottom coverage of 60%.
deposit m. The so-formed layer forms about 10% titanium nitride initially formed on the bottom of the third lower layer 164. Often only the minimum amount of top titanium needs to be deposited, perhaps 2-10 nm,
Data will be presented later indicating that the thickness is preferably limited to 60 nm or 100 nm.

The bottom coverage of all three underlayers should be relatively high for effective use of the invention for hole filling. The holes are not filled effectively, so
Values lower than 20% are not preferred. 100% is desirable, but a value greater than 90% indicates that the treatment is not being sufficiently promoted.

During typical operation, the nitrogen supply is abruptly shut off from the chamber at the beginning of the third deposition step 268. However, the previous titanium nitride deposition step 266
Then, a large amount of nitrogen is introduced into chamber 170,
It reacted with the titanium target 172 to form a titanium nitride surface on the titanium target 172. Therefore, at the beginning of the third PVD step 268, a significant amount of titanium nitride is sputtered from the target 172 until all the nitrogen has been removed from the target 172.
The main reason for the third deposition step 268 is that if the next wafer is processed, the titanium deposition of step 262 does not deposit any nitrogen that could adversely affect the semiconductor properties on the silicon. Inside is to clean the titanium target 162 from nitrogen. The requirements for the third deposition step 268 depend on many factors. If the plug is used to interconnect two metal layers so that the bottom of the plug contacts the other metal, possible nitrogen contamination will not significantly affect the plug contact to the underlying metal. Therefore, the target cleaning of the third deposition step 268 is not required as a target cleaning. Later data show that some minimal layers of metallic titanium depleted in nitrogen should be formed on titanium nitride to facilitate reflow of aluminum into narrow plugs, at least if it is an important parameter of the data. Indicates that there is. The general requirements for top titanium wetting and flat deposition for all plugs, especially for a wide range of plugs, are not shown.

Although the above step 268 of depositing a graded TiN _x underlayer abruptly shuts off the nitrogen supply, it is not possible to further reduce the nitrogen supply to accommodate the titanium nitride to titanium grading. It is possible.

Although it is possible to use separate chambers for different underlayers, as described in the above example, three HDP-formers for forming the liner layer are used.
The PVD deposition steps 262, 264, 266 are preferably performed in the same HDP-PVD chamber under the control of the controller 200, 250 with three steps distinguished by changes in gas composition and possibly power levels. Although this limited criticality has not been demonstrated, the HDP-PVD treatment does not yield titanium nitride underlayer 16
It is believed to be important only to 2, and if sufficient bottom coverage can be achieved in other ways,
The standard PVD chamber has an upper and lower titanium underlayer 16
Can be used for 0,164. However, in order to complete plug filling as economically as possible, after deposition of the liner layer 150, the wafer is then an interconnect, typically aluminum or an aluminum alloy, such as a 0.5% Cu alloy of Al. It should be transferred to conventional sputter chambers 236, 238 for metal deposition. Standard PVD processing is carried out in the absence of high density plasma and with relatively low ionization of sputtered particles. However, sputter deposition is performed on high speed, relatively inexpensive equipment.

Preferably, the aluminum is deposited in two steps, the cold hot sputter process of a conventional sputter apparatus without further annealing of the liner layer and without air break between the liner deposition and the aluminum deposition. . Both steps can easily be performed in a single standard PVD reactor by significantly changing the pedestal heating between the two steps. Of course, separate PVD reactors can be used for the two steps.

First aluminum sputtering step 27
At 0, about 200 nm of aluminum is 130 ° C
Alternatively, it is sputter deposited on the liner layer 150 with the substrate held at a lower temperature. This cold sputter forms a seed layer that adheres well to the upper titanium layer 164 without beading. In the second aluminum sputter step 272, most of the aluminum is sputter deposited onto the cold deposition layer with the substrate held at a higher temperature. The temperature selected for hot sputter is a tradeoff between lower temperature and longer reflow time. Detailed data are presented later, but it has been shown that hot sputter temperatures no higher than 470 ° C. are required, and hot sputter temperatures as low as 350 ° C. give reasonably short deposition or reflow anneals. The typical thickness of a hot-deposited metal layer is 800 nm on a flat surface.
And is sufficient to fill the 1.2 μm deep plug 140, substantially planarizing the surface above it,
Other thicknesses are possible.

PV of the above three steps of liner layer
In D deposition, the TiN and TiN _x underlayers are deposited in a process sequence that is carried out continuously at a temperature well below the effective oxidation temperature of TiN to oxygen partial pressure,
It is noted that indeed it can be carried out at temperatures below 300 ° C. Furthermore, the environment is kept substantially oxygen free until the end of the aluminum deposition. Thus, the titanium nitride layer has no opportunity to oxidize and lose its wettability, and even aluminum has almost no oxidation.

[0087]

【Example】

Process Example 1 A deposition rate of 120 nm / min of partially ionized titanium in the HDP-PVD process was achieved in the above chamber with the following parameters for a 200 nm wafer. Coil RF power supply 188 had a frequency of 2 MhZ and had a 1.5 kW RF power supply coupled to induction coil 186. The DC power supply 180 applied DC power of 5 kW to the titanium target cathode 172. Wafer bias power supply 182 operated at 350 kHz to provide 350 W of power to pedestal anode 174, resulting in a 45 V DC self-bias on wafer 175. The chamber pressure was maintained in the range of 20-30 mTorr of argon and the wafer temperature was about 50 ° C. (silicidation is performed in a separate step). To obtain a titanium deposition of 120 nm / min on a flat surface, approximately 4
Argon feed rate of 5 sccm (standard cubic centimeters per minute, ie the mass flow rate corresponding to the volumetric flow rate in cc that would occur if the gas was at a pressure of 760 Torr and a temperature of 0 ° C.) The corresponding pressure was kept at 20 mTorr.

Process Example 2 The deposition rate of 30 nm / min of titanium nitride reactively sputtered using ionized titanium was 200 nm.
Obtained when the wafer has the same chamber and the same frequency RF power supply under the following conditions. RF power of 1.5 kW is applied to the coil 186, and DC power of 5 kW is applied to the target anode 172.
90 W of RF power was applied to the pedestal anode 174, resulting in a 70 V DC self-bias on the wafer 176. The same pressure range can be used, resulting in the same 50 ° C. substrate temperature. 30 nm on a flat surface
Pressure of 30 mTorr in order to obtain titanium nitride deposits / min
The above pressure resulted from an argon feed rate of 45 seem and a nitrogen feed rate of 70 seem.

Liner Processing Window Plug holes with high aspect ratio, especially 0.35
A series of experiments were performed in which the power levels from the power sources 180, 182, 188 and the chamber pressure were varied to determine better process parameters to enhance the deposition of plugs with μm diameter and 3.5: 1 aspect ratio. Was done. The plug hole was formed with a silica layer having a thickness of about 1.2 μm, but the silica layer used in the experiment was either silicon, metal, or perhaps some other material such as those currently in commerce. On top of that substrate, P of SiO ₂
It was formed by thermal oxidation of the underlying silicon rather than by ECVD deposition. This process is PECVD-
It is necessary to be separately optimized for SiO _2, results close to results of thermal SiO ₂ is predicted.

The data is shown in the graph of FIG. The abscissa is for a power parameter equal to the ratio of the RF power supplied to coil 186 divided by the DC power supplied to target cathode 172 multiplied by the DC self-bias generated on pedestal anode 176. Was normalized. Along the ordinate the percentage bottom coverage is plotted, ie the thickness of the deposited layer at the bottom of the plug hole versus the thickness on the flat surface surrounding the top of the plug hole. When forming a liner layer extending over the entire plug hole at a high speed, a high bottom coverage is desired.

In one set of experiments, power was applied to titanium HDP-PVD under argon pressure of 5 mTorr to 10 mTorr.
Can be changed for deposition. The data is typically represented by a triangle that follows line 280. These data do not show any particular trend, except that the bottom coverage is low.

In the second set of experiments, the argon pressure was 20
Raised to mTorr. The variation in bottom coverage with normalized power is typically indicated by the circle that follows line 282. The bottom coverage typically increases with normalized power for a normalized power parameter of 10-15V, which is interpreted as a commercially feasible threshold.

In the third set of experiments, titanium nitride was reactively sputtered. Chamber pressure is 10sc
cm and 70 sccm, 30 mmTorr under Argon and Nitrogen supply, held at the above-mentioned values respectively.
Is held. The data is shown by the square that normally follows line 284. A sharp sharp bend exists at the normalized power of 15V on line 284 above which the bottom coverage shows a very high value, but acceptable values are for normalized powers of 10V and above. It occurs at the position.

Far from the effective bottom fill at high values of the RF power delivered to the coil, it increases the density of the plasma and the increased bottom coverage increases the smoothness of the deposited liner layer. Along with that, it allows the aluminum to flow through the walls of the plug holes so that it deposits more easily and faster at lower temperatures without voiding and more quickly. The smoothness of the liner layer is 10
It is believed to result from ionized particles impacting the partially formed surface at energies near eV, to clean and equilibrate the surface. Therefore, it is believed that the layers of the present invention also provide increased resistance to electromigration in the interconnect.

Top and Bottom Titanium Layers When the contacts are made to silicon, the main purpose for the bottom titanium layer in the liner layer is to:
It is to provide a raw material for siliciding the underlying silicon so as to form a good ohmic contact. On the other hand, if, for example, contacts are made to the metal through vias in the upper layer dielectric that connect the two levels of wiring, then the titanium layer is not needed. Similarly, the graded top TiN _x underlayer primarily requires cleaning the nitrogen sputter target in preparation for subsequent wafer titanium deposition. Thus, the graded top TiN _x does not require a bottom contact to the metal if hole filling can be driven only in the titanium nitride underlayer. For some material and structural bonds, including some intermetallic contacts, and for some planar structures, the liner layer provides a titanium nitride underlayer according to the present invention to provide a smooth surface for subsequent deposition of aluminum. It is believed that it is possible to only need to grow.

Experiments were carried out showing the advantages of HDP TiN as a major part of the liner layer over coherent (straightened) TiN, both of which provide similar plug coating properties. Coherent TiN is reactively sputtered in a chamber designed to fill 2: 1 contact holes. The coherent TiN film has a thickness of 30 when the DC power of 12 kW applied to the target cathode.
It was deposited over a period of 0 seconds. The substrate had a thermal oxide coating and was held at 300 ° C. The HDP TiN film is
In the case of DC power of 5 kW applied to the target and RF power of 1.5 kW applied to the coil, HDP-PV
Sputtered reactive in the D chamber, 90 W of RF power was applied to the pedestal producing a DC self-bias of -70V. The pedestal was kept at 25 ° C.

After TiN deposition (without any graded TiN _x layer), the wafer was alloyed with copper at 0.5% with 10 kW DC power for 36 seconds for a pedestal temperature of 300 ° C. It was transferred to a standard aluminum sputter chamber where 300 nm of aluminum was deposited.
There was a 2 hour air break on the closely deposited wafer, but the HDP deposited sample did not have any air break.

By visual inspection, the aluminum deposited on HDP-TiN had a glossier appearance than the aluminum deposited on coherent TiN. Transmission electron micrographs showed that the aluminum grains grown on HDP-TiN were about 3 times larger than the aluminum grains grown on coherent TiN.
X-ray diffraction of a sample with HDP-TiN shows that for a signal to noise ratio of about 70: 1, in the range of 30 ° to 60 °, about 3 corresponding to the aluminum <111> orientation.
It showed a single peak at 8.7 °. On the other hand, X-ray diffraction of a sample with coherent TiN showed a similar 38 with a signal to noise ratio of about 20: 1 with a smaller peak at 36.8 ° having a peak height of about 15% of the main peak. It showed a peak of 0.7 °. This secondary peak is H
DP-TiN did not appear in the underlying sample.

The X-ray vibration curve is presented in the graph of FIG. Oscillation curve 290 is for aluminum <111> with a sample containing a HDPTiN layer and oscillation curve 292 is for a similar peak with a sample containing a coherent TiN layer. These oscillation curves show that aluminum grown on coherent TiN has a substantially random crystallographic orientation, whereas <111> perpendicular to the plane of aluminum grown on HDP TiN. It shows that they are densely arranged in the orientation.

The data show that aluminum deposited on HDP TiN exhibits a larger grain structure and more oriented grain orientation than aluminum deposited on aligned TiN. As mentioned above, uniformly large TiN crystallinity and increased crystallographic orientation reduce electromigration.

Top Titanium Treatment Window When grown on HDP-PVD, the TiN layer appears to drive out the basic properties of post-deposited aluminum, especially as it appears in its dense and smooth crystal structure. However, any titanium intervening between TiN and Al has a significant effect. Almost pure titanium is obtained on top of graded TiN _x , but a similar effect is obtained if a special titanium sputter process is performed without any nitrogen included. Can be obtained.

Titanium provides the well-known wettability and bonding function to the aluminum deposited on it. Therefore, on the upper surface, a nearly pure form (TiN _x , x ≈
Although the requirement to contain titanium in 0) has not been explicitly shown so far, a significant amount of titanium seems desirable.
On the other hand, an excess thickness of titanium appears to reduce the effectiveness of the crystalline structure of the TiN layer in promoting the reflow properties of aluminum deposited on titanium. For plug-filling applications, it is observed that too thick a layer of titanium results in TiAl ₃ overhangs potentially shadowing the plug holes. The X-ray data presented above shows HD without a Ti or TiN _x layer
It is noted that it was measured on a planar sample with P TiN only. However, the lack of a plug means that no reflow was needed.

A series of experiments were performed by varying the TiN _x thickness of the graded layer and, in some cases, varying the hot deposition temperature and plug aspect ratio.

Typical process parameters for the experiment are as follows: The plug was formed of thermally oxidized silicon and had an aspect ratio in the range of 2: 1 to 4: 1. This structure consists of a 20 nm thick lower titanium layer, 600 nm
Layer of TiN _{x, with} a graded layer of TiN _x of 10 nm thickness. Therefore, the so-formed liner layer was sputter deposited with 200 nm cold aluminum and 800 nm hot aluminum in a conventional PVD apparatus.

From SEM, in the case of hot aluminum deposition, at a heater temperature of 450 ° C., the filling properties are 10 n thin.
It is clear that even better for graded layers of thickness m. It is believed that the thicker 60 nm graded layer reacts with the aluminum deposited thereon to form TiAl ₃ and the coarse grain structure indicates the flow of aluminum into the plug. At a higher temperature of 535 ° C., it performs slightly better because the thicker graded layer of TiN _x tends to show dewetting of the seed layer (cold deposited aluminum). . Better performance of thicker graded layers at 535 ° C is of second importance, as the present invention is primarily served by the lower aluminum deposition and reflow temperatures.

Another set of experiments was performed with 10 nm thick TiN.
reflow at 450 ° C to the top of a graded layer of _x ,
Compared to a reflow without the TiN _x layer, ie without the Ti wetting layer on top. SEM has 1 reflow
It was shown to be significantly improved with 0 nm TiN _x .

The final conclusion is that the top titanium wetting layer is required for narrow plug fills, and perhaps not for planar deposition,
At least in the processing parameter space presented above,
It is that its thickness should be less than 60 nm. The quoted thicknesses are for a graded layer of TiN _x , as most of it is substantially pure titanium. The lower limit of titanium thickness probably depends closely on the aspect ratio and other processing parameters. At least for typical data processing parameters, the thickness should be equal to or greater than 10 nm, with a thickness of 10 nm being preferred for the processing parameters used.

Aluminized Window Substantially adapted deposition of the liner layer in the plug holes through the dielectric leaves plug holes with an even higher aspect ratio than before. Even if the liner layer promotes plug filling with post-deposited metal, for many applications the plug will be of adequate length of time,
The deposition parameters for metallization are important if they are filled without voids at temperatures that are practically low. As mentioned above, the preferred metallization involves two steps, a cold hot sputter process. Cold hot sputter processing itself is well known. The above cited patent of Ong is between 50 ° C and 150 ° C.
Cold deposition at ° C and hot step at 550 ° C are proposed. Wang US Patent No. 5,108,
No. 570, cold deposition at 50-250 ° C and 4
We propose a hot deposition temperature that does not exceed 00 ° C. Wang does not provide good data for the minimum temperature of hot deposition and there is no suggestion that can be even below 400 ° C. However, it has been found that the liner layer allows hot sputter to be carried out at approximately low temperatures, especially if a reasonably short PVD deposition time is required.

Another series of experiments was performed on standard PVD aluminum deposition on plug holes with high aspect ratios. For these experiments, the dielectric layer was a thermal oxide, that is, the silicon was kept at a high temperature in an oxygen environment to oxidize the surface to silicon dioxide. On the contrary, industrial manufacturing usually
Plasma-enhanced CVD or spin-on subsequently cured
(spin-on) done with oxide deposited by glass. Each of these materials would have required a separate set of experiments to determine its aluminized window.

The inspected area 300 of FIG. 15 shows a processing window to which the conventional high aspect ratio plug filling process can be applied. In particular, the TiN liner layer is deposited by aligned PVD and the aluminum is deposited on it by a cold hot PVD process. The vertical axis shows the substrate temperature during the hot part of the aluminum sputter deposition, and the horizontal axis shows that this high temperature is maintained during deposition or during subsequent independent reflow processes to effectively fill the plugs. Indicates the time required. As shown, at 430 ° C. and below, the reflow period must be held for 3.5 minutes or more, which is considered excessive for high throughput PVD.

On the other hand, the shaded area 30
No. 2 shows a process according to the invention in which aluminum is filled in the plug holes which are precoated with a liner layer and also with a low temperature aluminum seed layer. The data is 0.25μ
800 to a hole with a diameter of m and an aspect ratio of 5
200 nm followed by hot deposition of nm aluminum
Based on cold deposition of aluminum. Sputtering occurs in a standard PVD chamber with an argon pressure in the range 0.5-2 mTorr. DC target power is
Adjusted to deposit 800 nm of hot aluminum at a given time, the target-to-wafer distance is maintained between cold and hot deposition. The data may vary somewhat for different hole geometries, metal layer thicknesses, and other processing parameters. It is preferred to carry out cold deposition at 200 ° C or lower, as the wetting temperature is about 250 ° C. And again, the plotted temperature is the substrate temperature during hot deposition and time is the time during hot deposition.

The process of the invention proves to be useful both at lower temperatures and at shorter deposition and reflow times. In particular, the very short deposition time is 470 ° C.
Even obtained at 30 ° C. For hot deposition at 390 ° C or even 350 ° C, the reflow time is 4
Much less than a minute. At approximately 350 ° C., the reflow period is still manageable 6 minutes. The preferred temperature range for hot deposition is 350 ° C to 400 ° C, but 32
Substrate temperatures as low as 0 ° C. or 300 ° C. are considered for processing windows optimized for lower temperatures.

These data demonstrate the advantages of the initial aluminum layer deposited at relatively cold temperatures. When deposited on the liner layers of the present invention, such layers are smooth and thus promote reflow. Then, for hot aluminum deposition,
Allow the intermediate surface between the cold aluminum layer and the liner layer to flow without obstruction. Thus, aluminum does not become spherical without loss of wettability, even at relatively high temperatures.

Interlevel Vias The above discussion is primarily concerned with contact fill for the underlying silicon. In the case of vias between two metal layers, there is no problem defeating the underlying silicon. Therefore, the need for a lower titanium layer is not clear. Nevertheless, many aspects of the invention are equally applicable to vias.

A typical via structure is shown in cross section in FIG. 16 before it is filled. For example, an aluminum patterned intermediate metal layer 310 (here,
The metal 1 layer) is overlaid with an antireflective (ARC) film 312 of TiN that is useful during photolithographic patterning in preventing excessive reflection from metal layer 310.
Over that, an interlevel dielectric layer 314 of, for example, silicon dioxide is deposited. Although the metal layer 310 is shown to be of uniform thickness, in many areas the dielectric layer 314 is at a lower level because it is pre-patterned to wiring levels that include many linearly extending interconnects. Dielectric layer 31
Contact 6 directly. However, vias are formed over the rest of metal layer 310. Over the top level dielectric layer 314 is deposited a photoresist 318 that is developed to expose the via area 320. The interlevel dielectric layer 314 is etched away in the via area 320, after which the photoresist 318 is stripped. Sometimes it is left to be removed by the plasma preclean, but occasionally the TiN ARC layer 312 is
Is also etched by the dielectric etch. In either case, the thin aluminum oxide layer and other foreign material that results from the removal of photoresist layer 318 typically forms at the bottom of via hole 320. Although it is believed that the removal of the insulating aluminum oxide layer 322 does not require any other step other than the pre-cleaning to remove foreign matter, removal of this stable insulating aluminum oxide layer 322 by plasma pre-cleaning is problematic. A titanium layer can be deposited to ensure good contact at the bottom of the via 318. Titanium reacts strongly with the underlying aluminum to form conductive TiAl ₃ and to break through the intervening layer 320 of insulating aluminum oxide. Thus, there is also no need for silicide for the lower level metal layer 310, but the lower titanium underlayer 160 of the liner layer 150 may still be useful in some situations to ensure good contact to the underlying metal layer. preferable.

Therefore, a preferred filled via structure is shown in cross-section in FIG. 17 and the major steps in its formation are shown in the flow diagram of FIG. Step 330
Then, the via hole 320 of FIG.
4 and ARC layer 322 are etched through. The above steps may include plasma precleaning. Along with the interlevel vias, the via holes 320 are etched and pre-cleaned as described in the aforementioned Ong patent.
It is preferable to facet the upper corners of the.
Such faceting is not used for contacts because energetic plasma particles can damage exposed silicon.

HDP in steps 262, 266 and 268
The PVD process is used to deposit the liner layer 150 similar to that done for the contacts 140 of FIG. The liner layer 150 has a via hole 320.
Coating the interior and the top surface 332 of the dielectric layer 314. The liner layer 150 is made of Ti, TiN, and TiN _x.
Three lower layers 160, 162, 164 of H
The DP-PVD process ensures a smooth, dense and crystallographically aligned liner layer 150.

The 400 ° C. deposition temperature of aluminum is
No separate silicidation is performed on the via, as it is sufficient for alloying with the underlying titanium to form Al ₃ . A warm top metal layer (metal 2) 334 is deposited in steps 270, 272 into the via 320 and on the dielectric layer 314, as was done for the contact 140 of FIG. The two-step process consists of a first cold standard PVD process followed by a hot standard PVD.
D processing is included. In step 336, the ARC layer 3
38 is deposited over the top metal layer 334 to facilitate photolithographic delineation into the interconnect.

The bottom HDP TiN layer need not be filled with oxygen to enable barrier properties, and titanium need not be silicided, so in some situations the bottom While the HDP TiN layer provides the necessary electrical contact, the three layer embodiment of the liner layer offers the advantage of a highly oriented crystalline smooth liner layer. In addition, the TiN liner layer prevents any moisture trapped in the silica layer 314 from migrating to the aluminum filled via 320. The above data is
It shows the minimum thickness requirement of the top titanium underlayer in the liner layer, but if the processing window is used when the top titanium underlayer is not needed for reflow, then the nitrogen scrubbing function of the top titanium underlayer is level. It is not needed for intervias, and thus can be dispensed with.

Thus, the present invention provides an effective but economical method for filling narrow apertures with metal. The technical data presented above lead to a number of conclusions defined in the claims, which are not limited by the particular examples presented.

Although the examples relate primarily to nearly symmetrical contacts and vias, the invention is not so limited. The same concept can be applied to contact or via trenches where the trench width determines the aspect ratio.

A promising structure called the dual damascene pattern, which is shown in FIG. 19 in regular hatching, joins the plugs by interconnection. The dual lithographic process includes trenches 340 extending laterally along the top of the dielectric layer 342 and an upper aperture 346 at the bottom of the trench 340 to a dielectric layer 342 adjacent to a silicon substrate or lower interconnect level not shown. Form both plugs 344 that extend to the bottom aperture at the bottom. The single step of the filling process of the present invention is plug 34.
Used to fill both 4 and trench 340 with metal. The metal in the trench 340 is used as an interconnect, while the metal in the plug 344 is used for the vertical interlayer connection. Such a structure allows for high density formation of interconnects. And, again, no metal lithography is required, only planarization, such as by chemical mechanical polishing of the top surface to expose the unpatterned portions of the dielectric layer 342. However, the dual damascene pattern structure exhibits a very high aspect ratio for filling because both the trench and the underlying plug need to be filled at the same time. The present invention is directed to filling such narrow and deep holes.

The present invention can also be applied to other aperture structures such as trenches for DRAMs that extend through the dielectric layer to the only partial path. Many of the inventive concepts can be applied to planar structures that do not depend critically on narrow apertures.

The above discussion of both interconnect contacts and via fills emphasizes that the plug fills of the present invention can be integrated with the deposition of metal layers for interconnection over fill plugs. Indeed, the X-ray diffraction data discussed with respect to FIG. 14 show that metal interconnects, especially aluminum, formed on the liner layer of the present invention show large uniform grain size and high crystallographic orientation of the metal crystals. Shows the best electric transfer behavior for. However, some applications that do not require a narrow plug fill do not require all three underlayers of the liner layer. It is noted that the X-ray diffraction data was measured on a sample with aluminum deposited directly on the TiN layer. Similarly, the top titanium underlayer is most obviously important for filling small conductive plugs.

Therefore, the interconnect structure of the present invention is shown in cross section in FIGS. The most important manufacturing steps are shown in the flow diagram of FIG. At step 350, a HDP-PVD process is used to deposit a liner layer 352 over a dielectric layer 354 of, for example, silicon dioxide. The liner layer 352 is shown in FIG.
And at least a TiN underlayer as well as the TiN underlayer 162 of the contact 140 of FIG. Its formation by HDP-PVD will have a smooth surface, large crystallinity and highly oriented crystallinity, as shown by X-ray diffraction experiments. Further, the liner layer 352 includes a lower titanium underlayer under the TiN underlayer, an upper TiN _x underlayer over the TiN underlayer, or both, although it is not known that intervening is necessary for interconnection.

At step 356, a metal layer 358, eg, aluminum, is deposited over the liner layer 352. Unlike the case of hole filling, this planar deposition is not critical, so if desired it can be performed in a single temperature step with standard PVD. In step 360, antireflective coating 362 is deposited over metal layer 358, and in step 364, photolithographic mask 366 of photoresist material is deposited and patterned over the intended interconnects. Referring now to FIG. 21, this structure leaves a uniform large grain interconnect 370 having a closely oriented <111> crystal structure for formation on the liner layer 352, step 368. Then, the periphery of the mask 366 is etched.

Other Embodiments The presently most important application of the present invention is to fill plug holes and form interconnections with aluminum, but the present invention is not so limited. Aluminum may be alloyed with other metals, for example up to 10% by weight. Examples of such alloys are aluminum-copper, aluminum-copper-silicon, aluminum-silicon,
Aluminum-germanium and aluminum-palladium-silicon. Other metals such as copper and their alloys and suicides are considered for contacts and interconnects and are subject to the same limitations as aluminum contacts and interconnects, and thus can enjoy similar advantages of the invention.

Although the exemplary dielectric layer was silicon dioxide, the present invention is not so limited. Other inorganic dielectrics such as Si ₃ N ₄ is currently commonly used as a field dielectric, another insulating material containing an organic material in the case of the present invention it is advantageous to apply thereto, the dielectric It can be used as a layer.

The example titanium layer described above was used for both wettability and silicidation. Other cemented carbides such as cobalt can also be used for these functions and are therefore included within the invention. Several groups are investigating CoSi as an ohmic contact material. The cemented carbide may be an intermetallic alloy containing two stoichiometrically close amounts of the two cemented carbides.

Preferably the TiN used in the present invention
Is a metal compound that has good conductivity and has a very smooth surface. The TiN layer provides some advantageous results, but other conductive cemented carbide nitride compounds can be replaced, such as TaN, especially if copper is used as the interconnect metal. Cemented carbides other than Ti and Ta that can be used in their elemental and nitride forms are W and Ni.

[0131]

Accordingly, the present invention provides a method for effectively filling holes that deposit metal layers having high aspect ratios and excellent crystallographic properties. The process of filling the narrow holes with metal can be performed simultaneously with the deposition of the metal, which can be defined in an electromigration resistant interconnect. Nevertheless, the process can be carried out on less expensive equipment while still exhibiting high deposition rates and thus achieving high throughput at reduced cost.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a contact or via hole extending through a dielectric layer in a semiconductor integrated circuit.

2 is a cross-sectional view of the contact or via of FIG. 1 after being deposited with partially sputtered metal.

FIG. 3 is a cross-sectional view of a contact or via with improper deposition forming a void.

FIG. 4 is a schematic cross-sectional view of a contact or via in which metal fills the contact or via and reflows to planarize the surface.

FIG. 5 is a flow diagram for a conventional hole filling process.

FIG. 6 is an orthographic view of a schematic representation of interconnections and their failure modes due to electromigration.

FIG. 7 is an orthographic view of a schematic representation of its failure modes due to interconnection and electromigration.

FIG. 8 is a cross-sectional view of a contact made with the liner layer of the present invention and subsequently filled with metal.

FIG. 9 is a graph of pressure dependent bottom coverage in high density plasma.

FIG. 10 is a schematic elevational view of a reaction chamber in which physical vapor deposition (PVD) with high density plasma (HDP) can be performed.

FIG. 11 is a schematic plan view of a multi-chamber cluster tool according to the present invention.

FIG. 12 is a flow diagram for a processing embodiment of the present invention.

FIG. 13 is a graph showing a process window for deposition of a liner layer as a function of power level and pressure.

FIG. 14 is a graph showing an X-ray vibration curve demonstrating the crystallinity of the aluminum layer deposited on the titanium nitride layer formed according to the present invention.

FIG. 15 is a graph showing a process window for standard PVD deposition of aluminum into a plug having a liner layer of the present invention.

FIG. 16 is a sectional view of a via hole.

FIG. 17 is a cross-sectional view of a via hole after its metallization according to the present invention.

FIG. 18 is a flow diagram of the major steps in filling a via according to the present invention.

FIG. 19 is an orthographic view of the dual damask pattern structure prior to its filling.

FIG. 20 is a cross-sectional view of an interconnect formed in accordance with the present invention.

FIG. 21 is a cross-sectional view of an interconnect formed in accordance with the present invention.

FIG. 22 is a flow diagram of the salient steps in forming an interconnection according to the present invention.

[Explanation of symbols]

140 ... Contact, 142 ... Dielectric layer, 144 ... Silicon wafer, 156 ... Metal layer, 160, 162, 16
4 ... Lower layer, 172 ... Sputter target, 174 ... Pedestal, 176 ... Wafer, 186 ... Induction coil, 31
0 ... Metal layer, 312 ... ARC film, 314 ... Dielectric layer, 3
18 ... Photoresist, 320 ... Via hole, 334 ... Metal layer, 338 ... ARC layer, 340 ... Trench, 344 ...
Plug, 346 ... Aperture, 352 ... Liner layer, 3
54 ... Dielectric layer, 358 ... Metal layer, 362 ... ARC film,
366 ... Mask.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 21/285 301 H01L 21/285 301L (72) Inventor John Forster San Francisco, California, United States , Haram Street 41 (72) Inventor Tse Yang Yau United States, California, Sunnyvale, Vicent Drive 1243 Number 78 (72) Inventor James Nullman United States, California, Palo Alto, El Camino Way 4155-Gee (72 ) Inventor Fusen Chen Portal Plaza 19910, Cupertino, California, United States 19910

Claims (58)

[Claims] 1. A method of performing sputtering on a substrate, comprising: a first step of performing a sputter deposition of a first layer containing a compound of a refractory metal on the substrate in high density plasma; and the first step. A second step of sputter depositing a second metal layer on the layer. 2. The method of claim 1, wherein the second layer forms a conductive element along the major axis. 3. The method of claim 1, wherein the second step is performed with a plasma having a density substantially less than the high density plasma of the first step. 4. The first step is performed in a first reaction chamber, wherein the high density plasma is at least partially energized by an induction coil surrounding the high density plasma space. The method of claim 3, wherein 5. The first step is performed in a first reaction chamber, wherein the high density plasma is at least partially energized by an induction coil surrounding the high density plasma space. The method of claim 1, wherein 6. The plasma reaction chamber wherein the second step is energized primarily by a voltage applied between a sputter target containing at least a portion of the metal and a pedestal supporting the substrate. Method according to claim 5, characterized in that it is carried out. 7. The method of claim 1, wherein the refractory metal compound comprises a refractory metal nitride. 8. The method of claim 7, wherein the compound of the refractory metal comprises TiN. 9. The method further comprises the third step of sputter depositing a third layer on the first layer in a high density plasma performed between the first and second steps. The method of claim 1, wherein at least a portion of the third layer facing the second layer consists primarily of at least one refractory metal. 10. The at least one refractory metal is Ti
10. The method of claim 9, comprising: 11. The substrate is formed with a dielectric layer overlying the substrate layer and passing through the dielectric layer at least 1:
An aperture having an aspect ratio of 1, wherein the first, second, and third steps deposit the first, second, and third layers on the aperture. The method according to claim 9, wherein 12. The substrate layer comprises silicon and further comprises a fourth step of sputter depositing a fourth layer predominantly comprising essentially at least one second refractory metal onto the substrate layer. The method according to claim 9, characterized by: 13. The method of claim 12, wherein the at least one second refractory metal comprises Ti. 14. The second deposition step comprises a first sub-step of sputter depositing a first underlayer while the substrate is held at a first temperature; and the substrate is the first sub-step. A second sub-step of sputter depositing a second underlayer while being held at a second temperature above the temperature, the method according to claim 1. 15. The metal layer comprises aluminum, and the first temperature is less than 250 ° C. and the second temperature is within a range of 350 ° C. and 470 ° C. The method according to claim 13. 16. The method of claim 14, wherein the second temperature is less than 430 ° C. 17. The sputter target, wherein the first step is performed in a plasma reaction chamber including an induction coil surrounding the plasma reaction chamber, is powered by a first RF power source, and the direct current power source includes titanium. The method of claim 1, further comprising a pedestal supporting the substrate and a pedestal supporting the substrate. 18. The RF during the generation of a high density plasma.
A power supply supplies RF power P _RF to the coil, the DC power supply supplies DC power P _DC to the target, and P _RF is equal to or greater than 20% of P _DC. 18. The method of claim 17, wherein 19. A second R biasing the pedestal in the plasma reaction chamber to RF bias the pedestal to create a DC self-bias V _BIAS in the high density plasma.
The F power source includes and during the generation of the high density plasma the following conditions: 18. The method of claim 17, wherein: 20. The condition is: 20. The method of claim 19, wherein: 21. The method of claim 1, wherein the first sputtering step is performed in a chamber containing the high density plasma and having a pressure greater than 1 milliTorr. 22. The method of claim 21, wherein the pressure is greater than 10 mTorr. 23. The method of claim 22, wherein the pressure is greater than 30 mTorr. 24. The method of claim 23, wherein the pressure is less than 100 mTorr. 25. The method of claim 21, wherein the pressure is less than 100 mTorr. 26. Placing a substrate in a first sputter chamber including an induction coil for forming a plasma therein, and at least 1 on the substrate in the first sputter chamber.
Depositing a first layer containing two refractory metal compounds
The first deposition step utilizing a plasma formed by the induction coil, and at least two electrodes to which plasma is primarily associated from the first sputter chamber. Transferring the substrate to a second sputtering chamber generated by: and depositing a second layer containing metal on the first layer utilizing the plasma generated by the at least two electrodes. And a method of performing sputtering of a metal layer including. 27. The method of claim 26, wherein the compound is a nitride of the refractory metal. 28. The at least one refractory metal is Ti
27. The method of claim 26, comprising: 29. The second step of depositing a second underlayer consisting essentially of at least one second refractory metal, wherein said first step is performed before said first substep. 27.
The method described in. 30. The method of claim 29, wherein the at least one second refractory metal comprises Ti. 31. A method for sputter-filling a contact hole formed in a dielectric layer, formed on a substrate including a silicon portion adjacent to the bottom of the contact hole, in a high density plasma. First, including metal titanium on the substrate including the contact hole,
A second step of sputter depositing a second layer comprising TiN on the first layer, the second step being performed in a high density plasma; A third step of sputter depositing a third layer having an upper portion comprising titanium metal on the layer, and a fourth step comprising mainly aluminum on the third layer.
A fourth step of sputter depositing a layer of. 32. The first, second, and third steps are performed in a first sputter chamber, and the fourth step is performed in a second sputter chamber. The method of claim 31. 33. The fourth step is performed in a plasma primarily generated by a DC electrical signal applied between a sputter target containing titanium and a pedestal supporting the substrate. 32. The method according to 32. 34. The second step comprises supplying gaseous nitrogen to a sputtering chamber surrounding a surface of the substrate and a sputtering target containing titanium, and TiN is reactively sputtered on the substrate. 32. The method of claim 31, comprising: sputtering the sputter target in the presence of the nitrogen so as to do so. 35. The third step is a composition TiN _{x in which} the third layer is graded between TiN and Ti.
Comprising interrupting the supply of the nitrogen to the chamber while maintaining the plasma between the second step and the third step so as to be deposited. The method according to 34. 36. The second step comprises 1 to 100
32. The method of claim 31, wherein the method is performed in a chamber containing the high density plasma maintained at a pressure of mTorr. 37. The method of claim 36, wherein the pressure is 30 mTorr or higher. 38. A method of forming an interconnect on a dielectric layer, comprising depositing a liner layer comprising a refractory metal compound on the dielectric layer in a high density plasma, said liner layer. Depositing a metal layer on the substrate, and photolithographically defining the metal layer to form horizontally extending electrical interconnections. 39. The compound of refractory metal comprises Ti and N.
39. The method of claim 38, comprising: 40. The method of claim 39, wherein the metal layer comprises aluminum. 41. A substrate including a silicon surface portion, a dielectric layer having an aperture formed on the substrate and extending through the silicon surface portion, and a dielectric layer deposited on a wall surface and a bottom portion of the aperture, A first layer containing a refractory metal; a second layer deposited on the first layer, containing a second refractory metal compound; and a third layer deposited on the second layer. A third layer containing a refractory metal, and a fourth layer containing a fourth refractory metal deposited on the third layer, wherein the RMS surface roughness of the third layer is , A contact structure not larger than 1.5 nm. 42. The contact structure of claim 41, wherein the fourth layer substantially fills the aperture. 43. The compound of the second refractory metal,
A nitride of the third refractory metal is included,
The contact structure according to claim 41. 44. The contact structure according to claim 43, wherein the first, second, and third refractory metals each include titanium. 45. The contact structure of claim 41, wherein the fourth layer comprises aluminum. 46. A substrate including a surface dielectric portion, a first layer comprising a first refractory metal compound deposited on the substrate, and at least one vertical layer deposited on the first layer. A second layer of metal formed to define a directionally extending electrical connection, the RMS surface roughness of the first layer being not greater than 1.5 nm. Interconnect structure. 47. The interconnect structure of claim 46, wherein the compound is a refractory nitride. 48. The interconnect structure of claim 47, wherein the first refractory metal comprises titanium. 49. The method of claim 46, further comprising a third layer deposited over the substrate by the first layer and including a second refractory metal. Interconnect structure. 50. The interconnect structure of claim 49, wherein the compound is a refractory nitride. 51. The interconnect structure of claim 50, wherein the first and second refractory metals include titanium. 52. (a) a first high density plasma PVD reaction chamber containing a target containing titanium and a nitrogen gas supply source; and (b) a maximum density substantially lower than that of the first PVD reaction chamber. A second PVD reaction chamber capable of generating a plasma and having a target containing aluminum, (c) selectively connectable to the first and second PVD reaction chambers, and subjecting to a vacuum break; Without the PV
D. at least one transfer chamber comprising at least one substrate handler for selectively loading and unloading a substrate into and from each of the D reaction chambers; And depositing a liner layer containing titanium and nitrogen on the substrate in the first PVD reaction chamber, and then instructing the robot to move the substrate from the first PVD reaction chamber. Transferring to the second reaction chamber, and then depositing a layer of aluminum on the liner layer in the second PVD reaction chamber. A semiconductor processing apparatus including loading means for loading the controller. 53. The semiconductor processing apparatus according to claim 52, wherein the loading means includes a transferable recordable medium in which the control program is recorded. 54. The first PVD reaction chamber includes an induction coil that couples RF power to the plasma of the first PVD reaction chamber; and the second PVD reaction chamber primarily the second PVD reaction chamber. PVD
53. The semiconductor processing system of claim 52, including at least two electrodes that couple direct current power to generate plasma in the reaction chamber. 55. A first PVD reactor comprising an induction coil coupled to an RF power source for generating a high density plasma inside the first reactor, and mainly for generating plasma inside the second reactor. A second PVD reactor comprising two electrodes coupled to an RF power source, selectively open to the first and second PVD reactors, capable of evacuating, and having therein An integrated manufacturing tool comprising: a transfer chamber including a robot for loading and unloading substrates into and from the first and second reactors; and a controller for controlling the first and second reactors and the robot. 56. The tool of claim 55, wherein the first reactor includes a PVD target that includes a refractory metal. 57. The tool according to claim 56, wherein the refractory metal is titanium. 58. The tool according to claim 57, wherein said second reactor comprises a PVD target comprising aluminum.