JP2000332106A - Semiconductor device for its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent broken wire defects due to electromigration which occurs in fine wiring of copper by forming a pattern for compensation which supplies copper. SOLUTION: This device is equipped with a 1st wire 14; a 2nd copper wire 23 made of copper or copper alloy; 2nd and 3rd insulating films 15 and 19 which are formed between the mentioned wires; a connection hole 20 which reaches the 1st and 2nd wires 14 and 23 and is formed in a 3rd insulating film 19; and a plug 24 which is formed of copper or copper alloy, connects the 1st and 2nd wires 14 and 23, formed in the connection hole 20, further equipped with the pattern 18 for compensation which is made of copper or copper alloy, connects directly to the plug 24, and is formed nearby the connection part between the plug 24 and 1st wire 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a wiring structure using copper and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same which have solved the problems caused by copper electromigration.

[0002]

2. Description of the Related Art With the increase in the integration of ULSI devices, the dimensional rules for device wiring have become finer, and signal delay due to an increase in capacitance between wires has hindered the speeding up of device operation, which has become a serious problem. In order to solve this problem, reducing the relative dielectric constant of the interlayer insulating film to reduce the capacitance, and replacing the conventional aluminum wiring,
Specific resistance lower than aluminum (specific resistance of aluminum = 2.7 μΩcm, specific resistance of copper = 1.72 μΩc
m) Further, introduction of copper wiring resistant to electromigration and stress migration is being studied.

First, to reduce the capacitance of an interlayer insulating film, a material having a lower dielectric constant than a conventional silicon oxide film-based material (having a relative dielectric constant of about 4.2) has been proposed. This low dielectric constant film is roughly classified into an organic film and an inorganic film. Above all, the relative dielectric constant required for devices of 0.18 μm to 0.13 μm or less is 3 or less, and many organic materials are used to realize the relative dielectric constant. These organic materials are said to have a low dielectric constant by lowering the material density and lowering the polarizability of the molecules themselves by including carbon atoms or fluorine atoms in the film. .

Further, a technique is disclosed in which copper wiring is formed by using a material such as tantalum nitride or tantalum as a barrier metal and using an electrolytic plating technique as a method of embedding copper. A device using the copper wiring has already been disclosed.

On the other hand, in the conventional aluminum wiring, electromigration is liable to occur. Therefore, as a measure against electromigration, a proposal for forming a compensation wiring has been made by the present applicant and disclosed in Japanese Patent Application Laid-Open No. Hei 9-17785. . The present invention has been made to solve the problem of disconnection of wiring due to electromigration, which is a problem peculiar to aluminum wiring.

In addition, the wiring design rule is 0.35 μm.
It has been assumed that electromigration failure does not occur in copper wiring of the m generation or earlier. However, 0.1
The present inventors have found that the same electromigration failure as the aluminum wiring occurs in the copper wiring from around the 8 μm generation.

As shown in FIG. 9, a first interlayer insulating film 11 is formed.
1, a wiring groove 112 is formed, and a first copper wiring 114 is formed in the wiring groove 112 via a barrier metal layer 113. On the first interlayer insulating film 111, a first
A second interlayer insulating film 115 covering the copper wiring 114 is formed. In the second interlayer insulating film 115, the wiring groove 11 is formed.
6, and a connection hole 117 reaching the first copper wiring 114 from the bottom of the wiring groove 116 is formed. Copper is buried in the connection hole 117 and the wiring groove 116 via a barrier metal layer 118, and a second copper wiring 119 is formed in the wiring groove 116 with the buried copper.
The plug 120 is formed in the connection hole 117.

[0008]

The dimensional rules of copper wiring are relatively loose, and there are many problems in applying copper wiring to finer dimensional rules. They are described below.

In order to bury copper inside the connection hole, usually,
Electrolytic plating is used. When performing this electrolytic plating, a copper seed layer is formed inside the connection holes by sputtering in advance. However, as the aspect ratio of the via increases, the coverage of the copper seed layer on the sidewalls within the via becomes significantly degraded. The copper seed layer in this portion is formed very thin due to the characteristics of sputtering. Therefore, when a plug is formed by filling the connection hole with copper by electrolytic plating, a void (cavity) is easily generated. In a buried plug having such voids, the voids gradually become larger at the time of current conduction, and eventually lead to disconnection.

[0010] As shown in FIG. 10, in a plug 120 formed by burying copper, a second interlayer insulating film 115 is formed.
A barrier metal layer 118 made of tantalum nitride, tantalum, or the like is formed on the inner surface of the connection hole 117 in order to prevent copper from diffusing into the connection hole 117. Causes the life of the battery to deteriorate. In the wiring structure made of copper, electrons e ⁻ pass through the plug 120 from the first copper wiring 114,
When flowing toward the second copper wiring 119, the copper in the plug 120 moves toward the second wiring 119 due to the electromigration phenomenon. In this case, since the barrier metal layer 118 is formed on the lowermost layer of the plug 120, the supply of copper from the first copper wiring 114 is cut off. For this reason, copper is insufficient at the portion of the plug 120 where copper has moved, and voids 131 are generated.

In particular, conventionally, it has been considered that electromigration of copper wiring can be neglected. However, according to an experiment conducted by the present inventors, it is necessary to ignore electromigration even for copper wiring for fine wiring of about 0.18 μm. Can not. The present inventor has found that electromigration cannot be ignored particularly when a current having a current density of 500 kA / cm ² or more flows.

As described above, when a void occurs,
A connection failure occurs at the portion where the void is generated, and wiring reliability is significantly impaired. In addition, the copper wiring did not have the expected wiring life, and in some cases, the wiring life was inferior to the conventional wiring structure using an aluminum wiring and a tungsten plug.

[0013]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

The first semiconductor device comprises a first wiring, a second copper wiring made of copper or a copper alloy, an insulating film formed between the first wiring and the second wiring, Wiring and the second
A connection hole formed in the insulating film and reaching the wiring of
A plug made of copper or a copper alloy for connecting the first wiring and the second wiring and having a plug formed inside the connection hole, and a plug made of copper or a copper alloy and directly connected to the plug, It is provided with a compensating pattern formed near the connection with the first wiring.

In the first semiconductor device having the above structure, for example, when a current flows from the second wiring through the plug to the first wiring, electrons flow through the plug from the first wiring in the opposite direction to the current. 2 flows to the wiring. At this time, electromigration occurs. That is, the copper atoms in the plug tend to move in the second wiring direction, which is the same as the direction in which electrons flow. Therefore, a void tends to be generated on the first wiring side of the plug.

In this configuration, the compensation pattern is made of copper or a copper alloy and is directly connected to the plug. The compensation pattern formed near the connection between the plug and the first wiring is provided. Copper atoms are supplied to the plug. Therefore, voids in the plug, which have occurred in the conventional wiring structure, do not occur, and good connection between the first wiring and the plug is maintained. Therefore, the occurrence of disconnection of the wiring due to electromigration is eliminated, and the semiconductor device has high wiring reliability.

The second semiconductor device is formed with a first wiring made of copper or a copper alloy, a second copper wiring made of copper or a copper alloy, and between the first wiring and the second wiring. An insulating film, a connection hole formed in the insulating film to reach the first wiring from the second wiring, and a plug formed inside the connection hole for connecting the first wiring and the second wiring. And a plug made of tungsten, made of copper or a copper alloy, connected at least continuously or directly to the wiring on the side where current flows out in the plug direction, and used for compensation formed near the connection portion with the plug. It has a pattern.

In the second semiconductor device having the above structure, when a current flows from the first wiring through the tungsten plug to the second wiring, electrons flow from the second wiring through the tungsten plug in reverse to the current. It flows to the first wiring. At that time, electromigration occurs. That is,
Copper atoms in the first wiring tend to move in the same direction as the direction in which electrons flow. For this reason, voids tend to be generated at the connection portion between the first wiring and the tungsten plug.
At that time, since copper atoms are supplied to the first wiring from the compensation pattern connected continuously or directly to the first wiring, the generation of voids in the first wiring which occurred in the conventional wiring structure is reduced. Thus, good connection between the first wiring and the tungsten plug is maintained. On the other hand, when a current flows in the opposite direction to the above description, copper atoms are supplied to the second wiring from a compensation pattern connected continuously or directly to the second wiring. The occurrence of voids in the second wiring, which has been performed, is suppressed, and good connection between the second wiring and the tungsten plug is maintained. Therefore, the occurrence of disconnection of the wiring due to electromigration is eliminated, and the semiconductor device has high wiring reliability.

In the first method of manufacturing a semiconductor device, a first wiring having a trench wiring structure is formed in a first insulating film, and then a second insulating film covering the first wiring on the first insulating film is formed. Forming a film, forming a recess having a bottom area larger than the cross-sectional area of the plug in the second insulating film, embedding copper or a copper alloy into the recess via a barrier metal layer, A step of forming a pattern, a step of forming a third insulating film covering the compensation pattern on the second insulating film,
Forming a groove for forming a second wiring in the insulating film and a connection hole communicating with the compensation pattern from the bottom of the groove, and forming a barrier metal layer on the side wall of the connection hole and on the inner surface of the groove. Burying the connection hole and the groove with copper or a copper alloy, forming a second wiring inside the groove, and forming a plug inside the connection hole.

In the method of manufacturing a first semiconductor device having the above-described structure, a connection hole is not formed so as to directly reach the first wiring, and the connection is made to the first wiring. Is formed, and a connection hole is formed so as to reach the compensation pattern. In addition, since a barrier metal layer is formed only on the side wall of the connection hole and a plug is formed by embedding copper or a copper alloy inside the connection hole, the plug is directly connected without the barrier metal. Connected to the compensation pattern. Therefore, when electrons flow from the first wiring to the second wiring via the plug, even if electromigration occurs, copper atoms are supplied from the compensation pattern toward the plug, so that the lower part of the plug is No void is generated in the vicinity of the barrier metal layer. That is, even if electromigration occurs,
The connection between the plug and the first wiring is securely held.

According to a second method of manufacturing a semiconductor device, a method of manufacturing a semiconductor device including a step of forming a wiring made of copper or a copper alloy to be connected to a plug is provided. A manufacturing method characterized in that a compensation pattern made of copper or a copper alloy is formed in the vicinity of a connection portion together with a wiring and integrally with the wiring.

In the second method of manufacturing a semiconductor device having the above-described structure, the plug for connecting the wirings is formed of tungsten which is assumed not to cause electromigration. No voids occur. In addition, since a compensation pattern made of copper or a copper alloy is formed integrally with the wiring at the same time as the wiring near the connection portion with the plug, even if an electromigration causes a void to be generated at a portion where the plug is connected, Copper atoms are supplied to the wiring from the compensation pattern. Therefore, no void is generated in the wiring, and the connection between the plug and the wiring is reliably established.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment relating to a first semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG.

As shown in FIG. 1, a first insulating film 11 is formed on a semiconductor substrate (not shown) to cover an element (not shown) formed on the semiconductor substrate. The first insulating film 11 is formed of, for example, a laminated film of a low dielectric constant organic film and an inorganic film. Here, polyaryl ether is used for the low dielectric constant organic film, and silicon oxide is used for the inorganic film.
In the first insulating film 11, a first groove 12 for burying a first wiring serving as a lower wiring is formed, and the first groove 12 is formed inside the first groove 12 via a barrier metal layer 13. Wiring 14 is formed. The first barrier metal layer 1
3 is, for example, tantalum nitride or tantalum,
It is formed of a metal compound or a metal material that prevents the movement of copper. The first wiring 14 is formed of, for example, copper or a copper alloy.

Further, on the first insulating film 11, a second insulating film 15 covering the first wiring 12 is formed. The second insulating film 15 is formed of, for example, a laminated film of a low dielectric constant organic film and an inorganic film. Here, polyaryl ether is used for the low dielectric constant organic film, and silicon oxide is used for the inorganic film. In the second insulating film 15, a concave portion 16 is formed at the connection portion of the first wiring 14 for reaching the connection portion and having a larger bottom area than the connection portion and for embedding a compensation pattern. Have been.

The barrier metal layer 1 is provided inside the recess 16.
7, a compensation pattern 18 is formed. Therefore, the compensation pattern 18 having an area larger than the connection portion with the first wiring 14 is formed so that the bottom surface and the side surface are wrapped by the second barrier metal layer 17. The barrier metal layer 17 is made of, for example, a metal compound or a metal material such as tantalum nitride or tantalum that prevents the movement of copper. The compensation pattern 18 is formed of, for example, copper or a copper alloy.

Further, a third insulating film 19 covering the compensation pattern 18 is formed on the second insulating film 15. The third insulating film 19 is formed of, for example, a laminated film of a low dielectric constant organic film and an inorganic film. Here, polyaryl ether is used for the low dielectric constant organic film, and silicon oxide is used for the inorganic film. In the third insulating film 19, a second wiring serving as an upper layer wiring is embedded, and a connection hole 20 reaching the compensation pattern 18 is formed. Further, in the upper layer of the third insulating film 19, a second groove 21 for burying a second wiring to be an upper wiring is formed.

In each of the second groove 21 and the connection hole 20, a second wiring 23 is formed via a barrier metal layer 22.
And a plug 24 are formed. The second barrier metal layer 22 is formed of, for example, a metal compound or a metal material such as tantalum nitride or tantalum that prevents the movement of copper. The second wiring 23 and the plug 24 are formed of, for example, copper or a copper alloy.

In the semiconductor device having the above-described wiring structure, the current flows from the second wiring 23 through the plug 24 to the first
, The electron e ⁻ flows from the first wiring 14 to the second wiring 23 through the plug 24 in the opposite direction to the current as shown by the arrow. At this time, electromigration occurs. That is, the copper atom C in the plug 24
u tries to move in the direction of the second wiring 23 which is the same as the direction in which the electrons e ⁻ flow. Therefore, a void is about to be generated on the first wiring 14 side of the plug 24. At this time, since copper atoms Cu are supplied from the compensation pattern 18 to the plug 24, voids in the plug, which have been generated in the conventional wiring structure, do not occur, and a good connection between the first wiring 14 and the plug 24 is obtained. Connection is maintained. On the other hand, the copper atoms in the first wiring 14 are prevented from moving in the direction of the compensation pattern 18 by the barrier metal layer 17 formed on the bottom of the compensation pattern 18, and thus move in the direction of the compensation pattern 18. do not do. Therefore, disconnection of the wiring due to electromigration does not occur, and the semiconductor device has high wiring reliability.

Next, an embodiment of the first method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 2 and 3, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2A, a first insulating film 11 covering an element (not shown) formed on the semiconductor substrate (not shown) is formed on the semiconductor substrate (not shown). . The first insulating film 11 is formed of, for example, a laminated film of a low dielectric constant organic film and an inorganic film. Here, polyaryl ether is used for the low dielectric constant organic film, and silicon oxide is used for the inorganic film. In the first insulating film 11, a first groove 12 for burying a first wiring to be a lower wiring is formed,
A first wiring 14 is formed inside the first groove 12 via a barrier metal layer 13. The first barrier metal layer 13 is formed of, for example, a metal compound or a metal material such as tantalum nitride or tantalum that prevents the movement of copper. The first wiring 14 is
For example, it is formed of copper or a copper alloy.

The first wiring 12 is formed on the first insulating film 11 on which the first wiring 14 is formed as described above.
Is formed to cover the first insulating film. The second insulating film 15 is formed, for example, of a laminated film of a low dielectric constant organic film and an inorganic film.

For example, using a spin coating device, the semiconductor substrate on which the first wiring 14, the first insulating film 11, etc. are formed is placed on a rotary chuck of the spin coating device, and a source solution of the polyaryl ether film is formed. About ³ cm ³ to 5 cm ³ on a semiconductor substrate, and 2500 rpm to 3000 r.
By rotating the rotary chuck at pm, the dropped source solution is spread evenly. After the application is completed,
Baking is performed for 1 minute each in a nitrogen atmosphere at ° C. Further, curing is performed for one hour in a nitrogen atmosphere at 400 ° C. using a curing furnace. Thus, a polyarylether film (relative permittivity = 2.75) covering the first wiring 14 is formed on the first insulating film 11 to a thickness of, for example, 200 nm.

Next, for example, by a plasma CVD method,
A silicon oxide film having a thickness of, for example, 100 nm is formed on the polyaryl ether film. In this plasma CVD method, monosilane (a supply flow rate is, for example, 1
00 sccm) and nitrous oxide (the supply flow rate is, for example, 40
0 sccm to 600 sccm) and a plasma CV
RF power of D device (13.56 MHz) 0.35k
W, the pressure of the film formation atmosphere is 667 Pa, and the substrate temperature is 400
The film was formed by setting the temperature to ° C. As a result, a second insulating film 15 in which a silicon oxide film having a thickness of 100 nm was formed on a polyaryl ether film having a thickness of 200 nm was formed.

Next, the second spin coating method is used.
After a resist film (not shown) used in the ordinary lithography technique is formed on the insulating film 15, the opening having a larger bottom area than the portion to be connected to the first wiring 14 is formed by the lithography technique. A part (not shown) is formed. Next, the second insulating film 15 is etched using the resist film as an etching mask to reach a connection portion with the first wiring 14 and to have a bottom area larger than the connection portion to form a compensation pattern. A recess 16 for embedding is formed. The recess 16 has, for example,.
It is formed in a size of about 3 μm to 0.6 μm square.

In the etching of the silicon oxide film of the second insulating film 15, as an example, a magnetron type plasma etching apparatus is used, and octafluorobutene (C ₄ F ₈ ) is used as an etching gas (the supply flow rate is, for example, 14 sc).
cm) and carbon monoxide (CO) (supply flow rate is, for example, 250
sccm) and argon (Ar) (supply flow rate is, for example, 10
0 sccm) and oxygen (O ₂ ) (supply flow rate is ₂ sc
cm), the power was set to 0.6 kW, the pressure of the etching atmosphere was set to 5.3 Pa, and the substrate temperature was set to 20 ° C. to perform etching.

In the etching of the polyarylether film of the second insulating film 15, as an example, electron cyclotron resonance (hereinafter referred to as ECR, ECR is Electron C
A nitrogen (N ₂ ) (supply flow rate is, for example, 40 sccm) and helium (He) (supply flow rate is, for example, 165 sccm) etching gas, and a microwave power of 0.1 is used. 5 kW, the substrate bias RF was set to 0.1 kW, the pressure of the etching atmosphere was set to 0.8 Pa, the substrate temperature was set to −50 ° C., and etching was performed using the silicon oxide film as a hard mask until the first wiring 14 was exposed. Was.

Subsequently, the first wiring 1 exposed at the bottom of the recess 16 is etched by argon sputter etching.
The insulator (for example, a natural oxide film) on the surface of No. 4 is removed.
This argon sputter etching is performed, for example, under the condition of etching a silicon oxide film by about 20 nm.

Next, the above-mentioned concave portion 1 is formed by sputtering.
6, a barrier metal layer 17 is formed with a thickness of, for example, 30 nm. The barrier metal layer 17 is, for example,
It is formed of a metal compound or a metal material such as tantalum nitride or tantalum that prevents the transfer of copper. In the above sputtering, a long-distance sputtering method or an ionization sputtering method is used as an example.

Next, the above-mentioned concave portion 1 is formed by sputtering.
6, a copper seed layer (not shown) is formed with a thickness of, for example, 50 nm to 200 nm via a barrier metal layer 17. In this sputtering, for example, a long-distance sputtering method or an ionization sputtering method is used. Next, copper is deposited on the surface of the copper seed layer by, for example, electrolytic plating, and the inside of the recess 16 is filled with copper. Thereafter, chemical mechanical polishing (hereinafter referred to as CMP)
By using mechanical mechanical polishing, the excess copper and the barrier metal layer 17 on the second insulating film 15 are removed, and the compensation pattern 18 is made of copper left inside the recess 16 via the barrier metal layer 17. Form. Further, the compensation pattern 18 may be formed of a copper alloy.

Next, as shown in FIG. 2B, for example, in the same manner as when the first insulating film 11 is formed,
On the second insulating film 15, a polyarylether film covering the compensation pattern 18 is formed to a thickness of, for example, 400 nm. Next, a silicon oxide film having a thickness of, for example, 500 nm is formed on the polyarylether film. Thereafter, the silicon oxide film is polished by a thickness of about 300 nm by CMP to flatten the surface, and a 200 nm-thick silicon oxide film is formed on a 400 nm-thick polyarylether film. The lower part of the film 19, that is, the part where the connection hole is formed is formed.

Subsequently, an intermediate layer 31 serving as an etching mask and an etching stopper is formed of, for example, a 50 nm-thick silicon nitride film on the lower layer of the third insulating film 19 by, for example, a plasma CVD method. Next, a resist film (not shown) used in a normal lithography technique
Is formed, an opening (not shown) for forming a connection hole in the resist film is formed by lithography. Next, the intermediate layer 31 is etched using the resist film as an etching mask to form an upper portion of the connection hole 20.

Next, as shown in FIG. 2C, for example, a polyaryl covering the upper part of the connection hole 20 is formed on the intermediate layer 31 in the same manner as the lower part of the third insulating film 19 is formed. An ether film is formed to a thickness of, for example, 300 nm. Next, a silicon oxide film having a thickness of, for example, 500 nm is formed on the polyarylether film. After that, the silicon oxide film was polished by a thickness of about 300 nm by CMP to planarize the surface, and a 200 nm-thick silicon oxide film was formed on the 300 nm-thick polyarylether film. An upper layer portion of the film 19, that is, a portion where a trench wiring is formed is formed.

Next, after forming a resist film (not shown) used in a normal lithography technique, an opening (not shown) for forming a wiring groove is formed in the resist film by a lithography technique. Next, the upper layer of the third insulating film 19 is etched using the resist film as an etching mask to form a second groove 21 serving as a wiring groove.

In the etching of the silicon oxide film in the upper layer of the third insulating film 19, as an example, a magnetron type plasma etching apparatus is used, and octafluorobutene (C ₄ F ₈ ) is used as an etching gas (the supply flow rate is, for example, 14 sccm), carbon monoxide (CO) (supply flow rate is, for example, 250 sccm), argon (Ar) (supply flow rate is, for example, 100 sccm), and oxygen (O ₂ ) (supply flow rate is, for example, 2 sccm). 6
Etching was performed at kW, a pressure of an etching atmosphere of 5.3 Pa, and a substrate temperature of 20 ° C.

In the etching of the polyaryl ether film in the upper layer of the third insulating film 19, as an example, an ECR type plasma etching apparatus is used, and nitrogen (N ₂ ) is used as an etching gas (the supply flow rate is, for example, 40 seconds).
ccm) and helium (He) (supply flow rate is, for example, 165).
sccm) and a microwave power of 0.5 kW,
The substrate bias RF was set to 0.1 kW, the pressure of the etching atmosphere was set to 0.8 Pa, the substrate temperature was set to −50 ° C., and etching was performed using the silicon oxide film as a hard mask until the intermediate layer 31 was exposed. In this etching,
Since the intermediate layer 31 is formed of a silicon nitride film, it functions as an etching stopper. In this manner, the second groove 2 serving as a wiring groove is formed in the third insulating film 19.
Form one.

Next, using the intermediate layer 31 as an etching mask, the silicon oxide film and the polyaryl ether film in the lower layer of the third insulating film 19 are etched under the same etching conditions as above to form the connection holes 20. .

Next, the insulator (for example, a natural oxide film) on the surface of the compensation pattern 18 exposed at the bottom of the connection hole 20 is removed by argon sputter etching. This argon sputter etching, for example,
The etching is performed under the condition that the silicon oxide film is etched by about 30 nm. For example, an etching device of an inductively coupled plasma type (hereinafter referred to as ICP, ICP is an abbreviation for Inductively Coupled Plasma) is used, and argon (A) is used as an etching gas.
r) (the supply flow rate is, for example, 50 sccm to 300 sccc)
m), the ICP power is 0.7 kW to 1.5 kW,
Substrate bias (RF = 13.56 MHz) from 100 V
The test was performed at 300 V.

Next, as shown in FIG. 3D, a second barrier metal layer 22 having a thickness of, for example, 30 nm is formed inside each of the second groove 21 and the connection hole 20 by sputtering.
It is formed to a thickness of 50 nm. The second barrier metal layer 22 is formed of, for example, a metal compound or a metal material such as tantalum nitride or tantalum that prevents the movement of copper. In the above sputtering,
As an example, a long-distance sputtering method or an ionization sputtering method is used.

Next, as shown in FIG. 3 (5), the second barrier metal layer 22 formed at the bottom of the connection hole 20 is removed by argon sputter etching again, and the above-mentioned compensation pattern 18 is removed. Expose the surface.

Next, as shown in FIG. 3 (6), the second groove 21 and the connection hole 2 are formed by sputtering.
0, a copper seed layer (not shown) is formed with a thickness of, for example, 100 nm to 200 nm via the second barrier metal layer 22. In this sputtering, for example, a long-distance sputtering method or an ionization sputtering method is used. Next, copper is deposited on the surface of the copper seed layer by, for example, electrolytic plating, and the insides of the second groove 21 and the connection hole 20 are filled with copper. After that, the excess copper on the third insulating film 19 and the second barrier metal layer 22 are removed by CMP, and the copper remaining in the second groove 21 via the second barrier metal layer 22 is removed. The second wiring 23
Is formed, and a plug 24 is formed of copper left inside the connection hole 20 via the second barrier metal layer 22.

In the above-described manufacturing method, the first wiring 1 is formed without forming the connection hole 20 so as to directly reach the first wiring 14.
4, a compensating pattern 18 wrapped around the bottom and side surfaces by a barrier metal layer 17 is formed, and a connection hole 20 is formed so as to reach the compensating pattern 18.
Moreover, after the second barrier metal layer 22 is formed inside the connection hole 20, the second barrier metal layer at the bottom of the connection hole 20 is removed, and copper is embedded inside the connection hole 20. Since the plug 24 is formed, the plug 2
4 is directly connected to the compensation pattern 18 without the intervention of a barrier metal. Therefore, when electrons flow from the first wiring 14 to the second wiring 23 via the plug 24, even if electromigration occurs, the electron flows from the compensation pattern 18 outside the portion to which the plug 24 is connected. Since copper atoms are supplied toward the plug 24, voids are not generated in the compensation pattern 18 near the barrier metal layer 17 below the plug 24. That is, even if electromigration occurs, the connection between the plug 24 and the first wiring 14 is
This is ensured through the compensation pattern 18.

The first insulating film 11 and the second insulating film 15
The third insulating film 19 is not limited to the insulating film having the above structure, and each insulating film can be formed by a single insulating film. However, in that case, the first insulating film 11 and the second insulating film 15 and the second insulating film 15 and the third insulating film 19 are preferably formed using materials having different etching characteristics. That is, when etching the third insulating film 19, the material of each insulating film is selected so that the second insulating film 15 serves as an etching stopper, and when the second insulating film 15 is etched, the first material is selected. It is preferable to select the material of each insulating film so that the insulating film 11 serves as an etching stopper. When the first, second, and third insulating films 11, 15, and 19 are all formed of the same insulating film material, it is necessary to form an etching stopper layer made of an insulating film between the insulating films. is there. When the etching stopper layer is not provided, the first and second grooves 12 and 21
And in etching for forming the connection hole 20,
The respective depths may be determined by controlling the etching time.

Next, an embodiment according to the second semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG.

As shown in FIG. 4, on a semiconductor substrate (not shown), a first insulating film 41 for covering an element (not shown) formed on the semiconductor substrate is formed. The first insulating film 41 is formed of, for example, a laminated film of a low dielectric constant organic film and an inorganic film. Here, polyaryl ether is used for the low dielectric constant organic film, and silicon oxide is used for the inorganic film.
In the first insulating film 41, a first groove 42 for embedding a first wiring serving as a lower wiring and a first compensation pattern for compensating movement of copper atoms due to electromigration is formed. .

The first wiring 44 and the first compensation pattern 61 are formed in the first groove 42 in a continuous state via the barrier metal layer 43. The first compensation pattern 61 is formed so as to be connected at least partially around the first wiring 44 to which a tungsten plug 48 described later is connected. Therefore, as shown in the drawing, the first compensation pattern 61 may be formed in a state where the first wiring 44 is extended in the wiring length direction beyond the portion where the tungsten plug 48 is connected. Although not shown, it may be formed on the side circumference of the first wiring 44 to which the tungsten plug 48 is connected, or may be formed on the lower surface side of the first wiring 44 immediately below the tungsten plug 48. That is, the first compensation pattern 61 may be formed at a position where copper atoms can be supplied to the portion of the first wiring 44 to which the tungsten plug 48 is connected. The first barrier metal layer 43 is formed of, for example, a metal compound or a metal material such as tantalum nitride or tantalum that prevents the movement of copper. The first wiring 44 is formed of, for example, copper or a copper alloy.

Further, on the first insulating film 41, a second insulating film 45 covering the first wiring 42 and the first compensation pattern 61 is formed. The second insulating film 45 is formed of, for example, a laminated film of a low dielectric constant organic film and an inorganic film. Here, polyaryl ether is used for the low dielectric constant organic film, and silicon oxide is used for the inorganic film. A connection hole 46 is formed in the second insulating film 45 so as to reach a position where a tungsten plug 48 is to be connected to the first wiring 44. A tungsten plug 48 is formed inside the connection hole 46 via an adhesion layer 47. The adhesion layer 47 is formed of, for example, a laminated film of a titanium film and a titanium nitride film.

Further, a third insulating film 49 covering the tungsten plug 48 is formed on the second insulating film 45. The third insulating film 49 is formed of, for example, a laminated film of a low dielectric constant organic film and an inorganic film. Here, polyaryl ether is used for the low dielectric constant organic film, and silicon oxide is used for the inorganic film. In the third insulating film 49, a second groove 50 for embedding a second wiring serving as an upper wiring and a second compensation pattern for compensating for the movement of copper atoms due to electromigration is formed in the second insulating film 49. At the bottom of the groove 50, at least the upper surface of the tungsten plug 48 is formed to be exposed.

A second wiring 52 and a second compensating pattern 62 are formed inside the second groove 50 via a barrier metal layer 51 in a continuous state. The second compensation pattern 62 is formed so as to be connected at least partially around the second wiring 52 to which the tungsten plug 48 is connected. Therefore, as shown in the drawing, the second wiring 52 is connected to the tungsten plug 4
The second compensating pattern 62 may be formed so as to extend in the wiring length direction beyond the portion to which the tungsten plug 8 is connected. Although not shown in the drawing, the second wiring 52 to which the tungsten plug 48 is connected is formed. And may be formed on the upper surface side of the second wiring 52 immediately above the tungsten plug 48. That is, the second compensation pattern 62 may be formed at a position where copper atoms can be supplied to the portion of the second wiring 52 to which the tungsten plug 48 is connected. The second barrier metal layer 51 is formed of a metal compound or a metal material such as tantalum nitride or tantalum that prevents the movement of copper. The second wiring 52 is formed of, for example, copper or a copper alloy.

In the semiconductor device having the above structure, the first wiring 4
Although the fourth and second wirings 52 are both trench wirings, ordinary copper wirings patterned on the interlayer insulating film by etching may be used. In this configuration, a barrier metal layer is formed at the interface between the wiring and the interlayer insulating film,
Also, a barrier metal layer is formed so as to cover the surface (upper surface and side surface) of the wiring.

[0061] In the semiconductor device having a wiring structure of the above configuration, as shown in FIG. 5, when flowing through the second wiring 52 current through the tungsten plug 48 from the first wire 44, electrons e ^- are current Conversely, it flows from the second wiring 52 to the first wiring 44 through the tungsten plug 48. At that time, electromigration occurs. That is, the copper atoms Cu in the first wiring 44 tend to move in the same direction as the direction in which the electrons e ⁻ flow (the direction indicated by the arrow). Therefore, the tungsten plug 4 of the first wiring 44
A void is about to be generated at the connection portion with No. 8. At this time, since copper atoms Cu are supplied from the first compensation pattern 61 to the first wiring 44, the occurrence of voids in the first wiring 44 which is generated in the conventional wiring structure is suppressed, and Good connection between the first wiring 44 and the tungsten plug 48 is maintained. On the other hand, the copper atoms in the second wiring 52
Plug 48 by the barrier metal layer 51 of FIG.
The movement of the tungsten plug 4
Does not move in eight directions.

As shown in FIG. 6, when a current flows from the second wiring 52 to the first wiring 44 through the tungsten plug 48, the electron e ⁻ flows from the first wiring 44 in reverse to the current. Second wiring 5 through tungsten plug 48
Flow to 2. At that time, electromigration occurs. That is, the copper atoms Cu in the second wiring 52 tend to move in the same direction as the direction in which the electrons e ⁻ flow (the direction indicated by the arrow). Therefore, a void is likely to be generated at a connection portion between the second wiring 52 and the tungsten plug 48. At this time, since copper atoms Cu are supplied from the second compensation pattern 62 to the second wiring 52, the generation of voids in the second wiring 52 which has been generated in the conventional wiring structure is suppressed, and Good connection between the second wiring 52 and the tungsten plug 48 is maintained. On the other hand, the copper atoms in the first wiring 44 are not moved in the direction of the tungsten plug 48 because they are prevented from moving in the direction of the tungsten plug 48 by the tungsten plug 48 and the adhesion layer 47.

Therefore, the occurrence of disconnection of the wiring due to electromigration is eliminated, and the semiconductor device has high wiring reliability.

Next, a first embodiment of the second method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. In FIG. 7, the same components as those described with reference to FIG. 4 are denoted by the same reference numerals.

As shown in FIG. 7, an element (not shown) formed on a semiconductor substrate (not shown)
An insulating film (not shown) is formed to cover. On this insulating film, for example, a first insulating film 41 is formed. This first
The insulating film 41 is formed of, for example, a laminated film of a low dielectric constant organic film and an inorganic film. Here, polyaryl ether is used for the low dielectric constant organic film, and silicon oxide is used for the inorganic film.

The above-mentioned polyaryl ether film is formed as follows. As an example, using a spin coating device, the semiconductor substrate on which the above-described elements and the like are formed is placed on a rotary chuck of the spin coating device, and the source solution of the polyarylether film is placed in 3c.
m ³ to 5 cm ³ approximately, by rotating the rotating chuck with 2500rpm~3000rpm with dripped onto the semiconductor substrate, uniformly spread the dripped source solution. After the application is completed, baking is performed for 1 minute in a nitrogen atmosphere at 150 ° C. and 250 ° C., respectively. Further, curing is performed for one hour in a nitrogen atmosphere at 400 ° C. using a curing furnace.
In this way, a polyarylether film (relative permittivity = 2.75) covering the element on the semiconductor substrate is, for example, 500 n
m.

Next, the silicon oxide film is formed.
As an example, a silicon oxide film is formed on the polyaryl ether film by, for example, 500 nm by a plasma CVD method.
m. In this plasma CVD method, monosilane (a supply flow rate is, for example, 100 scc)
m) and nitrous oxide (supply flow rate is, for example, 400 sccm
６００600 sccm) and R of the plasma CVD apparatus.
The film was formed by setting the F (13.56 MHz) power to 0.35 kW, the pressure of the film formation atmosphere to 667 Pa, and the substrate temperature to 400 ° C. In this way, a silicon oxide film covering the element is formed on the polyaryl ether
Formed to a thickness of

Thereafter, the silicon oxide film is polished by CMP to a thickness of about 300 nm to planarize the surface.
200 on a 500 nm thick polyarylether film
First insulating film 4 formed with a silicon oxide film having a thickness of nm.
1 was formed.

Next, after forming a resist film (not shown) used in the ordinary lithography technique on the first insulating film 41 by the ordinary spin coating method, the first wiring and the first wiring are formed by the lithography technique. An opening (not shown) for forming the first groove 42 for embedding the first compensation pattern is formed. Next, the first insulating film 41 is etched using the resist film as an etching mask to form a first groove 42.

In the etching of the silicon oxide film of the first insulating film 41, as an example, a magnetron type plasma etching apparatus is used, and octafluorobutene (C ₄ F ₈ ) is used as an etching gas (the supply flow rate is, for example, 14 sc).
cm) and carbon monoxide (CO) (supply flow rate is, for example, 250
sccm) and argon (Ar) (supply flow rate is, for example, 10
0 sccm) and oxygen (O ₂ ) (supply flow rate is ₂ sc
cm), the power was set to 0.6 kW, the pressure of the etching atmosphere was set to 5.3 Pa, and the substrate temperature was set to 20 ° C. to perform etching.

In the etching of the polyarylether film of the first insulating film 41, as an example, an ECR type plasma etching apparatus is used, and nitrogen (N ₂ ) (supply flow rate is, for example, 40 sccm) and helium ( He) (the supply flow rate is, for example, 165 sccm), the microwave power is 0.5 kW, and the substrate bias RF is used.
0.1 kW, the pressure of the etching atmosphere is 0.8 Pa,
The substrate temperature was set to −50 ° C., and the polyarylether film was etched using the silicon oxide film as a hard mask. At this time, the insulating film functions as an etching stopper. Therefore, it is desirable that the uppermost layer of the insulating film is formed of, for example, an inorganic insulating film which serves as an etching stopper when at least the polyarylether film is etched. Note that as long as it has a function as an etching stopper, it may be formed of a low dielectric constant organic insulating film.

Next, an insulator (eg, a natural oxide film) on the surface of the metal film pattern exposed at the bottom of the first groove 42 is removed by argon sputter etching. This argon sputter etching, for example,
The etching is performed under the condition that the silicon oxide film is etched by about 30 nm. For example, using an inductively coupled plasma type etching apparatus, using argon (Ar) (a supply flow rate is, for example, 50 sccm to 300 sccm) as an etching gas,
CP power (coil applied RF = 450 kHz) 0.7
kW to 1.5 kW, substrate bias (RF = 13.56M
Hz) was set to 100 V to 300 V.

Then, a first barrier metal layer 43 is formed in the first groove 42 by sputtering, for example, for 30 minutes.
It is formed to a thickness of nm. This first barrier metal layer 43
Is formed of, for example, a metal compound or a metal material such as tantalum nitride or tantalum which prevents the transfer of copper. In the above sputtering, a long-distance sputtering method or an ionization sputtering method is used as an example.

Next, a copper seed layer (not shown) is formed to a thickness of, for example, 50 nm to 200 nm in the first groove 42 via the first barrier metal layer 43 by sputtering. In this sputtering, for example, a long-distance sputtering method or an ionization sputtering method is used.

Next, copper is deposited on the surface of the copper seed layer by, for example, electrolytic plating, and the inside of the first groove 42 is filled with copper. After that, the excess copper and the first barrier metal layer 43 on the first insulating film 41 are removed by CMP, and the first barrier metal layer 4 is formed inside the first groove 42.
The first wiring 44 and the first compensating pattern 61 connected to the first wiring 44 are formed with the copper left through the third wiring 44.

Next, for example, in the same manner as the formation of the first insulating film 41, a polyaryl ether covering the first wiring 44 and the first compensation pattern 61 is formed on the first insulating film 41. The film is formed to a thickness of, for example, 500 nm. Next, a silicon oxide film having a thickness of, for example, 500 nm is formed on the polyaryl ether film. After that, the silicon oxide film is polished by a thickness of about 300 nm by CMP to planarize the surface, and a 200-nm-thick silicon oxide film is formed on a 500-nm-thick polyarylether film. A film 45 is formed.

Next, after forming a resist film (not shown) used in the ordinary lithography technique on the second insulating film 45, an opening () for forming a connection hole in the resist film is formed by the lithography technique. (Not shown). Next, using the resist film as an etching mask, the second insulating film 45 is etched to form a connection hole 46. This connection hole 46 is, for example, 0.15 μm to 0.30 μm.
It is formed with a diameter of about μm. The second insulating film 4
The etching of 5 may be performed under the same conditions as the etching of the first insulating film 41.

Next, the semiconductor substrate is heated to remove moisture absorbed by the second insulating film 45, the first insulating film 41, and the like due to exposure to the air. This heat treatment
As an example, heating was performed in a non-oxidizing atmosphere at 350 ° C. for 10 minutes. The non-oxidizing atmosphere may be an industrial vacuum atmosphere.

Subsequently, the surface of the first wiring 44 exposed at the bottom of the connection hole 46 is soft-etched without exposing the semiconductor substrate to the atmosphere. This soft etching is performed, for example, under the condition that the silicon oxide film is etched by about 30 nm. For example, by using an ICP type etching apparatus, argon (A
r) (the supply flow rate is, for example, 50 sccm to 300 sccc)
m) and hydrogen (H ₂ ) (the supply flow rate is, for example, 0 sccm to 3 sc).
00 sccm) and ICP power (coil applied R
F = 450 kW) 0.7 kW to 1.5 kW, substrate bias (RF = 13.56 MHz) 100 V to 300 V
I went to set. In this soft etching, an insulator (for example, a natural oxide film) on the surface of the first wiring 44 is removed by a stopper action of argon ions or a reducing action of hydrogen radicals.

Next, an adhesion layer 47 is formed inside each of the connection holes 46 by sputtering, for example, a titanium film is formed to a thickness of 20 nm from the lower layer, and a titanium nitride film is formed to a thickness of 5 nm.
A film is formed to a thickness of 0 nm, and a tungsten film is further formed to a thickness of 50 nm. In the above sputtering, a long-distance sputtering method or an ionization sputtering method is used as an example.

Next, using a tungsten CVD apparatus, tungsten is deposited so as to fill the inside of the connection hole 46. The tungsten CVD condition is, for example, that the process gas is tungsten hexafluoride (WF ₆ ).
(The supply flow rate is, for example, 15 sccm), hydrogen (H ₂ ) (the supply flow rate is, for example, 400 sccm), and monosilane (SiH).
₄ ) (The supply flow rate is, for example, 4 sccm) and argon (A
r) (supply flow rate is, for example, 500 sccm), the substrate temperature is set at 375 ° C., and nucleation is performed.
Using tungsten hexafluoride (WF ₆ ) (supply flow rate is, for example, 80 sccm), hydrogen (H ₂ ) (supply flow rate is, for example, 2000 sccm) and argon (Ar) (supply flow rate is, for example, 1000 sccm) as the process gas, and controlling the substrate temperature. Embedding was performed at 375 ° C.

After that, the excess adhesive layer 47 and the tungsten on the second insulating film 45 are removed by etch back or CMP to form a tungsten plug 48 with the adhesive layer 47 inside the connection hole 46.

Next, in the same manner as the formation of the second insulating film 45, a polyarylether film covering the tungsten process 48 is formed on the second insulating film 45 by, for example, 500
It is formed to a thickness of nm. Next, a silicon oxide film having a thickness of, for example, 500 nm is formed on the polyarylether film. Thereafter, the silicon oxide film is polished by a thickness of about 300 nm by CMP to flatten the surface,
A third insulating film 49 in which a silicon oxide film having a thickness of 200 nm is formed on the polyaryl ether film.

Next, after forming a resist film (not shown) used in a normal lithography technique on the third insulating film 49 by a usual spin coating method, a second film is formed on the resist film by a lithography technique. An opening (not shown) for forming a second groove for embedding the wiring and the second compensation pattern is formed. Next, the third insulating film 49 is etched using the resist film as an etching mask to form a second groove 50.

In the etching of the silicon oxide film in the third insulating film 49, for example, a magnetron-type plasma etching apparatus is used, and octafluorobutene (C ₄ F ₈ ) is used as an etching gas (supply flow rate is, for example, 1
4 sccm), carbon monoxide (CO) (supply flow rate is, for example, 250 sccm), argon (Ar) (supply flow rate is, for example, 100 sccm), and oxygen (O ₂ ) (supply flow rate is, for example, 2 sccm). Etching was performed at a setting of 6 kW, a pressure of an etching atmosphere of 5.3 Pa, and a substrate temperature of 20 ° C.

In the etching of the polyarylether film in the third insulating film 49, as an example, EC
Using an R-type plasma etching apparatus, nitrogen (N ₂ ) (supply flow rate is, for example, 40 sccm) and helium (He) (supply flow rate is, for example, 165 sccm) as etching gas.
, A microwave power of 0.5 kW, a substrate bias RF of 0.1 kW, and an etching atmosphere pressure of 0.8 kW.
Pa, the substrate temperature was set to −50 ° C., and etching was performed using the silicon oxide film as a hard mask until the tungsten plug 48 was exposed. In this etching, the silicon oxide film of the second insulating film 45 functions as an etching stopper. Thus, the second groove 50 is formed in the third insulating film 49.

Subsequently, the surface of the tungsten plug 48 exposed at the bottom of the second groove 50 is soft-etched without exposing the semiconductor substrate to the atmosphere. This soft etching is performed, for example, under the condition that the silicon oxide film is etched by about 30 nm. For example, IC
Using a P-type etching apparatus, the etching gas is argon (Ar) (supply flow rate is, for example, 50 sccm to 300 sc).
sccm) and hydrogen (H ₂ ) (the supply flow rate is, for example, 0 scc)
m-300 sccm), the ICP power (coil applied RF = 450 kW) is 0.7 kW-1.5 kW, and the substrate bias (RF = 13.56 MHz) is 100 V-3.
It was set at 00V. In this soft etching,
The insulator (for example, a natural oxide film) on the surface of the tungsten plug 48 is removed by a sputtering action of argon ions or a reducing action of hydrogen radicals.

Next, a second barrier metal layer 51 is formed inside the second groove 50 by sputtering, for example, 50.
It is formed to a thickness of nm. This second barrier metal layer 50
Is formed of, for example, a metal compound or a metal material such as tantalum nitride or tantalum which prevents the transfer of copper. In the above sputtering, a long-distance sputtering method or an ionization sputtering method is used as an example.

Subsequently, a copper seed layer (not shown) is formed in the second groove 50 via the second barrier metal layer 51 by sputtering, for example, in a thickness of 100 nm to 200 nm.
Formed to a thickness of In this sputtering, for example, a long-distance sputtering method or an ionization sputtering method is used.

Next, copper is deposited on the surface of the copper seed layer by, for example, electrolytic plating, and the inside of the second groove 50 is filled with copper. Thereafter, the third insulating film 49 is formed by CMP.
Excess copper and the second barrier metal layer 51 are removed, and the second wiring 52 and the second wiring 52 are continuously formed with the copper left inside the second groove 50 via the second barrier metal layer 51. A second compensation pattern 62 to be connected is formed.

In the above manufacturing method, the first wiring 44 and the second
Tungsten plug 4 which is assumed to be free from electromigration in order to connect
The formation of 8 prevents voids from occurring in the tungsten plug 48 even if current flows through the tungsten plug 48. Further, a first compensation pattern 61 connected to the first wiring 44 is formed, and a second wiring 52 is formed.
The second compensation pattern 62 connected to the first wiring 44 is formed on the first wiring 44 even if a void is generated in the portion to which the tungsten plug 48 is connected due to electromigration. Copper atoms are supplied from 61, and copper atoms are supplied to the second wiring 52 from the second compensation pattern 62. Therefore, no void is generated in the first wiring 44 and the second wiring 52, and the connection between the tungsten plug 48 and the first wiring 44 and the second wiring 52 is ensured.

The first insulating film 41 and the second insulating film 45
In addition, the third insulating film 49 is not limited to the insulating film having the above structure, and each insulating film can be formed of a single insulating film. However, in that case, it is preferable that the first insulating film 41 and the second insulating film 45 and the second insulating film 45 and the third insulating film 49 be formed using materials having different etching characteristics. That is, when etching the third insulating film 49, the material of each insulating film is selected so that the second insulating film 45 serves as an etching stopper, and when the second insulating film 45 is etched, the first material is selected. It is preferable to select the material of each insulating film so that the insulating film 41 serves as an etching stopper. When the first, second, and third insulating films 41, 45, and 49 are all formed of the same insulating film material, it is necessary to form an etching stopper layer made of an insulating film between the insulating films. is there. If the etching stopper layer is not provided, the first and second grooves 42 and 50
In the etching at the time of forming the layers, the respective depths may be determined by controlling the etching time.

In the above configuration, both the first wiring 44 and the second wiring 52 are formed by trench wiring. However, a metal layer for forming wiring is formed on the insulating film, and the usual lithography technique and etching are performed. A wiring structure in which a wiring pattern is formed by etching the metal layer depending on technology may be used.

Next, a description will be given of a second embodiment of a method of manufacturing a semiconductor device in the case where a copper wiring is formed by patterning using ordinary lithography and etching techniques, with reference to FIG.

As shown in FIG. 8, an element (not shown) formed on a semiconductor substrate (not shown) is formed on the semiconductor substrate (not shown).
A first insulating film 71 is formed to cover the first insulating film 71. On the first insulating film 71, a lower barrier metal layer 72 and an adhesion layer 7
3. A wiring forming layer 74, an upper barrier metal layer 75, and the like are sequentially formed. As an example, the lower barrier metal layer 72 is formed by depositing tantalum or tantalum nitride to a thickness of 30 nm, the adhesion layer 73 is formed by depositing tungsten to a thickness of 20 nm, and the wiring forming layer 74 is formed by depositing copper of 300 nm. The upper barrier metal layer 75 is formed by depositing titanium nitride to a thickness of 30 nm. These films are formed using an existing sputtering device, CVD device, or the like. Desirably, film formation is performed continuously without exposure to an atmosphere containing oxygen. Further, a hard mask layer (not shown) is formed of, for example, a silicon oxide film.

Next, after forming a resist film (not shown) used in the ordinary lithography technique on the hard mask layer by the ordinary spin coating method, the first wiring and the first wiring are formed by the lithography technique. A hard mask pattern (not shown) for patterning the compensation patterning is formed. After that, the resist film is removed. Next, using the hard mask pattern as an etching mask, the upper barrier metal layer 75, the wiring forming layer 74, the adhesion layer 73, and the lower barrier metal layer 72 are sequentially etched to form the first wiring 76 and the first wiring 76 successively. And a first compensating pattern 91 to be formed.

The etching for forming the first wiring 76 and the first compensation pattern 91 was performed in three stages using, for example, a helicon wave plasma etching apparatus. As an example of the etching conditions, in the first stage etching, boron trichloride (BC) is used as an etching gas.
l ₃ ) (supply flow rate is, for example, 10 sccm) and chlorine (Cl
₂ ) (supply flow rate is, for example, 10 sccm), the pressure of the film formation atmosphere is 0.1 Pa, the helicon wave source power is 0.15 kW, the RF bias is 0.3 W, and the stage temperature for mounting the substrate is 250 ° C. Set. In the etching of the second stage, chlorine (Cl ₂ ) (supply flow rate is, for example, 10 sccm) is used as an etching gas, the pressure of the film formation atmosphere is 0.05 Pa, and the helicon wave source power is 0.15 k.
W, the RF bias was set to 0.3 W, and the stage temperature for mounting the substrate was set to 240 ° C. In the etching of the third stage, difluoromethane (CH ₂ F ₂ ) is used as an etching gas.
(The supply flow rate is, for example, 10 sccm) and chlorine (Cl ₂ )
(The supply flow rate was, for example, 10 sccm), the pressure of the deposition atmosphere was set to 0.05 Pa, the helicon wave source power was set to 0.15 kW, the RF bias was set to 0.3 W, and the stage temperature for mounting the substrate was set to 240 ° C. .

Next, a second insulating film 77 covering the first wiring 76 is formed on the first insulating film 71 by, for example, 50
It is formed of a polyarylether film having a thickness of 0 nm.

Next, a third insulating film 78 is formed on the second insulating film 77 by, for example, a silicon oxide film having a thickness of 1.40 μm. Thereafter, the third insulating film 78 is polished by CMP to a thickness of about 600 nm to planarize the surface, and an interlayer insulating film including the third insulating film 78 and the second insulating film 77 in which connection holes are formed. Form a film.

Next, the third spin coating is performed by a usual spin coating method.
After a resist film (not shown) used in the ordinary lithography technique is formed on the insulating film 78, an opening is formed on the position where a plug for connecting the first wiring 76 and the upper wiring is formed by the lithography technique. A part (not shown) is formed. Next, the third insulating film 78 and the second insulating film 77 are etched using the resist film as an etching mask to form a connection hole 79 reaching a region where a predetermined connection hole of the first wiring 76 is formed. I do. After that, the resist film is removed.

In the above etching, the third etching is performed under the same etching conditions as those described in the first embodiment.
Of the insulating film 78 and the second insulating film 77 are performed.

Next, the semiconductor substrate is heated to remove moisture absorbed by the third insulating film 78, the second insulating film 77, and the like due to exposure to the air. This heat treatment
As an example, heating was performed in a non-oxidizing atmosphere at 350 ° C. for 10 minutes. The non-oxidizing atmosphere may be an industrial vacuum atmosphere.

Subsequently, the surface of the first wiring 76 exposed at the bottom of the connection hole 79 is soft-etched without exposing the semiconductor substrate to the atmosphere. This soft etching is performed under the same conditions as described above. In this soft etching, an insulator (for example, a natural oxide film) on the surface of the first wiring 76 is removed by a stopper action of argon ions or a reducing action of hydrogen radicals.

Next, an adhesion layer 80 is formed in the connection hole 79 by sputtering, for example, a titanium film is formed to a thickness of 20 nm from the lower layer, and a titanium nitride film is formed to a thickness of 50 nm.
The film is formed to have a thickness of nm. Further, a tungsten film is formed to a thickness of 50 nm. In the above sputtering, a long-distance sputtering method or an ionization sputtering method is used as an example.

Next, tungsten is deposited using a tungsten CVD apparatus so as to fill the inside of the connection hole 79. The tungsten CVD conditions are the same as those described above. After that, an extra adhesion layer 90 on the third insulating film 78 is formed by etch back or CMP.
Then, the tungsten is removed, and an adhesion layer 80 and a tungsten plug 81 are formed inside the connection hole 89.

Next, a first insulating film is formed on the third insulating film 78.
After the lower barrier metal layer 82, the adhesion layer 83, the wiring forming layer 84, and the upper barrier metal layer 85 are formed in the same manner as the formation of the wiring 76, these films are patterned by lithography and etching. Then, a second wiring 86 connected to the tungsten plug 81 and a second compensation pattern 92 formed continuously with the second wiring 86 are formed. The film formation conditions and the etching conditions for the above films were the same as those for forming the first wiring 76.

The first, second and third insulating films 7
Each of 1, 77 and 78 is formed of a laminated film of a polyarylether film and a silicon oxide film, but may be formed of another insulating material.

In the above manufacturing method, the first wiring 76 and the second
Tungsten plug 8 which is assumed not to cause electromigration in order to connect with wiring 86 of FIG.
Since no. 1 is formed, no void is generated in the tungsten plug 81 even if a current flows through the tungsten plug 81. Also, since the first compensation pattern 91 connected to the first wiring 76 is formed and the second compensation pattern 92 connected to the second wiring 86 is formed, the tungsten plug 81 is formed by electromigration. When a void is to be generated in a portion to which is connected, copper atoms are supplied to the first wiring 76 from the first compensation pattern 91 and copper atoms are supplied to the second wiring 86 from the second compensation pattern 92. Atoms are supplied. Therefore, no void is generated in the first wiring 76 and the second wiring 86, and the connection between the tungsten plug 81 and the first wiring 76 and the second wiring 86 is reliably performed.

[0109]

As described above, according to the first semiconductor device of the present invention, which is made of copper or a copper alloy and is directly connected to the plug, compensation is made in the vicinity of the connection between the plug and the first wiring. Current pattern is formed,
Even if electromigration occurs when the current flows from the wiring to the first wiring through the plug, copper atoms are supplied to the plug from the compensation pattern. Therefore, voids in the plug, which have occurred in the conventional wiring structure, do not occur, and good connection between the first wiring and the plug is maintained. Therefore, disconnection of the wiring due to electromigration does not occur, so that the wiring reliability of the semiconductor device can be improved.

According to the second semiconductor device of the present invention, the plug is made of tungsten, made of copper or a copper alloy, and is continuously or directly connected to at least the wiring on the side where current flows out in the plug direction. Since the compensation pattern formed near the portion is provided, even if electromigration occurs when a current flows from the wiring in the plug direction, copper atoms are supplied to the wiring from the compensation pattern. Therefore, no void is generated in the wiring, which occurs in the conventional wiring structure, and good connection between the wiring and the plug is maintained. Therefore, disconnection of the wiring due to electromigration does not occur, so that the wiring reliability of the semiconductor device can be improved.

According to the second method of manufacturing a semiconductor device of the present invention, the step of forming a compensating pattern near the connection between the first wiring and the first wiring of the plug connecting the first wiring and the second wiring. And a step of forming the plug so as to be directly connected to the compensation pattern. Therefore, even if electromigration occurs when a current flows from the first wiring through the plug to the second wiring. And a structure in which copper atoms are supplied from the compensation pattern to the plug. Therefore, in the device formed by this manufacturing method, the occurrence of disconnection of the wiring due to electromigration is eliminated, and the wiring reliability is high.

According to the second method of manufacturing a semiconductor device of the present invention, the plug for connecting the interconnections is formed of tungsten which is assumed to cause no electromigration. No voids occur in the part. In addition, since a compensating pattern made of copper or a copper alloy is formed integrally with the wiring at the same time as the wiring near the connection portion with the plug, even if the electromigration tends to generate a void at the portion where the plug is connected, the wiring Can be formed so that copper atoms are supplied from the compensation pattern. Therefore, in the device formed by this manufacturing method, the occurrence of disconnection of the wiring due to electromigration is eliminated, and the wiring reliability is high.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating an embodiment according to a first semiconductor device of the present invention.

FIG. 2 is a manufacturing process diagram for explaining an embodiment according to a first method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a manufacturing process diagram for explaining an embodiment according to a first method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a schematic cross-sectional view illustrating an embodiment according to a second semiconductor device of the present invention.

FIG. 5 is an explanatory diagram of an operation of a first compensation pattern.

FIG. 6 is an explanatory diagram of an operation of a second compensation pattern.

FIG. 7 is a manufacturing process diagram for explaining an embodiment according to a second method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a manufacturing process diagram illustrating a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a schematic sectional view illustrating a conventional wiring structure.

FIG. 10 is a schematic configuration sectional view for explaining a problem.

[Explanation of symbols]

14 first wiring, 15 second insulating film, 18 compensation pattern, 19 third insulating film, 20 connection hole, 23
Second wiring, 24 ... plug

Continued on the front page F-term (reference) QQ98 RR04 RR21 SS01 SS02 SS15 SS22 TT04 XX01 XX05

Claims (7)

[Claims] A first wiring; a second copper wiring made of copper or a copper alloy; an insulating film formed between the first wiring and the second wiring; A connection hole formed in the insulating film and reaching the second wiring; and a connection hole formed of copper or a copper alloy and connecting the first wiring and the second wiring to each other. And a compensating pattern formed of copper or a copper alloy and directly connected to the plug, and formed near a connecting portion between the plug and the first wiring. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the second wiring and the plug are formed integrally, and the plug is connected to the first wiring via a barrier metal layer. 2. The semiconductor device according to 1. Forming a first wiring of a trench wiring structure on the first insulating film, and then forming a second insulating film covering the first wiring on the first insulating film; Forming a concave portion having a bottom area larger than the cross-sectional area of the plug in the second insulating film; burying copper or a copper alloy via a barrier metal layer in the concave portion to form a compensation pattern; Forming a third insulating film covering the compensation pattern on the second insulating film; forming a second wiring in the third insulating film; and forming a third wiring on the third insulating film. Forming a connection hole communicating with the compensation pattern from the bottom, and forming a barrier metal layer on the side wall of the connection hole and the inner surface of the groove, and then burying the connection hole and the groove with copper or a copper alloy; Before forming the second wiring inside the groove, The method of manufacturing a semiconductor device characterized by comprising the step of forming the plug into the connection hole. A first wiring made of copper or a copper alloy; a second copper wiring made of copper or a copper alloy; an insulating film formed between the first wiring and the second wiring. A connection hole that reaches the first wiring from the second wiring and is formed in the insulating film; and a connection hole that connects the first wiring and the second wiring and that is inside the connection hole. A semiconductor device comprising copper or a copper alloy, wherein at least a current is continuously or directly connected to the wiring on the side on which current flows out in the plug direction, and the compensation device is formed near a connection portion with the plug. A semiconductor device comprising a pattern. 5. The semiconductor device according to claim 4, wherein said plug is made of tungsten. 6. A method for manufacturing a semiconductor device, comprising a step of forming a wiring made of copper or a copper alloy to be connected to a plug, comprising: A method of manufacturing a semiconductor device, wherein the method is formed integrally with the wiring at the same time as the wiring. 7. The method according to claim 6, wherein the plug is formed of tungsten.