JPH09107011A - Semiconductor device and aligning method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an aligning method which is capable of easily judging not only whether a semiconductor device is accurately aligned with a test probe but also the extent of positional deviation (direction and distance) of the semiconductor device when it gets out of alignment. SOLUTION: A dedicated alignment pad 4 which is different from a pad 3 that serves as a usual input/output terminal or a power supply terminal is provided on at least two out of the four corners of a semiconductor device substrate 2 respectively and composed of a center pad A and peripheral pads B to E concentrically arranged surrounding the center pad A, wherein grounding resistors RA to RE are connected to the center pad A and the peripheral pads B to E respectievly, and the resistors RA to RE are set different from each other in resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output terminal and a power supply terminal of a semiconductor device with respect to a probe (probe) attached to a tester when, for example, conducting an electrical test of the semiconductor device. The present invention relates to a semiconductor device that can be easily aligned so that the pads are in good contact with each other, and a method for aligning the semiconductor device.

[0002]

2. Description of the Related Art For example, when conducting a test for confirming electrical characteristics at a wafer stage in the process of manufacturing a semiconductor device such as an LSI chip, pads for an input / output terminal and a power supply terminal provided in the semiconductor device are used. A test probe is brought into contact, and in this state, signals corresponding to various tests are supplied from the tester to the semiconductor device via the probe. Then, the semiconductor device operates according to the supplied input signal or power supply, and the output signal is captured again in the tester to determine the quality of the characteristics of the semiconductor device.

Therefore, in carrying out such a test, it is necessary to carry out alignment in advance so that the probe is in good contact with the pad of the semiconductor device.

By the way, in the prior art, while observing the semiconductor device and the probe with a microscope, the position is adjusted so that each probe is in good contact with all pads of the semiconductor device.

However, under the circumstances where the number of pins of a semiconductor device is increasing and the pitch is narrowing as in recent years,
A great deal of labor is required to visually and accurately align the probe and each pad of the semiconductor device. In particular, it has a long and narrow shape (vertical and horizontal lengths are 1:10
With a chip having a special shape such as the above, if the chip is tilted clockwise or counterclockwise, it becomes extremely difficult to perform visual alignment.

As a measure for reducing the labor required for such alignment, for example, the amount of positional deviation between the pad of the semiconductor device and the probe is extracted by image processing,
It is conceivable that the position is automatically adjusted by performing feedback control on the position shift amount.

However, in order to automate the alignment based on such image processing, it is necessary to newly install a monitor camera, a microcomputer which executes a program for image processing, and the like, resulting in a large capital investment. The cost will increase.

On the other hand, in the prior art, there is also an apparatus which can judge whether or not the probe is accurately in contact with the pad of the semiconductor device with a relatively simple structure without causing an excessive increase in cost. It has been proposed (see, for example, JP-A-1-129432).

That is, in this prior art, as shown in FIG. 7, when a semiconductor device, for example, an LSI chip is manufactured, the substrate a is separately provided from the pads b serving as the input / output terminals and power supply terminals of the chip a. Alignment pads e _{1 to} e ₄ are formed at the four corners of c, and the left and right pads e ₁ to
e ₂ , e ₃ and e ₄ are connected to each other via a wiring pattern f.

Further, a pair of alignment probes g _{1 to} g ₄ for contacting the respective alignment pads e _{1 to} e ₄ are separately provided on the probe card mounted on the tester, and a pair of left side pair of alignment probes g _{1 to} g ₄ are provided. A monitor circuit h is connected between the alignment probes g ₁ and g ₃ , and the pair of right alignment probes g ₂ and g ₄ are connected to each other by an external wiring i.

When testing various characteristics of the chip a with a tester, the resistance value between the left alignment pads e ₁ and e ₃ is measured by the monitor circuit h in advance.

[0012] Here, if the alignment of the chip a, as shown is being carried out correctly is that the alignment probe g ₁ to g ₄ is in contact with all of the alignment pad e ₁ to e ₄ Therefore, since the closed circuit is configured via the monitor circuit h, the resistance value detected by the monitor circuit h shows a small value.

On the other hand, the alignment probe g ₁
If even one of the to g ₄ are out of alignment pads e ₁ to e ₄ becomes an open state, monitor circuit h
Since the resistance value detected by means a very large value or an infinite value, it can be judged that the alignment of the chip a is defective.

[0014]

However, in the prior art shown in FIG. 7, although it is possible to judge whether the semiconductor device is accurately aligned with the tester,
When the two are misaligned, it is not possible to grasp how much the misalignment is directionally and distanceally. In other words, conventionally, it is only possible to make an alternative decision as to whether or not the alignment is good, but it is not possible to make a decision as to the extent of the misalignment in which direction and how much the distance is misaligned.

Further, even when it is attempted to determine the degree of displacement by the trace on the pad generated when the probe comes into contact with the pad, the pad having the trace of the probe because it has already been tested once is newly added this time. Since it can not be distinguished from the traces generated by the test
It is difficult to understand the degree of misalignment.

For this reason, when it is determined that the positional deviation has occurred, after all, the positional adjustment must be performed again by visual observation, and much labor is spent on the adjustment as in the conventional case.

The present invention has been made to solve the above problems, and not only can easily determine whether the semiconductor device is accurately aligned with the test probe, but also If there is a positional deviation, the degree of the positional deviation (direction and distance) can be easily recognized, so that the positioning can be performed more easily than before without further increasing the cost. The task is to do.

[0018]

The present invention adopts the following constitution in order to solve the above problems.

That is, according to the first aspect of the present invention, dedicated alignment pads are formed at least at two corners of the semiconductor device substrate separately from the pads that are used as normal input / output terminals and power supply terminals. Each alignment pad is composed of a center pad and a plurality of peripheral pads arranged concentrically around the center pad, and the center pad and the peripheral pad are respectively connected to a ground resistance, and
The ground resistances are set to have different resistance values.

According to the second aspect of the invention, the first aspect is
In the configuration described, the ground resistance connected to the center pad is set so that its resistance value is minimized.

According to a third aspect of the present invention, an alignment probe is provided corresponding to the alignment pad of the semiconductor device according to the first or second aspect, and the alignment probe is brought into contact with the semiconductor device. The semiconductor device is aligned by determining the degree of positional deviation of the semiconductor device based on the detected output of the voltage value generated at that time.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION In this embodiment, a case where an LSI chip is used as a semiconductor device will be described as an example.

FIG. 1 is a plan view of an LSI chip according to this embodiment, and FIG. 2 is an enlarged plan view of a portion indicated by reference numeral X in FIG.

This LSI chip 1 has four substrates 2
In the corner, a dedicated alignment pad 4 is formed separately from the pad 3 which is a normal input / output terminal or a power supply terminal. It should be noted that these alignment pads 4 are formed at the same time in the process of forming the pads 3 serving as the above-mentioned normal input / output terminals and power supply terminals.

When the alignment pads 4 are formed at the four corners of the substrate 2 as in this example, the LS is set as described later.
This is advantageous in that the accuracy and accuracy are increased in identifying the direction and distance of the displacement of the I-chip 1, but the present invention is not limited to this. For example, as a minimum, 2 on the diagonal of substrate 2
If the alignment pads 4 are formed in the corners, the degree of positional deviation (direction and distance) can be known.

Each of the above-mentioned alignment pads 4 has the same shape, and in this example, the center pad A and the arc-shaped outer periphery which is concentrically surrounded by the center pad A and is equally divided into four parts are arranged. It comprises pads B, C, D and E.

The diameter l ₃ of the center pad A is set to the same size as the tip diameter of the probe that comes into contact with the pad 3 that is a normal input / output terminal or power supply terminal. The distance l ₁ between the pads B to E is appropriately set to an optimum value in consideration of the distance l ₂ between the pads 3 which are normal input / output terminals and power supply terminals, depending on the target accuracy.

Further, the LSI chip 1 has ground resistors R _{A to} R _E formed on the substrate 2. These ground resistances R _{A to} R _E are manufactured in the same process when forming other circuit elements constituting the LSI chip 1, and these ground resistances R _{A to} R _E are the same as those described above. Center pad A
And peripheral pads B, C, D and E are individually connected. Moreover, the resistance values of the ground resistors R _{A to} R _E are set to be different for each pad A to _E. In particular, the resistance R _A connected to the center pad A is set so that its resistance value is minimized in order to improve the alignment accuracy.

For example, each resistor R connected to each pad
When representing the value of _A to R _E as the same reference numerals R _{A ~R E,} R
_A = 1 KΩ, R _B = 10 KΩ, R _C = 20 KΩ, R _D = 30
KΩ and R _E = 40 KΩ are set, respectively.

Next, a procedure for aligning each pad 3 of the LSI chip 1 with the probe will be described.

3 and 4 show that the probe 10,
12 shows a contact state between the LSI chip 1 and the LSI chip 1.

That is, in these drawings, (1) shows a state where the probe is displaced upward with respect to the chip, (2) shows a state where the probe is displaced downward with respect to the chip, and (3) shows a state where the probe is displaced. The probe is displaced to the left with respect to (4)
Is the state where the probe is displaced to the right with respect to the chip,
(5) is a state where the probe is shifted counterclockwise with respect to the chip, (6) is a state where the probe is displaced clockwise with respect to the chip, and (7) is a state where the probe is clockwise rotated with respect to the chip ( 6)
In each case, there is a state in which the shift is extremely different from the case.

When testing various electrical characteristics of the LSI chip 1 with a tester, in the probe card mounted on the tester, what is the probe 10 that should come into contact with the pad 3 that is a normal input / output terminal or power supply terminal? Separately, a dedicated alignment probe 12 corresponding to each alignment pad 4 is newly provided.

When the probes 10 and 12 are in contact with the LSI chip 1, the LSI chip 1 is energized from the tester through the alignment probe 12, and the voltage value generated at that time is detected by the tester. To do.

Here, for ease of explanation, the values of the resistances connected to the respective pads A to E of the respective alignment pads 4 are R _A = 1KΩ, R _B = 10KΩ, and R _C = 20K.
Ω, R _D = 30 KΩ, R _E = 40 KΩ, and
A current of 1 mA is supplied from each alignment probe 12. Note that these numerical values are merely examples, and the present invention is not limited to these.

Now, when the LSI chip 1 is accurately aligned, each alignment probe 1
2 is brought into contact with only the central pad A of each alignment pad 4, so that the alignment pad 4
_A resistance of R _A = 1 KΩ is inserted between this and ground. Therefore, when a current of 1 mA is supplied from the tester to the central pad A via the alignment probe 12, a voltage drop of 1.00 V is measured.

On the other hand, for example, as shown in FIG. 3A, when the probes 10 and 12 are slightly displaced upward with respect to the LSI chip 1, the alignment probes 12 are aligned with the alignment pads. Center pad A of 4
Not only is it also in contact with the two outer peripheral pads B and C on the upper side, but _RA between the alignment pad 4 and the ground.
= 1KΩ, R _B = 10KΩ, and R _C = 20KΩ, the same state as when three resistors are inserted in parallel. Therefore, if the value of the combined resistance is R _T , then R _T = 877Ω, and when a current of 1 mA is supplied from the tester to the alignment pad 12 via the alignment probe 12, the state (1) in FIG. As can be seen from the result of, all of the four alignment pads 4 are 0.87.
A voltage drop of 7V is measured. In other words, this voltage value (=
0.877V is the voltage value (=) when the alignment is good.
It is a small value, unlike 1.00V).

On the other hand, for example, as shown in FIG.
When the probes 10 and 12 are slightly displaced downward with respect to the SI chip 1, the respective alignment probes 1
Since 2 contacts not only the center pad A of the alignment pad 4 but also the two outer peripheral pads D and E on the lower side, R _A = 1K between the alignment pad 4 and the ground.
Ω, R _D = 30 KΩ, and R _E = 40 KΩ are in the same state as when three resistors are inserted in parallel. Therefore, the value R _T of the three combined resistances becomes R _T = 944Ω, and when a current of 1 mA is supplied from the tester to the alignment pad 14 via the alignment probe 12, the state (2) in FIG. As can be seen from the measurement results, a voltage drop of 0.944 V is measured for each of the four alignment pads 4. That is, this voltage value (= 0.944
V) is the voltage value (= 1.00V) when the alignment is good
The value is smaller than that, and is different from the measurement result (= 0.877V) in the state (1) when the value is shifted upward.

Further, as shown in FIG. 4 (5), for example, L
When the probes 10 and 12 are displaced counterclockwise with respect to the SI chip 1, the contact position of the alignment probe 12 with respect to each alignment pad 4 is set to each pad 4.
Each will be different. Therefore, when a current of 1 mA is supplied from the tester to each alignment pad 4 via each alignment probe 12, the state of FIG.
As can be seen from the measurement result of (5), with respect to the four alignment probes 4, 0.930V, 0.952V,
Voltage drops having different values such as 0.967V and 0.882V are measured for each alignment probe 4.

Further, as shown in FIG. 4 (7), since the probe is shifted clockwise relative to the chip more than in the case of FIG. 4 (6), the alignment probe 12 is completely displaced from the center pad A. If it comes off, the state of Fig. 5
As can be seen from the measurement result of (7), the voltage value becomes extremely large as compared with the measurement results of the states (1) to (6) when the both 12 and A are in contact with each other.

As described above, when the relative positions of the probes 10 and 12 are deviated from the LSI chip 1,
The measured voltage value shows a value different from the voltage value measured in a good alignment state, and the measured voltage value also differs depending on the direction of the position deviation and the degree of the position deviation. Indicates.

Therefore, in advance, (1) to FIG. 3 and FIG.
If voltage values are measured in accordance with the state of positional deviation as shown in (7), and the data of the measurement results are tabulated as shown in FIG. 5 and stored in a memory of a computer, for example, The quality of the positional deviation and the degree of the positional deviation (direction and distance) can be easily determined.

In this embodiment, the LSI chip 1 is described as an example of the semiconductor device, but the present invention is not limited to this, and the present invention can be applied to various semiconductor devices such as TCP.

The shape of the alignment pad 4 is as follows.
It is not limited to this example. For example, as shown in FIG. 6 (a), the peripheral pads B to I are concentrically arranged with respect to the central pad A, or as shown in FIG. 6 (b), the central pad is arranged. It is also possible to have a configuration in which A is a quadrangle and the outer peripheral pads B to E are concentrically arranged along with the central pad A. Also, the outer peripheral pad B
~ E and FI are not only divided into four as in this example, but also 2
It may be divided into three, or further divided into a large number. If the number of divisions is increased, it is possible to perform highly accurate alignment.

[0045]

According to the present invention, the following effects can be obtained.

(1) In the invention according to claim 1, not only is there a conventional alternative decision based only on the quality of the positional deviation, but in the case where the positional deviation occurs, in what direction and how much. It is possible to easily judge whether the distance is shifted. Moreover, since it is not necessary to introduce a high-performance device such as image processing for the determination, it is possible to perform the alignment without increasing the cost.

(2) In the invention described in claim 2, since the level difference of the detection output between the case where the position is accurately aligned and the case where it is not aligned can be increased, the alignment accuracy can be improved.

(3) In the invention according to claim 3, since the fine adjustment of the alignment can be performed while confirming the contact position of the probe, the alignment is required more than the conventional visual alignment operation. The labor can be greatly reduced.

For this reason, it is possible to easily perform alignment even for a semiconductor device having a large number of pins and a narrow pitch, and an elongated chip adopted in a liquid crystal driver or the like.

Further, even if there is a trace of the probe because the test has already been carried out once, it is not visually confused.
It becomes possible to align them.

[Brief description of the drawings]

FIG. 1 is a plan view of an LSI chip showing an embodiment of the present invention.

FIG. 2 is an enlarged plan view of a portion indicated by reference numeral X in FIG.

FIG. 3 is an explanatory diagram of a state in which each positional deviation has occurred.

FIG. 4 is an explanatory diagram of a state in which each positional deviation has occurred.

FIG. 5 is a diagram showing a result of measuring a voltage value in a state where the positional deviations shown in FIGS. 3 and 4 occur.

FIG. 6 is a plan view showing a modified example of the alignment pad.

FIG. 7 is an explanatory diagram of a conventional alignment method.

[Explanation of symbols]

1 ... LSI chip, 2 ... substrate, 3 ... pad, 4 ... alignment pad, A ... center pad, B to E ... outer peripheral pads, R _A to R _E ... ground resistance, 10 ... probe, 12 ... alignment probe.

Claims (3)

[Claims] 1. A semiconductor device substrate having at least two corners,
Dedicated alignment pads are formed separately from the pads that become the normal input / output terminals and power supply terminals. Each of these alignment pads is composed of a center pad and a plurality of concentric arrangements surrounding the center pad. The semiconductor device, wherein the central pad and the outer peripheral pad are respectively connected to a ground resistance, and the ground resistances are set to have mutually different resistance values. 2. The semiconductor device according to claim 1, wherein the ground resistance connected to the center pad is set to have a minimum resistance value. 3. An alignment probe is provided corresponding to the alignment pad of the semiconductor device according to claim 1 or 2, and the alignment probe is energized while being in contact with the semiconductor device. A method for aligning a semiconductor device, comprising: determining the degree of misalignment of the semiconductor device based on a detected output of a voltage value generated in the semiconductor device, and aligning the semiconductor device.