JPH0888324A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a field-effect transistor which restrains a short-channel effect without using a buried layer and whose gate length is short. CONSTITUTION: A field-effect transistor 2 is formed on a semiconductor substrate 1, and a coil is then manufactured by a process in which a metal is vapor- deposited two times while an insulator is sandwiched in between. A current is made to flow to the coil, and a magnetic field 7 is generated. The direction of the generated magnetic field is perpendicular to the running direction of carriers 13 inside a channel layer 11. Thereby, Lorentz's force due to the magnetic field acts on the carriers 13 inside the channel layer 11, and a force 12 acts on the side of a gate electrode opposite to the side of the semiconductor substrate at the lower part of the channel layer 11. The carriers can be run as they remain confined in the channel layer 11 by the force, and a short-channel effect is restrained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a short gate length applied in a high frequency band.

[0002]

2. Description of the Related Art In a field effect transistor, when the gate length becomes short, a short channel effect occurs in which carriers flow under the channel layer on the semiconductor substrate side. Therefore, a layer having a polarity opposite to that of the channel layer is buried under the channel layer by an ion implantation technique (for example,
Embed the p layer for the n channel layer). In this structure, an energy barrier is created at the boundary between the channel layer and the lower part, and carriers are confined in the channel layer to suppress the short channel effect (T. Shimura et al. IEEE GaAs).
IC Symposium 165, 1992).

[0003]

However, in the above-mentioned conventional ion implantation technique, there is a problem that the buried implantation ions are diffused and the buried layer reacts with the channel layer of the field effect transistor. Therefore, there are many structural parameters for obtaining the desired transistor characteristics, and the control technique is difficult, which is a problem.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device which avoids the short channel effect without using a buried ion implantation technique.

[0005]

In order to achieve this object, the semiconductor device of the present invention is manufactured by manufacturing an ordinary field effect transistor having no buried structure by an ordinary method and applying a magnetic field from the outside of the transistor. , Has a configuration in which carriers are confined in the channel layer to suppress the short channel effect.

[0006]

The magnetic field is applied perpendicular to both the traveling direction of carriers in the channel layer and the normal line direction of the semiconductor substrate surface. At that time, Lorentz force due to the magnetic field acts on the carrier, and a force in the direction of the gate electrode opposite to the semiconductor substrate side under the channel layer acts. Due to the force, carriers are confined in the channel layer and run, and the short channel effect is suppressed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

First, a semiconductor device will be described with reference to FIG. As shown in FIG. 1 (a), first, as is generally performed, a channel layer and a contact layer are manufactured by an ion implantation method, and then an electrode is vapor-deposited.
The field effect transistor 2 having a double structure is manufactured. At this time, the positional relationship between the source electrode, the gate electrode, and the drain electrode is
In the drawing, the source electrode 3, the gate electrode 4, and the drain electrode 5 are arranged in this order from the bottom.

The magnetic field generating source 6 is on the left side of the field effect transistor 2. The magnetic field 7 generated from the magnetic field generation source 6 is
As shown in the figure, carriers in the channel layer of the transistor are perpendicularly incident in the traveling direction (direction from the source electrode 5 toward the drain electrode 3).

FIGS. 2B and 2C are sectional views of the field effect transistor 2 taken along the broken line in FIG.
(B) As shown in the figure, x from right to left on the paper
The positive direction of the axis is defined as the positive direction of the y-axis, and the downward direction is defined as the positive direction of the y-axis. (B) is a case of a metal semiconductor field effect transistor, and (c) is a case of a metal oxide semiconductor field effect transistor. The magnetic field 7 emitted from the magnetic field generation source faces downward in the drawing. Since the carrier electrons 13 traveling in the channel layer have the velocity vector component 14 in the positive direction of the x-axis, the force 12 acts in the positive direction of the y-axis by the Lorentz force by the magnetic field. By this force 12, the carrier electrons 13 are confined in the channel layer, and the short channel effect is suppressed. The above cases are for the case where the channel layer is n-type and the carriers are electrons, but the same applies when the channel layer is p-type and the carriers are holes.

Next, a method of manufacturing a coil on a semiconductor substrate and a method of manufacturing a semiconductor device having a field effect transistor and a magnetic field generation source on the same semiconductor substrate will be collectively described with reference to FIG.

First, as shown in FIG. 1A, a field effect transistor 35 having a planar structure in which a channel layer is an n type without a p layer buried structure is formed on a semiconductor substrate 40 by a conventionally used method. To manufacture. The positional relationship between the source electrode 32, the gate electrode 31, and the drain electrode 30 is, as shown in the figure, from the bottom to the source gate and the drain. Next, apply photoresist to cover the transistor part,
The semiconductor substrate 40 is wet-etched. That is,
In the figure, the left side of the transistor is mesa-etched.
After the mesa etching, a coil that produces a magnetic field in the recess is manufactured. First, gold 41, which is a metal having good conductivity, is vapor-deposited by a pattern as shown in FIG. The vapor deposition of this metal is performed by a general photolithography-metal vapor deposition-lift-off method.

Next, as shown in FIG. 2 (b), an insulating film Si ₃ is formed on the entire surface.
N ₄ 50 is deposited by the plasma CVD method. The film thickness is approximately twice the height of the mesa etching portion. In addition, in the figure (b), the part covered with the Si ₃ N ₄ film and not originally visible is also shown by a broken line.

Next, as shown in FIG. 3C, a photoresist is applied by a pattern in which a window opens at the end of the comb-shaped pattern under the Si ₃ N ₄ film, and then Si ₃ Dry etching N ₄ with CF ₄ to open a window. At this time, the photoresist does not cover the FET portion on the right side of the drawing. Then, as shown in the figure, the FET portion is exposed after etching.

Next, as shown in FIG. 3D, a photoresist 51 is applied by a pattern that connects the windows opened in FIG.

Next, as shown in (e), gold 41, which is the same as the metal deposited in (a), is deposited and lifted off. In this way, the lower metal and the upper metal are connected across the Si ₃ N ₄ film,
A single coil is manufactured. Through the above steps, a semiconductor device having a magnetic field generation source (coil) and a field effect transistor on the same semiconductor substrate is manufactured.

Of the above steps, the steps excluding the step involving the field effect transistor are the method for manufacturing the coil on the semiconductor substrate.

A view of only the manufactured coil portion is shown in FIG. In this figure, the field effect transistor is on the other side of the coil. When generating a magnetic field, a current 60 is passed from the front side of the paper to the other side. The generated magnetic field 61 is in the direction opposite to the plane of the coil, and is perpendicular to the traveling direction of carriers in the channel layer of the field effect transistor. In addition,
Although the above figure shows the case where the number of turns of the coil is 5, the number of turns need not necessarily be 5. Even when the number of turns is not 5, the manufacturing method is the same as above.

[0019]

By the magnetic field generated from the magnetic field generation source,
Lorentz force acts on the carrier of the field effect transistor, and the carrier can travel while being confined in the channel layer, and the short channel effect is suppressed.

Also, in this semiconductor device, unlike the suppression of the short channel effect by the buried layer, the force applied to the carriers can be changed by changing the current flowing in the coil, and the short channel effect is suppressed. There is also an advantage that the degree can be changed after the transistor is manufactured.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a field effect transistor provided with a magnetic field generation source on the same semiconductor substrate.

FIG. 2 is a process diagram showing a method for manufacturing a field effect transistor having a magnetic field generation source on the same semiconductor substrate.

[Explanation of symbols]

1 semiconductor substrate 2 field effect transistor 3 drain electrode 4 gate electrode 5 source electrode 6 magnetic field source 7 generated magnetic field 10 contact layer 11 channel layer 12 y-direction component of Lorentz force by magnetic field 13 carrier electron 14 of carrier X direction component of velocity vector 30 drain electrode 31 gate electrode 32 source electrode 35 field effect transistor (FET) 40 semiconductor substrate 41 gold 42 photoresist 50 Si ₃ N ₄ 60 current 61 generated magnetic field

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/812 21/338 9171-4M H01L 29/80 R

Claims (6)

[Claims] 1. A semiconductor substrate, a field effect transistor provided on the semiconductor substrate, and a magnetic field generation source provided on the semiconductor substrate, wherein the magnetic field generated from the magnetic field generation source is the field effect. The carriers in the channel layer of the transistor are incident in a direction perpendicular to both the traveling direction (direction from the source region to the drain region) and the direction normal to the semiconductor substrate surface, and the carriers in the channel layer are exposed to the magnetic field. The carrier force is confined in the channel layer by the force acting in the direction toward the interface between the channel layer and the gate electrode due to the Lenz force.
A semiconductor device in which the to-channel effect is suppressed. 2. The semiconductor device according to claim 1, further comprising a coil on the semiconductor substrate, and a magnetic field generation source that generates a magnetic field when a current flows through the coil. 3. A method of manufacturing a coil on a semiconductor substrate, comprising: comb-depositing a metal having good conductivity on a semiconductor substrate; depositing an insulator on the entire surface of the semiconductor substrate and the metal. A coil whose winding direction (the central axis of the coil) is perpendicular to the normal to the semiconductor substrate surface is formed by etching the insulator to open a window and further depositing the metal in a comb shape. A method for manufacturing a coil, which comprises manufacturing the coil. 4. The method for manufacturing a coil according to claim 3, wherein the metal having good conductivity is gold. 5. The method for manufacturing a coil on a semiconductor substrate according to claim 3, wherein the insulator is manufactured by depositing Si ₃ N ₄ by a plasma CVD method. 6. A method of manufacturing a semiconductor device, the method comprising: manufacturing a field effect transistor on a semiconductor substrate; performing mesa etching so that the field effect transistor has a convex portion on the semiconductor substrate; A method of manufacturing a semiconductor device, comprising the step of manufacturing a coil on the semiconductor substrate according to claim 3 in the recess.