JPH0883782A - Method for manufacturing compound semiconductor device - Google Patents
Method for manufacturing compound semiconductor deviceInfo
- Publication number
- JPH0883782A JPH0883782A JP21510594A JP21510594A JPH0883782A JP H0883782 A JPH0883782 A JP H0883782A JP 21510594 A JP21510594 A JP 21510594A JP 21510594 A JP21510594 A JP 21510594A JP H0883782 A JPH0883782 A JP H0883782A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- semiconductor substrate
- oxide film
- resist
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 150000001875 compounds Chemical class 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000005530 etching Methods 0.000 claims abstract description 24
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 15
- -1 gallium arsenide compound Chemical class 0.000 abstract description 15
- 238000001035 drying Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- IKWTVSLWAPBBKU-UHFFFAOYSA-N a1010_sial Chemical compound O=[As]O[As]=O IKWTVSLWAPBBKU-UHFFFAOYSA-N 0.000 abstract description 3
- 229910000413 arsenic oxide Inorganic materials 0.000 abstract description 3
- 229960002594 arsenic trioxide Drugs 0.000 abstract description 3
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 abstract description 3
- 229910001195 gallium oxide Inorganic materials 0.000 abstract description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 238000007654 immersion Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005211 surface analysis Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Weting (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
(57)【要約】
【目的】レジスト残渣や表面の汚れの除去にドライプロ
セスを用いないで清浄な化合物半導体基板表面を得るこ
とができる化合物半導体装置の製造方法を提供すること
にある。
【構成】ガリウム砒素化合物半導体基板1の表面に酸化
処理を行って酸化ガリウムおよび酸化砒素を含む表面酸
化膜2を形成し、表面酸化膜2上に所望のレジストパタ
ーン3を形成する。そして、表面酸化膜2におけるレジ
ストパターン3で覆われていない露出部分をフッ化水素
酸によるウェットエッチングで除去する。このとき、レ
ジスト残渣や表面の汚れが同時に除去され、清浄な化合
物半導体基板表面が露出する。そして、清浄な化合物半
導体基板1の表面にエッチングや電極形成を行う。
(57) [Summary] [Object] To provide a method for manufacturing a compound semiconductor device capable of obtaining a clean compound semiconductor substrate surface without using a dry process for removing resist residues and surface stains. A surface oxide film 2 containing gallium oxide and arsenic oxide is formed by oxidizing the surface of a gallium arsenide compound semiconductor substrate 1, and a desired resist pattern 3 is formed on the surface oxide film 2. Then, the exposed portion of the surface oxide film 2 which is not covered with the resist pattern 3 is removed by wet etching with hydrofluoric acid. At this time, the resist residue and surface stains are simultaneously removed, and the clean compound semiconductor substrate surface is exposed. Then, etching and electrode formation are performed on the surface of the clean compound semiconductor substrate 1.
Description
【0001】[0001]
【産業上の利用分野】本発明は、化合物半導体装置の製
造方法であって、詳しくは、エッチングや電極形成等の
加工を行う時に問題となるレジスト残渣や表面の汚れを
除去し、清浄な化合物半導体基板表面を得る方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a compound semiconductor device, and more specifically, it removes resist residues and surface stains, which are problems during processing such as etching and electrode formation, and is a clean compound. The present invention relates to a method for obtaining a semiconductor substrate surface.
【0002】[0002]
【従来の技術】化合物半導体装置は高い周波数で動作さ
せるために、微細なリセス形状を必要とするほか、電極
の接触抵抗も低いことが要求される。一方、化合物半導
体装置の製造においては、電気的特性の低下を避けるた
めにドライプロセスを使わないことが望ましい。しか
し、レジスト除去後のドライプロセスを用いずに有機洗
浄のみを用いると、化合物半導体基板表面にレジストが
変質したレジスト残渣や汚れが付着しやすい。このよう
な表面にレジスト残渣や汚れがある化合物半導体基板表
面に、ウェットエッチングで極微細なリセス加工を行う
とエッチング深さやサイドエッチングのばらつきが大き
くなるといった不具合が生じる。又、電極を形成する場
合にも、レジスト残渣や汚れが原因で接触抵抗が大きく
なったり、電極が剥がれるといった不具合が生じる。2. Description of the Related Art A compound semiconductor device is required to have a fine recess shape in order to operate at a high frequency and also to have a low contact resistance of electrodes. On the other hand, in manufacturing a compound semiconductor device, it is desirable not to use a dry process in order to avoid deterioration of electrical characteristics. However, if only the organic cleaning is used without using the dry process after removing the resist, the resist residues and stains, which are resist-altered, are easily attached to the surface of the compound semiconductor substrate. When a compound semiconductor substrate surface having resist residues or stains on such a surface is subjected to extremely fine recess processing by wet etching, there arises a problem that variations in etching depth and side etching become large. In addition, when the electrodes are formed, problems such as an increase in contact resistance and peeling of the electrodes may occur due to resist residues and stains.
【0003】一方、シリコン半導体装置の製造ではプラ
ズマアッシングやプラズマエッチングといったドライプ
ロセスが用いられてきた。この時のレジスト残渣の除去
方法が、特開平4−82221号公報にて提案されてい
る。この方法は、塩素系ガスプラズマ反応を用いたエッ
チング処理でアルミ合金配線パターンを形成する際に発
生するレジスト残渣を、予め形成しておいた下地の犠牲
膜と同時にフッ素系ガスプラズマ反応で除去するという
ものである。On the other hand, dry processes such as plasma ashing and plasma etching have been used in the manufacture of silicon semiconductor devices. A method for removing the resist residue at this time is proposed in Japanese Patent Laid-Open No. 4-82221. This method removes the resist residue generated when the aluminum alloy wiring pattern is formed by the etching process using the chlorine-based gas plasma reaction by the fluorine-based gas plasma reaction at the same time as the previously formed underlying sacrificial film. That is.
【0004】[0004]
【発明が解決しようとする課題】しかし、この技術を上
述するような化合物半導体装置の製造におけるリセス加
工や電極形成に適用した場合、プラズマ反応にさらされ
た化合物半導体基板表面がそのまま用いられるため、作
製された化合物半導体装置はショットキ特性等の電気的
特性が低いという問題があった。However, when this technique is applied to recess processing and electrode formation in the production of the compound semiconductor device as described above, the surface of the compound semiconductor substrate exposed to the plasma reaction is used as it is, The produced compound semiconductor device has a problem that electrical characteristics such as Schottky characteristics are low.
【0005】そこで、この発明の目的は、レジスト残渣
や表面の汚れの除去にドライプロセスを用いないで清浄
な化合物半導体基板表面を得ることができる化合物半導
体装置の製造方法を提供することにある。Therefore, an object of the present invention is to provide a method for manufacturing a compound semiconductor device which can obtain a clean compound semiconductor substrate surface without using a dry process for removing resist residues and surface stains.
【0006】[0006]
【課題を解決するための手段】請求項1に記載の発明
は、少なくともガリウムまたは砒素を含む化合物半導体
基板の表面に酸化処理を行って表面酸化膜を形成する第
1工程と、前記表面酸化膜上に所望のレジストパターン
を形成する第2工程と、前記表面酸化膜におけるレジス
トパターンで覆われていない露出部分をウェットエッチ
ングで除去することによりレジスト残渣や表面の汚れを
同時に除去し、清浄な化合物半導体基板表面を露出させ
る第3工程と、前記清浄な化合物半導体基板表面にエッ
チングや電極形成を行う第4工程とを備えた化合物半導
体装置の製造方法をその要旨とする。According to a first aspect of the present invention, there is provided a first step of forming a surface oxide film by oxidizing a surface of a compound semiconductor substrate containing at least gallium or arsenic, and the surface oxide film. A second step of forming a desired resist pattern on the upper surface, and a wet compound for removing exposed portions of the surface oxide film that are not covered with the resist pattern by wet etching to simultaneously remove resist residues and surface stains, and to obtain a clean compound. The gist is a method of manufacturing a compound semiconductor device including a third step of exposing the surface of a semiconductor substrate and a fourth step of etching or forming electrodes on the surface of the clean compound semiconductor substrate.
【0007】請求項2に記載の発明は、請求項1に記載
の化合物半導体装置の製造方法において、第2工程での
レジストパターンとして異なるレジストパターンを用い
て第2工程から第4工程を繰り返し行う化合物半導体装
置の製造方法をその要旨とする。According to a second aspect of the present invention, in the method for manufacturing a compound semiconductor device according to the first aspect, the second to fourth steps are repeated using different resist patterns as the resist pattern in the second step. The gist of the invention is a method of manufacturing a compound semiconductor device.
【0008】請求項3に記載の発明は、請求項1に記載
の化合物半導体装置の製造方法において、第3工程での
ウェットエッチング液はフッ化水素酸である化合物半導
体装置の製造方法をその要旨とする。The invention according to claim 3 is the method for manufacturing a compound semiconductor device according to claim 1, wherein the wet etching solution in the third step is hydrofluoric acid. And
【0009】[0009]
【作用】請求項1に記載の発明によれば、第1工程によ
り少なくともガリウムまたは砒素を含む化合物半導体基
板の表面に酸化処理が行われて表面酸化膜が形成され、
第2工程により表面酸化膜上に所望のレジストパターン
が形成される。そして、第3工程により表面酸化膜にお
けるレジストパターンで覆われていない露出部分をウェ
ットエッチングで除去することによりレジスト残渣や表
面の汚れが同時に除去されて清浄な化合物半導体基板表
面が露出される。つまり、この第3工程において、少な
くともガリウムまたは砒素を含む化合物半導体基板の酸
化膜はエッチング液に溶解されやすく、エッチングによ
る化合物半導体基板の酸化膜の溶解とともにレジスト残
渣や表面の汚れが除去され、清浄な化合物半導体基板表
面が得られる。According to the invention of claim 1, in the first step, the surface of the compound semiconductor substrate containing at least gallium or arsenic is oxidized to form a surface oxide film.
By the second step, a desired resist pattern is formed on the surface oxide film. Then, in the third step, the exposed portion of the surface oxide film which is not covered with the resist pattern is removed by wet etching, whereby the resist residue and the surface dirt are removed at the same time to expose the clean compound semiconductor substrate surface. In other words, in the third step, the oxide film of the compound semiconductor substrate containing at least gallium or arsenic is easily dissolved in the etching solution, and the resist residue and surface stains are removed as the oxide film of the compound semiconductor substrate is dissolved by etching. A compound semiconductor substrate surface is obtained.
【0010】さらに、第4工程により清浄な化合物半導
体基板表面にエッチングや電極形成が行われる。請求項
2に記載の発明によれば、請求項1に記載の発明の作用
に加え、第2工程でのレジストパターンとして異なるレ
ジストパターンを用いて第2工程から第4工程が繰り返
し行われる。つまり、表面酸化膜を形成後、異なるレジ
ストパターンを用いて表面酸化膜を除去する工程と、エ
ッチングや電極形成する工程が順次繰り返して行われ
る。その結果、前のレジストパターン形成工程で生じた
レジスト残渣や表面の汚れに影響を受けることなく必要
なときに清浄な化合物半導体基板表面が露出される。Further, in the fourth step, etching and electrode formation are performed on the surface of the clean compound semiconductor substrate. According to the second aspect of the invention, in addition to the effect of the first aspect of the invention, the second to fourth steps are repeated using different resist patterns as the resist pattern in the second step. That is, after forming the surface oxide film, the step of removing the surface oxide film by using a different resist pattern and the step of etching and forming electrodes are sequentially repeated. As a result, a clean compound semiconductor substrate surface is exposed when necessary without being affected by the resist residue and surface contamination generated in the previous resist pattern forming step.
【0011】請求項3に記載の発明によれば、請求項1
に記載の発明の作用に加え、第3工程においてフッ化水
素酸にて表面酸化膜がウェットエッチングされる。According to the invention of claim 3, claim 1
In addition to the effect of the invention described in (1), the surface oxide film is wet-etched with hydrofluoric acid in the third step.
【0012】[0012]
(第1実施例)以下、この発明を具体化した第1実施例
を図面に従って説明する。(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.
【0013】本実施例は、ガリウム砒素化合物半導体基
板をリセスエッチングするものであり、図1〜図5に製
造工程を示す。又、各工程においてXPSを用いた化合
物半導体基板表面の酸素と炭素のピーク面積をまとめた
結果を図6に示す。In this embodiment, a gallium arsenide compound semiconductor substrate is recess-etched, and the manufacturing process is shown in FIGS. Further, FIG. 6 shows the results of summarizing the peak areas of oxygen and carbon on the surface of the compound semiconductor substrate using XPS in each step.
【0014】まず、図1に示すように、リセスエッチン
グを施そうとするガリウム砒素化合物半導体基板1を用
意する。そして、図2に示すように、ガリウム砒素化合
物半導体基板1の表面に酸化処理を行って酸化ガリウム
および酸化砒素を含んだ表面酸化膜2を形成する。この
表面酸化膜処理は、ガリウム砒素化合物半導体基板1を
80℃、18%過酸化水素水200ミリリットル中に5
分間浸漬して行う。このとき形成された表面酸化膜2を
オージェ電子分光法を用いて分析したところ、表面酸化
膜2の厚さはおよそ35Åであった。First, as shown in FIG. 1, a gallium arsenide compound semiconductor substrate 1 to be subjected to recess etching is prepared. Then, as shown in FIG. 2, the surface of the gallium arsenide compound semiconductor substrate 1 is oxidized to form a surface oxide film 2 containing gallium oxide and arsenic oxide. This surface oxide film treatment is carried out by treating the gallium arsenide compound semiconductor substrate 1 with 5% in 200 ml of 18% hydrogen peroxide solution at 80 ° C.
Soak for a minute. When the surface oxide film 2 formed at this time was analyzed by Auger electron spectroscopy, the thickness of the surface oxide film 2 was about 35Å.
【0015】次に、図3に示すように、表面酸化膜2上
にポジレジストを1.4μmの厚さに塗布し、ブリベー
クを100℃で120秒間行い、マスクを用いて露光し
たのち現像し、所望のレジストパターン3を形成する。
このとき現像された部分、即ち、表面酸化膜2における
レジストパターン3で覆われていない露出部分(レジス
トパターン3の開口部4)には、現像残りであるレジス
ト残渣や表面の汚れ5が生成される。Next, as shown in FIG. 3, a positive resist is applied on the surface oxide film 2 to a thickness of 1.4 μm, and a bribake is carried out at 100 ° C. for 120 seconds. The film is exposed using a mask and then developed. Then, a desired resist pattern 3 is formed.
At this time, in the developed portion, that is, in the exposed portion of the surface oxide film 2 which is not covered with the resist pattern 3 (opening 4 of the resist pattern 3), a resist residue which is a development residue and a surface stain 5 are generated. It
【0016】以上に述べたガリウム砒素化合物半導体基
板表面の変化は、図6に示すXPSによる表面分析から
明らかである。即ち、図1の状態から図2に示すよう
に、酸化処理を行うことにより酸素ピーク面積が基板初
期から大きく増加しており、ガリウム砒素化合物半導体
基板表面に酸化膜が形成されたことが示されている。
又、図3に示したように、レジストパターン3を形成す
る工程後に炭素のピーク面積が増加しており、レジスト
残渣や表面の汚れ5が生じたことを示している。The change in the surface of the gallium arsenide compound semiconductor substrate described above is apparent from the surface analysis by XPS shown in FIG. That is, as shown in FIG. 2 from the state of FIG. 1, the oxygen peak area was greatly increased from the initial stage of the substrate by performing the oxidation treatment, and it was shown that an oxide film was formed on the surface of the gallium arsenide compound semiconductor substrate. ing.
Further, as shown in FIG. 3, the peak area of carbon increases after the step of forming the resist pattern 3, which indicates that resist residues and surface stains 5 have occurred.
【0017】続いて、レジストパターン3を形成したガ
リウム砒素化合物半導体基板1を、5%フッ化水素酸中
に5分間浸漬する。その結果、図4に示すように、レジ
ストパターン3の開口部4(表面酸化膜2の露出部)に
おける表面酸化膜2が除去される。この工程後のXPS
分析結果は、図6に示されるように、酸素ピーク面積も
炭素ピーク面積も共に減少しており、化合物半導体基板
1をフッ化水素酸中へ浸漬することにより、表面酸化膜
2が溶解するとともにレジスト残渣や表面の汚れ5も除
去されたことを示している。Subsequently, the gallium arsenide compound semiconductor substrate 1 having the resist pattern 3 formed thereon is immersed in 5% hydrofluoric acid for 5 minutes. As a result, as shown in FIG. 4, the surface oxide film 2 in the opening 4 (exposed portion of the surface oxide film 2) of the resist pattern 3 is removed. XPS after this process
As shown in FIG. 6, the analysis result shows that both the oxygen peak area and the carbon peak area decrease, and the surface oxide film 2 is dissolved while the compound semiconductor substrate 1 is immersed in hydrofluoric acid. This indicates that the resist residue and the surface stain 5 are also removed.
【0018】このようにして清浄な化合物半導体基板表
面が得られる。この清浄な化合物半導体基板表面に対
し、図5に示すように、リセスエッチングを行い所望の
エッチング形状を得る。このように、清浄な化合物半導
体基板表面を用いてエッチング形状を安定して作製でき
る。In this way, a clean compound semiconductor substrate surface is obtained. As shown in FIG. 5, recess etching is performed on the clean surface of the compound semiconductor substrate to obtain a desired etching shape. In this way, the etching shape can be stably produced using a clean compound semiconductor substrate surface.
【0019】このように本実施例では、ガリウム砒素化
合物半導体基板1の表面に酸化処理を行って表面酸化膜
2を形成し(第1工程)、表面酸化膜2上に所望のレジ
ストパターン3を形成し(第2工程)、表面酸化膜2に
おけるレジストパターン3で覆われていない露出部分を
ウェットエッチングで除去することによりレジスト残渣
や表面の汚れ5を同時に除去し、清浄な化合物半導体基
板表面を露出させ(第3工程)、清浄な化合物半導体基
板表面にエッチングを行うようにした(第4工程)。As described above, in this embodiment, the surface of the gallium arsenide compound semiconductor substrate 1 is oxidized to form the surface oxide film 2 (first step), and the desired resist pattern 3 is formed on the surface oxide film 2. After forming (second step), the exposed portion of the surface oxide film 2 which is not covered with the resist pattern 3 is removed by wet etching to simultaneously remove the resist residue and surface stains 5, thereby forming a clean compound semiconductor substrate surface. It was exposed (third step) and the clean compound semiconductor substrate surface was etched (fourth step).
【0020】このように、エッチング工程においてドラ
イプロセスを用いずに清浄な化合物半導体基板表面が得
られ、エッチング深さやサイドエッチングのばらつきを
低減でき、安定した化合物半導体装置の製造が可能とな
る。As described above, a clean compound semiconductor substrate surface can be obtained without using a dry process in the etching step, variations in etching depth and side etching can be reduced, and a stable compound semiconductor device can be manufactured.
【0021】又、フッ化水素酸にて表面酸化膜2をウェ
ットエッチングしたので、表面酸化膜2を確実にウェッ
トエッチングすることができる。尚、上記実施例では、
ガリウム砒素化合物半導体基板を用いた場合について説
明したが、インジウムガリウム砒素,インジウムアルミ
ニウム砒素やアルミニウムガリウム砒素など少なくとも
ガリウムまたは砒素を含む二元系,三元系や四元系化合
物半導体基板に適用が可能である。ただし、ここにいう
化合物半導体基板とは図1に示すような単一の基板に限
らず、表面に電極形成やエッチング等の加工を施してあ
ったり、ガリウム又は砒素を含み組成の異なる複数の膜
が積層されたものも含む。又、上記実施例では、化合物
半導体基板表面の酸化処理には加熱した過酸化水素水中
への浸漬を行ったが、その他、常温の過酸化水素水への
浸漬や、常温及び加熱した水への浸漬、さらに、表面酸
化膜は後に除去されるのでプラズマ酸化法や熱酸化法、
陽極酸化法の利用等種々の方法が考えられる。Since the surface oxide film 2 is wet-etched with hydrofluoric acid, the surface oxide film 2 can be surely wet-etched. In the above embodiment,
The case of using a gallium arsenide compound semiconductor substrate has been described, but it can be applied to a binary, ternary or quaternary compound semiconductor substrate containing at least gallium or arsenic such as indium gallium arsenide, indium aluminum arsenide and aluminum gallium arsenide. Is. However, the compound semiconductor substrate referred to here is not limited to a single substrate as shown in FIG. 1, but a plurality of films having different compositions including gallium or arsenic, which have been subjected to processing such as electrode formation or etching on the surface. Also includes those in which are laminated. Further, in the above example, the oxidation treatment of the surface of the compound semiconductor substrate was carried out by immersion in heated hydrogen peroxide water, but in addition, immersion in room temperature hydrogen peroxide water or room temperature and heated water was carried out. Immersion, and since the surface oxide film is removed later, plasma oxidation method or thermal oxidation method,
Various methods are conceivable, such as utilizing the anodizing method.
【0022】又、上記実施例では第4工程として清浄な
化合物半導体基板表面にエッチングを行う場合について
説明したが、清浄な化合物半導体基板表面に電極形成を
行う場合に適用してもよい。この際、電極形成工程にお
いてドライプロセスを用いずに清浄な化合物半導体基板
表面が得られ、電極の接触不良を低減でき、安定した化
合物半導体装置の製造が可能となる。 (第2実施例)次に、第2実施例を第1実施例との相違
点を中心に説明する。Further, in the above embodiment, the case where the clean compound semiconductor substrate surface is etched as the fourth step has been described, but it may be applied when the electrode is formed on the clean compound semiconductor substrate surface. At this time, a clean compound semiconductor substrate surface can be obtained without using a dry process in the electrode formation step, contact failure of the electrodes can be reduced, and a stable compound semiconductor device can be manufactured. (Second Embodiment) Next, the second embodiment will be described focusing on the differences from the first embodiment.
【0023】本実施例では、ガリウム砒素化合物半導体
基板表面にオーミック電極を形成する工程とリセスエッ
チングを行う(およびショットキ電極を形成する)工程
を含む場合について、図7〜図14を用いて説明する。In this embodiment, a case including a step of forming an ohmic electrode on the surface of a gallium arsenide compound semiconductor substrate and a step of performing recess etching (and forming a Schottky electrode) will be described with reference to FIGS. 7 to 14. .
【0024】まず、図7に示すように、第1実施例と同
じ表面酸化処理条件を用いてガリウム砒素化合物半導体
基板1の表面に酸化ガリウムおよび酸化砒素を含んだ表
面酸化膜2を形成する。First, as shown in FIG. 7, the surface oxide film 2 containing gallium oxide and arsenic oxide is formed on the surface of the gallium arsenide compound semiconductor substrate 1 under the same surface oxidation treatment conditions as in the first embodiment.
【0025】次に、図8に示すように、第1実施例と同
様にオーミック電極のためのレジストパターン3を形成
する。このとき、レジストパターン3の開口部4には、
現像残りであるレジスト残渣や表面の汚れ5aが生成さ
れる。そして、図9に示すように、化合物半導体基板1
をフッ化水素酸に浸漬してレジストパターン3の開口部
4における表面酸化膜2を除去する。このとき、現像残
りであるレジスト残渣や表面の汚れ5aも同時に除去さ
れ、清浄なガリウム砒素化合物半導体基板表面が露出す
る。続いて、図10に示すように、ガリウム砒素化合物
半導体基板1の表面に、金−ゲルマニウム/ニッケル/
金を蒸着し、リフトオフを行った後、合金化処理してオ
ーミック電極6を形成する。Next, as shown in FIG. 8, a resist pattern 3 for an ohmic electrode is formed as in the first embodiment. At this time, in the opening 4 of the resist pattern 3,
Resist residues that are undeveloped and surface stains 5a are generated. Then, as shown in FIG. 9, the compound semiconductor substrate 1
Is immersed in hydrofluoric acid to remove the surface oxide film 2 in the opening 4 of the resist pattern 3. At this time, the resist residue that is the undeveloped residue and the surface stain 5a are also removed at the same time, and the clean gallium arsenide compound semiconductor substrate surface is exposed. Then, as shown in FIG. 10, gold-germanium / nickel /
After vapor deposition of gold and lift-off, alloying treatment is performed to form the ohmic electrode 6.
【0026】さらに、図11に示すように、リセスエッ
チングのためのレジストパターン7を第1実施例と同様
に形成する。このとき、レジストパターン7の開口部8
には、現像残りであるレジスト残渣や表面の汚れ5bが
生成される。そして、図12に示すように、化合物半導
体基板1をフッ化水素酸に浸漬してレジストパターン7
の開口部8での表面酸化膜2を除去する。このとき、現
像残りであるレジスト残渣や表面の汚れ5bも同時に除
去され、清浄なガリウム砒素化合物半導体基板表面が露
出する。Further, as shown in FIG. 11, a resist pattern 7 for recess etching is formed similarly to the first embodiment. At this time, the opening 8 of the resist pattern 7
On the other hand, a resist residue which is a development residue and a surface stain 5b are generated. Then, as shown in FIG. 12, the compound semiconductor substrate 1 is immersed in hydrofluoric acid to form a resist pattern 7.
The surface oxide film 2 in the opening 8 is removed. At this time, the resist residue that is the undeveloped residue and the surface contamination 5b are also removed at the same time, and the clean gallium arsenide compound semiconductor substrate surface is exposed.
【0027】引き続き、図13に示すように、化合物半
導体基板1の表面にエッチング処理を行い、リセス形状
を得たのち、図14に示すように、チタン/白金/金を
蒸着してリフトオフでショットキ電極9を形成する。Subsequently, as shown in FIG. 13, the surface of the compound semiconductor substrate 1 is subjected to etching treatment to obtain a recess shape, and then titanium / platinum / gold is vapor-deposited and lift-off is applied to the Schottky as shown in FIG. The electrode 9 is formed.
【0028】このように本実施例では、レジストパター
ンとして異なるレジストパターン3,7を用いて第2工
程から第4工程を繰り返し行うようにした。つまり、全
工程に先んじて表面酸化膜2を形成し、異なるレジスト
パターンを形成する工程と、表面酸化膜2を除去する工
程と、エッチングまたは電極を形成する工程とを順次繰
り返して行った。よって、前のレジストパターン形成工
程で生じたレジスト残渣や表面汚れに影響を受けること
なく必要なときに常に清浄な化合物半導体基板表面を得
ることができる。このように、最初に表面酸化膜2を形
成しておくだけで、必要なときに必要な位置に酸処理を
施すだけで清浄な化合物半導体基板表面を得ることがで
きる。As described above, in this embodiment, the second to fourth steps are repeated by using different resist patterns 3 and 7 as the resist patterns. That is, the step of forming the surface oxide film 2 and forming a different resist pattern prior to all the steps, the step of removing the surface oxide film 2, and the step of etching or forming electrodes were sequentially repeated. Therefore, it is possible to always obtain a clean compound semiconductor substrate surface without being affected by the resist residue and surface stains generated in the previous resist pattern forming step. In this way, by simply forming the surface oxide film 2 first, a clean compound semiconductor substrate surface can be obtained by performing acid treatment at a necessary position when necessary.
【0029】尚、この発明は上記各実施例に限定される
ものではなく、例えば、表面酸化膜2の除去のためのエ
ッチング液としてフッ化水素酸の代わりに希硫酸や酢
酸,クエン酸,アンモニアを用いてもよい。The present invention is not limited to the above-mentioned embodiments. For example, instead of hydrofluoric acid as an etching solution for removing the surface oxide film 2, dilute sulfuric acid, acetic acid, citric acid, or ammonia is used. May be used.
【0030】[0030]
【発明の効果】以上詳述したように請求項1に記載の発
明によれば、レジスト残渣や表面の汚れの除去にドライ
プロセスを用いないで清浄な化合物半導体基板表面を得
ることができる優れた効果を発揮する。As described in detail above, according to the invention described in claim 1, it is possible to obtain a clean compound semiconductor substrate surface without using a dry process for removing resist residues and surface stains. Be effective.
【0031】請求項2に記載の発明によれば、請求項1
に記載の発明の効果に加え、前のレジストパターン形成
工程で生じたレジスト残渣や表面の汚れに影響を受ける
ことなく必要なときに清浄な化合物半導体基板表面を露
出することができる。According to the invention described in claim 2, claim 1
In addition to the effect of the invention described in (1), a clean compound semiconductor substrate surface can be exposed when necessary without being affected by the resist residue and surface stains generated in the previous resist pattern forming step.
【0032】請求項3に記載の発明によれば、請求項1
に記載の発明の効果に加え、表面酸化膜を確実にウェッ
トエッチングすることができる。According to the invention of claim 3, claim 1
In addition to the effect of the invention described in (1), the surface oxide film can be surely wet-etched.
【図1】第1実施例の化合物半導体装置の製造工程を示
す断面図である。FIG. 1 is a cross-sectional view showing a manufacturing process of a compound semiconductor device of a first embodiment.
【図2】第1実施例の化合物半導体装置の製造工程を示
す断面図である。FIG. 2 is a cross-sectional view showing a manufacturing process of the compound semiconductor device of the first embodiment.
【図3】第1実施例の化合物半導体装置の製造工程を示
す断面図である。FIG. 3 is a cross-sectional view showing a manufacturing process of the compound semiconductor device of the first example.
【図4】第1実施例の化合物半導体装置の製造工程を示
す断面図である。FIG. 4 is a cross-sectional view showing a manufacturing process of the compound semiconductor device of the first example.
【図5】第1実施例の化合物半導体装置の製造工程を示
す断面図である。FIG. 5 is a cross-sectional view showing the manufacturing process of the compound semiconductor device of the first example.
【図6】第1実施例における各工程ごとにXPSで表面
分析を行い、酸素と炭素のピーク面積についてまとめた
結果を示す図である。FIG. 6 is a diagram showing a result obtained by performing surface analysis by XPS for each step in the first example and summarizing peak areas of oxygen and carbon.
【図7】第2実施例の化合物半導体装置の製造工程を示
す断面図である。FIG. 7 is a cross-sectional view showing a manufacturing process of the compound semiconductor device of the second embodiment.
【図8】第2実施例の化合物半導体装置の製造工程を示
す断面図である。FIG. 8 is a cross-sectional view showing the manufacturing process of the compound semiconductor device of the second embodiment.
【図9】第2実施例の化合物半導体装置の製造工程を示
す断面図である。FIG. 9 is a cross-sectional view showing the manufacturing process of the compound semiconductor device of the second example.
【図10】第2実施例の化合物半導体装置の製造工程を
示す断面図である。FIG. 10 is a cross-sectional view showing a manufacturing process of the compound semiconductor device of the second embodiment.
【図11】第2実施例の化合物半導体装置の製造工程を
示す断面図である。FIG. 11 is a cross-sectional view showing the manufacturing process of the compound semiconductor device of the second example.
【図12】第2実施例の化合物半導体装置の製造工程を
示す断面図である。FIG. 12 is a cross-sectional view showing the manufacturing process of the compound semiconductor device of the second example.
【図13】第2実施例の化合物半導体装置の製造工程を
示す断面図である。FIG. 13 is a cross-sectional view showing the manufacturing process of the compound semiconductor device of the second embodiment.
【図14】第2実施例の化合物半導体装置の製造工程を
示す断面図である。FIG. 14 is a cross-sectional view showing the manufacturing process of the compound semiconductor device of the second example.
【符号の説明】 1…ガリウム砒素化合物半導体基板、2…表面酸化膜、
3…レジストパターン、4…開口部、5…レジスト残渣
や表面の汚れ、6…オーミック電極、7…レジストパタ
ーン、8…開口部、9…ショットキ電極[Explanation of reference numerals] 1 ... Gallium arsenide compound semiconductor substrate, 2 ... Surface oxide film,
3 ... Resist pattern, 4 ... Aperture, 5 ... Resist residue and surface stain, 6 ... Ohmic electrode, 7 ... Resist pattern, 8 ... Aperture, 9 ... Schottky electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 水谷 道代 愛知県刈谷市昭和町1丁目1番地 日本電 装 株式会社内 (72)発明者 外山 哲男 愛知県刈谷市昭和町1丁目1番地 日本電 装 株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Michiyo Mizutani, 1-1, Showa-cho, Kariya, Aichi Prefecture, Nihon Denso Co., Ltd. (72) Inventor, Tetsuo Toyama 1-1, Showa-cho, Kariya, Aichi, Nidec Within the corporation
Claims (3)
合物半導体基板の表面に酸化処理を行って表面酸化膜を
形成する第1工程と、 前記表面酸化膜上に所望のレジストパターンを形成する
第2工程と、 前記表面酸化膜におけるレジストパターンで覆われてい
ない露出部分をウェットエッチングで除去することによ
りレジスト残渣や表面の汚れを同時に除去し、清浄な化
合物半導体基板表面を露出させる第3工程と、 前記清浄な化合物半導体基板表面にエッチングや電極形
成を行う第4工程とを備えたことを特徴とする化合物半
導体装置の製造方法。1. A first step of oxidizing a surface of a compound semiconductor substrate containing at least gallium or arsenic to form a surface oxide film, and a second step of forming a desired resist pattern on the surface oxide film. A third step of removing a resist residue and surface stains at the same time by removing an exposed portion of the surface oxide film which is not covered with a resist pattern by wet etching to expose a clean compound semiconductor substrate surface; And a fourth step of etching or forming electrodes on the surface of the compound semiconductor substrate.
造方法において、第2工程でのレジストパターンとして
異なるレジストパターンを用いて第2工程から第4工程
を繰り返し行う化合物半導体装置の製造方法。2. The method of manufacturing a compound semiconductor device according to claim 1, wherein different resist patterns are used as resist patterns in the second step, and the second to fourth steps are repeated.
造方法において、第3工程でのウェットエッチング液は
フッ化水素酸である化合物半導体装置の製造方法。3. The method for manufacturing a compound semiconductor device according to claim 1, wherein the wet etching solution in the third step is hydrofluoric acid.
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