JPH0863374A - Tracing function incorporated type lsi - Google Patents

Abstract

PURPOSE: To provide the tracing function incorporated type LSI which has a function for holding history information on LSI operation without connecting hardware such as a memory to a bus. CONSTITUTION: The tracing function incorporated type LSI is equipped with an internal circuit 3 which has a specific data processing,function and generates an error generation signal in case of error occurrence, a trace memory circuit 7 which is connected to the internal circuit 3 in the LSI having input/output terminals 2 and 4 for inputting and outputting data to and from the internal circuit and stores and holds a specific number of the latest data among the input/output data to and from the internal circuit 3 and internal data in specific locations in the internal circuit 3 during operation, a memory control circuit 8 which receives an error occurrence signal and stops the storing and holding operation for new data by the trace memory circuit 7, and an interface circuit 9 which sends out the data stored and held in the trace memory circuit 7 after the storing and holding operation for the new data is stopped to the outside through an interface terminal 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI having a built-in trace function for tracing input / output information or an LSI internal signal to an operating LSI, and more particularly, tracing inside the LSI separately from a predetermined data processing function of the LSI. The present invention relates to a trace function built-in LSI provided with a functional portion.

[0002]

2. Description of the Related Art Conventionally, as a method of debugging a bug in the design of an LSI from an LSI device itself manufactured or manufactured as a prototype, a history of bus information (that is, information of an LSI input / output terminal) from several cycles before an error occurs The method of analysis is used.

As a method of obtaining the information of such an LSI input / output terminal, there are a method of directly measuring the voltage of the LSI terminal using a logic analyzer and a method of incorporating a bus trace function into a system using the LSI.

First, FIG. 7 is a diagram showing a configuration example of a conventional device for acquiring LSI input / output terminal information using a logic analyzer. In FIG. 7, the tester brings the probe 34, to which the logic analyzer 35 is connected, into contact with the input / output terminal 33 of the LSI 32 mounted on the substrate 31.
When a system including the LSI is operated in this state, the logic analyzer 35 takes in the signal of the input / output terminal 33, synchronizes the signal for each cycle, and sets the voltage level of the signal to “1” or “0”. It is converted into a binary value and the information is displayed on the display 36. When an abnormality occurs in the LSI, the cause of the abnormality is analyzed using the information from the error occurrence up to several clocks before.

Next, FIG. 8 is a diagram showing an example of the configuration of a conventional device for acquiring information on LSI input / output terminals in which a bus trace function is incorporated in a system. In FIG. 8A, the system bus 41 includes an LSI 42 to be debugged,
Information processing device 43 on a system other than the LSI 42
(Including an input / output device and a storage device), a trace RAM control circuit 44 and a trace RAM 45 are connected. Here, the system bus 41 and the trace RAM control circuit 44
The bus trace function is configured by the trace RAM 45.

Further, the trace RAM 45 is shown in FIG.
As shown in (b), it is composed of bus width × N-stage address,
The write address is circulated so that the latest N addresses are always held.

When a system incorporating such a bus trace function is operated, the bus information from the LSI 42 (that is, the information on the LSI input / output terminals) is stored in the trace RAM.
It is written in the trace RAM 45 under the control of the control circuit 44. When an abnormal value such as an error code is detected in the data on the bus monitored by the trace RAM control circuit 44 during the system operation, the trace RAM is detected.
The control circuit 44 holds the address of the trace RAM 45 at that time and prohibits writing to the trace RAM 45.

After this, the tester determines that the trace RAM 45
Information is read out, and the cause of the abnormality is analyzed using the read bus information from the occurrence of the error to N clocks before. In such a system, quick analysis can be performed by limiting the trace contents to information effective for analysis.

[0009]

If the LSI for debugging the design bug is a general-purpose LSI such as a memory or a microprocessor and is a mass-produced product, the above-mentioned method is used to save time and labor. Even if you debug over time, your productivity will not drop that much.

However, in the case of a product that needs to be manufactured in a small amount and in a wide variety of products, such as a special-purpose LSI called ASIC, for example, it is possible to debug a design bug efficiently or to operate the LSI while avoiding the bug. Examining the method will greatly contribute to the improvement of productivity.

From the viewpoint of such productivity improvement,
The method using the logic analyzer has a problem that it is very troublesome to connect the probe 34 to the input / output terminal 33 of the LSI and the efficiency is low. Further, in the surface-mount LSI, there is a problem that the interval between the input / output terminals 33 is narrow and there is a high risk that the probe 34 will contact an adjacent terminal. In addition, the latest packaging technology, BGA (Ba
ll Grid Array), it is impossible to connect the probe to the inner terminal, and it is not possible to obtain the necessary information.

On the other hand, when the bus trace function is added to the above-mentioned system, the bus trace function is incorporated into the system body ordered by the user to debug the LSI such as ASIC, and then the product is left as the product with the bus trace function left. Often shipped. In such a case,
When an error occurs during the use of the system, it is possible to consider further debugging work at the user's place or to consider a method of operating the LSI while avoiding a bug.

However, such a method can only obtain information from a preset terminal. In order to deal with this, it is necessary to set so that many terminals can be analyzed, but for that purpose, since the trace RAM 45 must be provided corresponding to each terminal,
The amount of hardware in the entire system increases. As the amount of hardware increases, the load on the system bus 41 increases and the operating cycle of the system becomes slower. Since the bus trace function is only for debugging the LSI, it is not preferable that the operation of the system, which is a product, slows down for such a reason.

Further, in the above two methods, the substrate 3
1 or only the information history from the input / output terminal connected to the system bus 41 can be checked. Actually, it may be necessary to check the signal inside the LSI that is not output from the input / output terminal, and such a request cannot be met by the above method. Therefore, although a dedicated terminal for outputting the internal signal may be provided in particular, the attachment of such a terminal increases the area of the LSI and increases the manufacturing cost.

The present invention has been made in view of such a situation, and in a system to which an LSI is connected, the history information of the connected LSI is held without connecting hardware to the system bus of the system. It is an object of the present invention to provide an LSI with a built-in trace function, which can realize the function to operate, and can operate the system at high speed.

[0016]

In order to solve the above-mentioned problems, the invention according to claim 1 has a predetermined data processing function, and during operation, the predetermined data processing function is detected and an error is detected. In an LSI having an internal circuit that issues an error occurrence signal when an error occurs, and an input / output terminal for inputting / outputting data to / from this internal circuit, connected to the internal circuit, and input / output data to / from this internal circuit during operation A trace memory circuit that always stores and holds the latest predetermined number of pieces of internal data at a predetermined position in the circuit, and a memory control circuit that receives an error occurrence signal and stops the storage and holding operation of new data in the trace memory circuit. , The data stored / held in the trace memory circuit after stopping the storage / holding operation of new data is transmitted via the interface terminal. A trace function built-in type LSI provided with an interface circuit for sending to the outside Te.

Further, the invention according to claim 2 has an internal circuit which has a predetermined data processing function, and which detects the predetermined data processing function during operation and issues an error occurrence signal when an error occurs, In an LSI having an input / output terminal for inputting / outputting data to / from an internal circuit, the latest input / output data to / from this internal circuit or an internal data at a predetermined position in this internal circuit which is connected to the internal circuit during operation is always the latest. A trace memory circuit that stores and holds a predetermined number of data, and a memory that receives an error occurrence signal or a forced stop signal externally input via an interrupt terminal to stop the storage and holding operation of new data in the trace memory circuit The interface between the control circuit and the data stored and held in the trace memory circuit after stopping the storage and holding operation of new data Trace function built-in LSI provided an interface circuit for sending to the outside through the over scan terminals
Is.

Further, the invention according to claim 3 has an internal circuit which has a predetermined data processing function and which detects the predetermined data processing function during operation and issues an error occurrence signal when an error occurs, In an LSI having an input / output terminal for inputting / outputting data to / from an internal circuit,
A trace memory circuit that is connected to an internal circuit and always stores and holds the latest predetermined number of data in the input / output data for this internal circuit or internal data at a predetermined position in this internal circuit, and the operating state of the internal circuit in advance. An operating condition detection circuit that outputs a condition matching signal when a condition specified from the outside is output, and a memory control circuit that receives an error occurrence signal or a condition matching signal and stops the storage holding operation of new data in the trace memory circuit, An LSI with a built-in trace function provided with an interface circuit for sending the data stored and held in the trace memory circuit to the outside through an interface terminal after the storage and holding operation of new data is stopped.

Further, an invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the invention is inserted between an internal circuit and a trace memory circuit, and input / output data for the internal circuit or This is a trace function built-in type LSI to which a data selection circuit for selecting data of a specified type from the outside of internal data at a predetermined position in the internal circuit and sending it to the trace memory circuit is added.

[0020]

Therefore, first, in the trace function built-in type LSI of the invention according to claim 1, the input / output data to / from the internal circuit, which is the original function of the LSI, or the internal signal in the internal circuit is trace memory. The data is input to the circuit and the latest predetermined number of data is always stored and held.

Here, when the error occurrence signal from the internal circuit is received, the memory control circuit stops the record holding operation of new data in the trace memory circuit.
Then, according to an instruction from the outside, the interface circuit reads the data in the trace memory circuit to the outside through the interface terminal, and analyzes the data.

Further, in the trace function built-in type LSI of the invention according to claim 2, the memory control circuit receives a forced stop signal via the interrupt terminal in addition to the same operation as the invention according to claim 1. Also in this case, the memory control circuit stops the record holding operation of new data in the trace memory circuit.

After this, similarly to the case described above, the interface circuit reads the data in the trace memory circuit to the outside through the interface terminal according to the instruction from the outside, and analyzes the data.

Further, in the trace function built-in type LSI of the invention according to claim 3, the same operation as that of the invention according to claim 1 is achieved, and when the internal circuit reaches a condition designated from the outside in advance, A condition agreement signal is output to the memory control circuit by the operating condition detection circuit.

Also in this case, the memory control circuit stops the recording and holding operation of new data in the trace memory circuit. Furthermore, in the trace function built-in type LSI of the invention according to claim 4, the same operation as the invention according to any one of claims 1 to 3 is achieved, and the input / output data to / from the internal circuit and the internal circuit The data selected by the data selecting means from among the internal signals of (3) are written in the trace memory. The data selected by the data selection means is designated from the outside.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a trace function built-in type L according to the present invention.
It is a block diagram which shows the 1st Example of SI.

In the LSI 1 shown in FIG. 1, the internal logic circuit 3 performs necessary arithmetic operations based on a signal input from an input terminal 2 connected to a system bus (not shown), and the arithmetic result is connected to an output terminal 4. It outputs to a system bus (not shown) and performs the same function as an LSI that does not have a trace function. An error detection circuit 13 is incorporated in the logic circuit 3.

In addition to the internal logic circuit 3, a trace RAM 7 into which input / output information from the input terminal 2 and the output terminal 4 is written, and an external circuit via the internal logic circuit 3 or the forced interrupt terminal 5 are provided in the LSI 1. Trace R for controlling the trace RAM 7 based on the signal from the controller 6
An AM control circuit 8 and a serial bus interface circuit 9 which is controlled by the external controller 6 via the serial bus terminal 10 and reads information from the trace RAM 7 and the trace RAM control circuit 8 are provided.

The trace RAM control circuit 8 is composed of a write permission generation circuit 11 and an address counter 12. Here, the write permission generation circuit 11
Is an error detection circuit 1 incorporated in the internal logic circuit 3.
On the basis of the error occurrence signal output from 3 or the forced stop signal input from the external controller 6 via the forced interrupt terminal 5, the count-up of the address counter 12 and the writing of the trace RAM 7 are prohibited. Further, the operation of the address counter 12 and the trace RAM 7 is restarted based on the release of the error occurrence signal of the internal logic circuit 3 or the forced stop signal from the external controller 6.

The address counter 12 counts up from 0 to N-1 and resets to 0 after N-1 to control the write address in the trace RAM 7. Further, the trace RAM 7 has a configuration of storage width bits × N stages.

Next, the operation of the trace function built-in type LSI of the present embodiment configured as described above will be explained. First, when the LSI 1 is operated, the trace RAM control circuit 8
Gives a write enable signal (WE) to the trace RAM 7. Here, the address counter 12 counts up the write address of the trace RAM 7 every cycle. As a result, the input / output information from the input terminal 2 and the output terminal 4 is written in the trace RAM 7.

The address circulates from 0 to N-1, so that the latest N cycles of information are always trace RA.
It is stored in M7. Next, when an error occurs in the operating internal logic circuit 3, the error is detected by the error detection circuit 13 in the internal logic circuit 3, and the error occurrence signal is delivered to the trace RAM control circuit 8. Trace R
When the AM control circuit 8 receives an error occurrence signal from the error detection circuit 13 or a forced stop signal from the external controller 6 via the forced interrupt terminal 5, the AM control circuit 8 stops counting up the address counter 12 and holds the address. At the same time, the write permission of the trace RAM 7 is stopped.
At this point of time, the trace RAM 7 stores the information of N cycles immediately before the occurrence of the error or the forced stop.

Further, the external controller 6 controls the serial bus interface circuit 9 to read the latest address value in the address counter 12 and the information for N stages in the trace RAM 7, and to obtain the latest information for N cycles. Obtainable.

As described above, the trace function built-in type LSI according to this embodiment has the trace RAM 7, the trace RAM control circuit 8, the serial bus interface circuit 9, the forced interrupt terminal 5 and the serial bus terminal 10 in the LSI 1. Input terminal 2 provided and connected to the system bus
Since the input / output information from the output terminal 4 and the recorded information can be read from the serial bus through the serial bus terminal 10 without passing through the system bus, analysis using a logic analyzer is not necessary. , L
Since the setup work and the like for connecting the probe to the SI terminal can be omitted, it is possible to efficiently carry out an analysis for debugging a bug in the LSI design or examining a method for avoiding the bug.

Further, when the bus trace function is incorporated in the system, since the trace RAM and the trace RAM control circuit are connected to the system bus, the amount of bus traffic increases due to these hardware and the operating speed of the system itself becomes slow. Become. However, since the system using the LSI of this embodiment does not need to connect these devices to the system bus, the hardware amount of the entire system can be reduced as compared with the case where the bus trace function is incorporated in the system. , The operation of the system can be made faster.

The speedup of the operation of such a system can be evaluated, for example, by the following equation (1), that is, the general equation of the propagation delay at the rising edge of the pulse. Tpd = Tup + Kup · (ΣCin + ΣCi) (1) where Tpd: signal propagation delay time (ns) Tup: output driver specific delay time (ns) Kup: output driver specific load coefficient (ns / ps) Cin: input driver input Load (pF) ΣCi: Wiring capacitance (pF) Here, Cin represents the capacitance of each component connected to the bus, and Σ
Ci represents the total wiring length (wiring capacity), and RAM
Is composed of a capacitor, it can be understood that Tpd, that is, the signal propagation delay time can be shortened by reducing the number of RAMs connected to the system bus. In other words, if the number of RAMs connected to the system bus is reduced, ΣCin will be reduced, and the total wiring length will be shortened.
ΣC i) becomes smaller. Therefore, trace RAM is LS
By incorporating it in I, the propagation delay time of the system bus is shortened and the operating cycle of the system is shortened.

Next, FIG. 2 is a block diagram showing a second embodiment of the trace function built-in type LSI according to the present invention.
The same parts as those in FIG. 1 are described with the same reference numerals, and only different parts will be described here.

In FIG. 2, the trace RAM 7b is connected to the internal logic circuit 3 instead of the input terminal 2 and the output terminal 4, and the internal signal is written at a predetermined position of the internal logic circuit 3.

Since the other structure is the same as that of the first embodiment, its description is omitted here. The operation of the trace function built-in type LSI of the present embodiment configured as described above is such that the information written in the trace RAM is not input / output information and is not output from the output terminal 4.
Since it is the same as the operation of the first embodiment except that it is the internal information of the above, the description thereof is omitted here.

As described above, the trace function built-in type LSI according to the present embodiment can trace the internal information without delaying the operation speed of the system as in the first embodiment, and without providing a new output terminal. The internal information of the internal logic circuit 3 can be traced. This is L
This leads to a reduction in the number of SI input / output terminals and a reduction in the chip area, so that the LSI manufacturing cost can be reduced.

Further, FIG. 3 is a block diagram showing a third embodiment of a trace function built-in type LSI according to the present invention. The same parts as those in FIG. 1 are described with the same reference numerals, and only different parts will be described here.

In FIG. 3, the input terminal 2 and the output terminal 4
And signals from a plurality of positions in the internal logic circuit 3 are input to the selector 14, and the selector 14 selects information to be written in the trace RAM 7c based on the information in the mode switching register 15.

The mode switching register 15 includes a serial bus interface circuit 9 from the external controller 6.
The target of the information selected by the selector 14 is written via b. The contents of the mode switching register 15 can be rewritten.

Information of the input terminal 2 and the output terminal 4 or the internal logic circuit 3 selected by the selector 14 is written in the trace RAM 7c. The data selection circuit includes, for example, the selector 14 and the mode switching register 1
It is composed of 5.

Since the other structure is the same as that of the first embodiment, its description is omitted here. Next, the trace function built-in type L of the present embodiment configured as described above
The operation of SI will be described.

First, a value is set in the mode switching register 15 via the serial bus interface circuit 9b. The target of the information traced is specified by this set value. The trace content varies depending on the application, but in this embodiment, it is an input signal, an output signal, or an internal signal of the internal logic circuit 3 such as a control register. If the number of internal signals to be traced is large, they can be divided into a plurality of groups. Of these pieces of information, the one designated in the mode switching register 15 as described above is selected by the selector 14 to be selected in the trace RAM 7.
Input to c.

When the LSI 1 is operated after the trace information target is designated, the trace RAM control circuit 8 gives a write enable signal (WE) to the trace RAM 7c. Here, the address counter 12 has a trace RAM for each cycle.
The write address of 7c is counted up, and as a result, the input / output information from the input terminal 2 and the output terminal 4 is written in the trace RAM 7c.

The address circulates from 0 to N-1, whereby the latest N cycles of information are always traced RA.
It is stored in M7c. Next, when an error occurs in the operating internal logic circuit 3, the error is detected by the error detection circuit 13 in the internal logic circuit 3, and the error occurrence signal is delivered to the trace RAM control circuit 8. When the trace RAM control circuit 8 receives an error occurrence signal from the error detection circuit 13 or a forced stop signal from the external controller 6 via the forced interrupt terminal 5, the trace RAM control circuit 8 stops counting up the address counter 12 and holds the address. At the same time, the write permission of the trace RAM 7c is stopped. At this point in time, the trace RAM 7c stores information on N cycles immediately before the occurrence of an error or forced stop.

Further, the external controller 6 controls the serial bus interface circuit 9b so that the latest address value in the address counter 12 and the trace RAM 7c can be obtained.
It is possible to obtain the latest N cycles of information by reading the information of N stages in the above.

As described above, the LSI with built-in trace function according to the present embodiment can obtain the same effect as that of the first or second embodiment, and further divides input information, output information, and internal information into finer groups. Since the trace bit width can be reduced, the required RAM capacity can be reduced. In addition, the mode switching register 15
The necessary information can be switched and selected with, so more information can be traced. Therefore, the capacity of the trace RAM 7c can be made smaller than in the case of the first or second embodiment, and more information can be traced.

Further, FIG. 4 is a block diagram showing a fourth embodiment of a trace function built-in type LSI according to the present invention. The same parts as those in FIG. 3 are described with the same reference numerals, and only different parts will be described here.

In FIG. 4, an operation condition detection circuit 16 is provided in the internal logic circuit 3 in addition to the error detection circuit 13. The operation condition detection circuit 16 sends a condition match signal to the trace RAM control circuit 8 when the operation condition written from the external controller 6 via the serial bus interface circuit 9c is satisfied.

Since the other structure is the same as that of the third embodiment, its description is omitted here. Next, the trace function built-in type L of the present embodiment configured as described above
The operation of SI will be described.

First, a necessary value is input to the operation condition detection circuit 16 via the serial bus interface circuit 9c to set the LSI stop condition. Operating condition detection circuit 1
The sixth embodiment is the same as the third embodiment except that the condition matching signal is transmitted to the trace RAM control circuit 8 when the condition set therein is satisfied during the operation of the LSI 1.

Consider, for example, that the history until the M-th register in the internal logic circuit 3 becomes the value K is obtained during the operation. First, when the Mth register in the internal logic circuit 3 becomes the value K in the operating condition detection circuit 16 via the serial bus interface circuit 9c, the condition matching signal is traced RA.
It is set to send to the M control circuit 8.

Next, the mode switching register 15 is rewritten through the serial bus interface circuit 9c, and the Mth register is set to be traced. After the above setting, the LSI is operated. In the operation, if the error does not occur until the Mth register becomes K and the forced stop signal from the outside is not input, when the Mth register becomes K, the condition matching signal is sent to the trace RAM control circuit 8. Then, the trace RAM 7c is stopped.

If, for example, the input value until the M-th register becomes K is also required, the value of the mode switching register 15 may be switched to perform the same operation. in this way,
In the trace function built-in type LSI according to the present embodiment, the writing of new data to the trace RAM 7c can be stopped under the condition set in the operation condition detection circuit 16, so that the same effect as the third embodiment can be obtained. The circuit (LSI) can be stopped under any condition in the internal logic circuit 3 and the history up to that point can be analyzed.

FIG. 5 is a block diagram showing the fifth embodiment of the trace function built-in type LSI according to the present invention.
The same parts as those in FIG. 4 are described with the same reference numerals, and only different parts will be described here.

In FIG. 5, an operation condition detection circuit 16b is provided in the error detection circuit 13b in the internal logic circuit 3. Therefore, the error detection circuit 13b generates an error when an error occurs in the internal circuit or when the operation condition written in the operation condition detection circuit 16b from the external controller 6 via the serial bus interface circuit 9c is satisfied. A forced stop signal is sent to the trace RAM control circuit 8 instead of the signal or the condition matching signal.

Since the other structure is the same as that of the fourth embodiment, its explanation is omitted here. The operation of the trace function built-in type LSI of the present embodiment configured as described above is the fourth except that the error occurrence signal or the forced stop signal is sent to the trace RAM control circuit 8 instead of the condition matching signal. It is similar to the embodiment of.

As described above, in the trace function built-in type LSI according to the present embodiment, since the operating condition detection circuit 16b is provided in the error detection circuit 13b, the same effect as that of the fourth embodiment can be obtained and the fourth embodiment. Error detection circuit 1 in the embodiment
3 can be omitted, so that the circuit can be simplified.

FIG. 6 is a block diagram showing a sixth embodiment of a trace function built-in type LSI according to the present invention.
The same parts as those in FIG. 1 are described with the same reference numerals, and only different parts will be described here.

In FIG. 6, an LSI with a built-in trace function
Does not include the forced interrupt terminal in FIG. In this embodiment, a forced stop signal from the outside is input to the trace RAM control circuit 8 via the serial bus terminal 10 and the serial bus interface circuit 9d.

Since the other structure is the same as that of the first embodiment, its explanation is omitted here. In the operation of the trace function built-in type LSI of the present embodiment configured as described above, the trace RAM control circuit 8 receives a forced stop signal from the outside via the serial bus interface circuit 9d.
Since the operation is the same as that of the first embodiment except that it is input to, the description thereof will be omitted here.

As described above, in the trace function built-in type LSI according to the present embodiment, the forced interrupt terminal is omitted from the first embodiment, and the forced stop signal from the outside is traced through the serial bus interface circuit 9d to the trace RAM. Since the input is made to the control circuit 8, the input and output terminals of the LSI can be reduced in addition to the same effect as the first embodiment.
This leads to a reduction in the chip area, so that the LSI manufacturing cost can be reduced.

Further, this embodiment is naturally applicable to the second, third, fourth and fifth embodiments. In addition,
Although the embodiment uses the serial bus for connection with the external controller, the present invention is not limited to this, and any bus may be used.

Further, in the present embodiment, the information read control in the trace RAM and the address counter is performed by the external controller, but the present invention is not limited to this, and if the system bus is not used. Information may be read by any method, for example, a read control portion may be provided in the LSI. As described above, the present invention can be variously modified without departing from the gist thereof.

[0068]

As described above in detail, according to the present invention, L
In a system to which SI is connected, the function to retain the history information of the connected LSI can be realized without connecting the hardware to the system bus of the system, and eventually the system has a trace function that can operate the system at high speed. A type LSI can be provided.

[Brief description of drawings]

FIG. 1 is a first LSI with a built-in trace function according to the present invention.
FIG.

FIG. 2 is a second LSI with a built-in trace function according to the present invention.
FIG.

FIG. 3 is a third LSI with a built-in trace function according to the present invention.
FIG.

FIG. 4 is a fourth LSI with a built-in trace function according to the present invention.
FIG.

FIG. 5 is a fifth LSI with a built-in trace function according to the present invention.
FIG.

FIG. 6 is a sixth LSI with a built-in trace function according to the present invention.
FIG.

FIG. 7 is a diagram showing a configuration of a conventional device that acquires LSI input / output terminal information using a logic analyzer.

FIG. 8 is a diagram showing a configuration of a conventional device for acquiring information on an LSI input / output terminal in which a bus trace function is incorporated in a system.

[Explanation of symbols]

1 ... LSI, 2 ... Input terminal, 3 ... Internal logic circuit, 4 ... Output terminal, 5 ... Forced interrupt terminal, 7, 7b, 7c ... Trace RAM, 8 ... Trace RAM control circuit, 9, 9
b, 9c, 9d ... Serial bus interface circuit,
11 ... Write permission generation circuit, 12 ... Address counter, 13, 13b ... Error detection circuit, 14 ... Selector,
15 ... Mode switching register 16, 16b ... Operating condition detection circuit.

Claims (4)

[Claims] 1. An internal circuit which has a predetermined data processing function and which detects the predetermined data processing function during operation and issues an error occurrence signal when an error occurs, and inputs and outputs data to and from this internal circuit. An LSI having an input / output terminal for storing the latest predetermined number of data in the input / output data to / from the internal circuit or the internal data at a predetermined position in the internal circuit which is connected to the internal circuit during operation. A trace memory circuit, a memory control circuit that receives the error occurrence signal and stops the storage and holding operation of new data in the trace memory circuit, and a storage and holding unit in the trace memory circuit after stopping the storage and holding operation of the new data With an interface circuit that sends the stored data to the outside through the interface terminal LSI with built-in functions. 2. An internal circuit which has a predetermined data processing function and which detects the predetermined data processing function during operation and issues an error occurrence signal when an error occurs, and inputs and outputs data to and from this internal circuit. An LSI having an input / output terminal for storing the latest predetermined number of data in the input / output data to / from the internal circuit or the internal data at a predetermined position in the internal circuit which is connected to the internal circuit during operation. A trace memory circuit, a memory control circuit that receives the error occurrence signal or a forced stop signal input from the outside through an interrupt terminal and stops the memory holding operation of new data in the trace memory circuit, and the new data Data stored in the trace memory circuit after stopping the memory holding operation of the An LSI with a built-in trace function that has an interface circuit that sends it to the outside. 3. An internal circuit which has a predetermined data processing function and which detects the predetermined data processing function during operation and issues an error occurrence signal when an error occurs, and inputs and outputs data to and from this internal circuit. An LSI having an input / output terminal for storing the latest predetermined number of data in the input / output data to / from the internal circuit or the internal data at a predetermined position in the internal circuit which is connected to the internal circuit during operation. A trace memory circuit, an operation condition detection circuit that outputs a condition match signal when the operation state of the internal circuit satisfies a condition specified in advance from the outside, and the trace memory that receives the error occurrence signal or the condition match signal A memory control circuit for stopping the memory holding operation of new data in the circuit, and after stopping the memory holding operation of the new data Trace function built-in LSI having an interface circuit for sending data stored and held in the trace memory circuit to the outside through the interface terminal. 4. An input / output data for the internal circuit or data of a type specified from outside of internal data at a predetermined position in the internal circuit is inserted between the internal circuit and the trace memory circuit. 4. The trace function built-in type LSI according to any one of claims 1 to 3, further comprising a data selection circuit for selecting and transmitting to the trace memory circuit.