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JPH0859795A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0859795A
JPH0859795A JP6198168A JP19816894A JPH0859795A JP H0859795 A JPH0859795 A JP H0859795A JP 6198168 A JP6198168 A JP 6198168A JP 19816894 A JP19816894 A JP 19816894A JP H0859795 A JPH0859795 A JP H0859795A
Authority
JP
Japan
Prior art keywords
epoxy resin
semiconductor device
resin composition
curing
encapsulated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6198168A
Other languages
Japanese (ja)
Inventor
Toshiaki Ishii
利昭 石井
Kuniyuki Eguchi
州志 江口
Akira Mogi
亮 茂木
Hiroyoshi Kokado
博義 小角
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6198168A priority Critical patent/JPH0859795A/en
Publication of JPH0859795A publication Critical patent/JPH0859795A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Epoxy Resins (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】 【構成】エポキシ樹脂とフェノール性水酸基を有する硬
化剤，硬化促進剤，分子中にアルミニウムを有する特定
の化合物を含有する樹脂組成物によって封止されている
樹脂封止型半導体装置。 【効果】金属表面，ポリイミドへの接着性が大きく、半
導体装置のインサートとの接着性が良好であるため、耐
はんだリフロー性に優れている。 (57) [Summary] [Structure] A resin-encapsulated semiconductor encapsulated with a resin composition containing an epoxy resin, a curing agent having a phenolic hydroxyl group, a curing accelerator, and a specific compound having aluminum in the molecule. apparatus. [Effect] Since the adhesiveness to the metal surface and the polyimide is large and the adhesiveness to the insert of the semiconductor device is good, the solder reflow resistance is excellent.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、成形性，硬化後の力学
的な物性に優れ、かつ、半導体装置構成する各インサー
トとの接着に優れたエポキシ樹脂組成物で封止した耐は
んだリフロークラック性に優れた樹脂封止型半導体装置
に関する。FIELD OF THE INVENTION The present invention relates to a solder reflow crack which is excellent in moldability and mechanical properties after curing, and which is sealed with an epoxy resin composition excellent in adhesion to each insert constituting a semiconductor device. The present invention relates to a resin-sealed semiconductor device having excellent properties.

【０００２】[0002]

【従来の技術】樹脂封止技術は量産性が高いため、トラ
ンジスタ，ＩＣ，ＬＳＩ等の半導体素子のパッケージ技
術として広く用いられている。半導体封止材料には、エ
ポキシ樹脂とフェノール樹脂に硬化促進剤を配合した組
成物が一般的に用いられている。2. Description of the Related Art Since resin encapsulation technology has high mass productivity, it is widely used as a packaging technology for semiconductor devices such as transistors, ICs and LSIs. As a semiconductor encapsulating material, a composition in which a curing accelerator is mixed with an epoxy resin and a phenol resin is generally used.

【０００３】近年、半導体素子の集積度の増加，電子電
気機器の小型化の要求から半導体装置の形状や実装方法
が変化しているため、封止樹脂の耐熱性，耐湿性，低応
力化などなお一層の高信頼性化が望まれている。In recent years, the shape and mounting method of semiconductor devices have changed due to the increasing degree of integration of semiconductor elements and the demand for miniaturization of electronic and electrical equipment. Therefore, the heat resistance, moisture resistance, and stress of sealing resin are reduced. Still higher reliability is desired.

【０００４】例えば、表面実装型の半導体装置では、プ
リント基板への実装時にパッケージ全体が２００〜２６
０℃に加熱されるため、パッケージが吸湿していると、
内部の水分の急激な膨張により、パッケージの膨張，イ
ンサートと封止材の剥離，パッケージクラックが生じ
る。For example, in a surface mount type semiconductor device, the entire package is 200 to 26 when mounted on a printed circuit board.
Since it is heated to 0 ℃, if the package absorbs moisture,
Due to the rapid expansion of moisture inside, expansion of the package, separation of the insert and sealing material, and package cracking occur.

【０００５】この問題には、従来からリフロー時の封止
樹脂層の高温強度を高めること、樹脂層の吸湿率を小さ
くする為の検討が行われている。薄型の半導体装置では
封止樹脂層の強度を高めることよりも吸湿率を小さくす
ること、また剥離を防止するためにインサートと封止樹
脂との接着力を高めることが有効な手法となっている。
この方法として、ビフェニル型エポキシ樹脂とフェノー
ルアラルキル樹脂硬化剤からなるエポキシ樹脂組成物で
封止した半導体装置が特開平3−207714 号並びに特開平
4−48759号公報に開示されている。また、ナフタレン構
造を有するエポキシ樹脂からなる樹脂組成物を用いた半
導体装置では特開平4−50223号並びに特開平4−199857
号公報に開示されている。一般に、封止材の接着性を高
める目的で、エポキシシランなどのシランカップリング
剤がエポキシ樹脂組成物中に配合されている。しかし、
エポキシ樹脂とこれらカップリング剤を組み合わせた場
合にも、耐はんだリフロー性に対する効果は十分ではな
い。To solve this problem, studies have been made to increase the high temperature strength of the sealing resin layer during reflow and to reduce the moisture absorption rate of the resin layer. In thin semiconductor devices, it is effective to reduce the moisture absorption rate rather than to increase the strength of the sealing resin layer, and to increase the adhesive force between the insert and the sealing resin to prevent peeling. .
As this method, a semiconductor device sealed with an epoxy resin composition composed of a biphenyl type epoxy resin and a phenol aralkyl resin curing agent is disclosed in JP-A-3-207714 and JP-A-3-207714.
It is disclosed in Japanese Patent Publication No. 4-48759. Further, a semiconductor device using a resin composition made of an epoxy resin having a naphthalene structure is disclosed in JP-A-4-50223 and JP-A-4-199857.
No. 6,086,045. In general, a silane coupling agent such as epoxysilane is mixed in the epoxy resin composition for the purpose of improving the adhesiveness of the encapsulant. But,
Even when the epoxy resin and these coupling agents are combined, the effect on the solder reflow resistance is not sufficient.

【０００６】[0006]

【発明が解決しようとする課題】低吸湿，高接着力を有
するエポキシ樹脂系を用いる従来の技術は、耐はんだリ
フロー性に優れるが、その効果はまだ十分ではない。ま
た、半導体装置の内部剥離に注目すると、シリコンチッ
プやシリコンチップの回路面を封止材からの応力から保
護するために用いられているポリイミドパッシベーショ
ン膜と封止材間の接着力を高めることが重要である。こ
の部分の剥離は実装後の耐湿信頼性，温度サイクル性を
著しく低下させる原因となる。The conventional technique using an epoxy resin system having a low moisture absorption and a high adhesive force is excellent in solder reflow resistance, but its effect is not yet sufficient. Focusing on the internal peeling of the semiconductor device, it is possible to enhance the adhesive force between the polyimide passivation film used to protect the silicon chip and the circuit surface of the silicon chip from the stress from the encapsulant and the encapsulant. is important. Peeling of this part causes a significant drop in moisture resistance reliability and temperature cycle performance after mounting.

【０００７】本発明の目的は、半導体装置の各インサー
トと良好な接着性を有するエポキシ樹脂組成物で封止し
た耐はんだリフロー性，温度サイクル性，耐湿信頼性に
優れた樹脂封止型半導体装置を提供することにある。An object of the present invention is to provide a resin-encapsulated semiconductor device excellent in solder reflow resistance, temperature cycle property, and moisture resistance reliability, which is encapsulated with an epoxy resin composition having good adhesiveness with each insert of the semiconductor device. To provide.

【０００８】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明者等は、成形後における封止材のポリイミド
に対する接着力、金属に対する接着力を向上させるべ
く、各種エポキシ樹脂，硬化剤に添加する接着性向上剤
としてのカップリング剤の化学構造と接着力を検討し
た。その結果、アルミニウムのキレート錯体を用いれ
ば、シリコンと封止材，ポリイミドパッシベーション膜
と封止材の接着力が向上することを見いだした。In order to achieve the above object, the present inventors have developed various epoxy resins and hardeners in order to improve the adhesive force of a sealing material to polyimide after molding and the adhesive force to metal. The chemical structure and the adhesive strength of the coupling agent as an adhesiveness improver added to were investigated. As a result, they have found that the use of the aluminum chelate complex improves the adhesive strength between silicon and the sealing material and between the polyimide passivation film and the sealing material.

【０００９】すなわち、本発明の樹脂封止型半導体装置
は、エポキシ樹脂と、フェノール性水酸基を有する硬化
剤，硬化促進剤、さらに化１または化２で表される化合
物を必須成分として含有するエポキシ樹脂組成物で封止
したことを特徴とする。That is, the resin-encapsulated semiconductor device of the present invention includes an epoxy resin, a curing agent having a phenolic hydroxyl group, a curing accelerator, and an epoxy containing the compound represented by Chemical Formula 1 or Chemical Formula 2 as essential components. It is characterized in that it is sealed with a resin composition.

【００１０】本発明において、エポキシ樹脂は、一分子
中にエポキシ樹脂を複数個有し、半導体封止用樹脂とし
て一般的に使用されるものであればいかなるものであっ
てもよい。このようなエポキシ樹脂は、ビスフェノール
Ａ，ＦまたはＳ型エポキシ樹脂，フェノールノボラック
型エポキシ樹脂，クレゾールノボラック型エポキシ樹
脂、また分子中にビフェニル骨格やナフタレン骨格，ジ
シクロペンタジエン骨格を有する二官能以上のエポキシ
樹脂，脂環式エポキシ樹脂、また以上のエポキシ樹脂を
臭素化したエポキシ樹脂等が挙げられる。本発明では、
これらを単独あるいは数種類混合して使用される。In the present invention, the epoxy resin may be any one as long as it has a plurality of epoxy resins in one molecule and is generally used as a semiconductor encapsulating resin. Examples of such epoxy resin include bisphenol A, F or S type epoxy resin, phenol novolac type epoxy resin, cresol novolac type epoxy resin, and bifunctional or higher functional epoxy having biphenyl skeleton, naphthalene skeleton or dicyclopentadiene skeleton in the molecule. Examples thereof include resins, alicyclic epoxy resins, and epoxy resins obtained by brominated the above epoxy resins. In the present invention,
These are used alone or as a mixture of several kinds.

【００１１】本発明において、フェノール性水酸基を有
する硬化剤は、一分子中にフェノール性の水酸基を複数
個有し、半導体封止用樹脂として一般的に使用されるも
のであればいかなるものであってもよい。このような硬
化剤として、ビスフェノールＡ，ＦまたはＳ，フェノー
ルノボラック，クレゾールノボラック、また、分子中に
ビフェニル骨格をもつビフェノール，ナフタレン骨格を
有するもの、ジシクロペンタジエン骨格を有するもの、
また以上の樹脂の共重合体、または数種類の混合物が使
用される。これらは樹脂の反応性，流動性などの成形性
と硬化物の吸湿率，力学物性等の諸物性に応じて使用さ
れる。In the present invention, the curing agent having a phenolic hydroxyl group is any one as long as it has a plurality of phenolic hydroxyl groups in one molecule and is generally used as a semiconductor encapsulating resin. May be. As such a curing agent, bisphenol A, F or S, phenol novolac, cresol novolac, biphenol having a biphenyl skeleton in the molecule, those having a naphthalene skeleton, those having a dicyclopentadiene skeleton,
Further, copolymers of the above resins or a mixture of several kinds are used. These are used depending on various properties such as resin moldability such as reactivity and fluidity, and moisture absorption rate of cured product and mechanical properties.

【００１２】本発明に用いられるエポキシ樹脂組成物に
は、硬化反応を促進させるため硬化促進剤が添加され
る。本発明で用いられる硬化促進剤はエポキシ樹脂と硬
化剤の硬化反応を促進するものなら特に限定されるもの
ではない。通常は、エポキシ樹脂組成物の保存安定性や
成形性、硬化後の電気特性などが良好な、トリフェニル
フォスフィン，トリフェニルフォスフォニウム−トリフ
ェニルボレート，テトラフェニルフォスフォニウム−テ
トラフェニルボレート、およびこれらの誘導体等の分子
中に燐を含有するもの、またトリエチレンジアミン，ジ
アミノジフェニルメタン、１，８−ジアザビシクロ
（５，４，０）−ウンデセン，イミダゾールおよびその
誘導体などのアミン系のもの、ＢＦ３，スルホニウム塩
等が、一種類、あるいは複数種類をエポキシ樹脂に添加
され用いられる。添加量はエポキシ樹脂組成物の成形性
や硬化物の物性にあわせ任意に決めることができる。A curing accelerator is added to the epoxy resin composition used in the present invention in order to accelerate the curing reaction. The curing accelerator used in the present invention is not particularly limited as long as it accelerates the curing reaction between the epoxy resin and the curing agent. Usually, storage stability and moldability of the epoxy resin composition, good electrical properties after curing, triphenylphosphine, triphenylphosphonium-triphenylborate, tetraphenylphosphonium-tetraphenylborate, And those containing phosphorus in the molecule such as derivatives thereof, amine-based ones such as triethylenediamine, diaminodiphenylmethane, 1,8-diazabicyclo (5,4,0) -undecene, imidazole and derivatives thereof, BF3. A sulfonium salt or the like is used by adding one kind or a plurality of kinds to the epoxy resin. The addition amount can be arbitrarily determined according to the moldability of the epoxy resin composition and the physical properties of the cured product.

【００１３】本発明におけるエポキシ成形材料では、化
１，化２で表されるアルミキレート化合物の配合が必要
で、エポキシ樹脂に対して０.００５ 〜５重量％配合す
ることが好ましい。すなわち、０.００５ 重量％ではエ
ポキシ成形材料と各種金属，ポリイミド等の接着性に効
果が小さく、また５重量％をこえると成形金型の汚れ
や，離型性の低下，エポキシ樹脂成形材料の硬化不良等
の問題が起こる傾向がある。エポキシ樹脂の硬化触媒と
してアルミキレート化合物を用いる方法は、特開昭57−
133119号，特開昭57−133122号公報に開示されている。
この方法は、エポキシ樹脂成形材料の保存安定性と反応
性の両方を向上する為の方法である。本発明では、エポ
キシ樹脂の硬化促進剤として触媒を別途配合し、アルミ
キレート化合物はインサート間の接着性を向上するため
のカップリング剤として作用させるため、アルミキレー
ト化合物が直接エポキシ樹脂と反応する上記の発明とは
異なっている。In the epoxy molding material of the present invention, it is necessary to mix the aluminum chelate compound represented by Chemical formula 1 and Chemical formula 2, and it is preferable to mix it in an amount of 0.005 to 5% by weight with respect to the epoxy resin. That is, when the amount is 0.005% by weight, the adhesiveness between the epoxy molding material and various metals, polyimide, etc. is less effective, and when it exceeds 5% by weight, the molding die becomes dirty and the releasability deteriorates. Problems such as poor curing tend to occur. A method using an aluminum chelate compound as a curing catalyst for an epoxy resin is disclosed in JP-A-57-
No. 133119 and JP-A No. 57-133122.
This method is a method for improving both storage stability and reactivity of the epoxy resin molding material. In the present invention, a catalyst is separately blended as a curing accelerator for the epoxy resin, and the aluminum chelate compound acts as a coupling agent for improving the adhesiveness between the inserts, so that the aluminum chelate compound directly reacts with the epoxy resin. Is different from the invention of.

【００１４】本発明のエポキシ樹脂成形材料では上記の
素材の他、必要に応じ、充填剤，離型剤，着色剤，カッ
プリング剤，可とう化剤，難燃剤等を添加して用いる。
充填剤はエポキシ成形材料の熱膨張係数を小さくする目
的で、また、強度を高めるために用いられ、タルク，ク
レー，シリカ，炭酸カルシウム，水酸化アルミニウム，
水酸化マグネシウム，ガラス繊維，セラミック繊維等の
無機質充填剤全般を用いることができる。充填量は５０
容積％〜８５容積％が適当で、５０容積％未満では熱膨
張係数の低減，強度の向上に対して十分な効果が得られ
ない。また、８５容積％を越えて配合すると、充填剤の
最密充填密度がエポキシ樹脂マトリックスの配合量を下
回るため、成形材料の調製が困難となり、また調製後の
粘度が非常に高くなり、成形性が低下する。したがって
充填量は５０容積％〜８５容積％が好ましい。離型剤は
成形金型からの離型を容易にするもので、カルナバワッ
クス，モンタン酸系ワックス，ポリオレフィン系ワック
スを単独で用いるか、これらを併用して用いる。添加量
は、全量の０.０１ 〜５重量％が好ましい。すなわち
０.０１ ％未満では離型性に効果がなく、また５％をこ
えるとリードフレームやシリコンチップとの接着性が低
下するからである。着色剤はカーボンブラックを用いる
ことが望ましい。硬化物の強靭化，低弾性率化のため配
合される可とう化剤はエポキシ樹脂と非相溶のアミノ基
またはエポキシ基，カルボキシル基末端のブタジエン・
アクリロニトリル系共重合体、また、末端または側鎖ア
ミノ基，水酸基，エポキシ基，カルボキシル基変性シリ
コーン樹脂系可とう化剤などが用いられる。In the epoxy resin molding material of the present invention, in addition to the above materials, if necessary, a filler, a release agent, a coloring agent, a coupling agent, a softening agent, a flame retardant, etc. are added.
The filler is used for the purpose of reducing the coefficient of thermal expansion of the epoxy molding material and for increasing the strength, such as talc, clay, silica, calcium carbonate, aluminum hydroxide,
Inorganic fillers such as magnesium hydroxide, glass fiber, and ceramic fiber can be used in general. Filling amount is 50
Volume% to 85% by volume is suitable, and if it is less than 50% by volume, sufficient effects cannot be obtained for reducing the thermal expansion coefficient and improving the strength. Further, if the content is more than 85% by volume, the closest packing density of the filler will be less than the content of the epoxy resin matrix, making it difficult to prepare a molding material, and the viscosity after preparation will be extremely high, resulting in moldability. Is reduced. Therefore, the filling amount is preferably 50% by volume to 85% by volume. The release agent facilitates release from the molding die, and carnauba wax, montanic acid-based wax, polyolefin-based wax may be used alone or in combination. The addition amount is preferably 0.01 to 5% by weight of the total amount. That is, if it is less than 0.01%, the releasability is not effective, and if it exceeds 5%, the adhesion to the lead frame or the silicon chip is deteriorated. It is desirable to use carbon black as the colorant. The softening agent that is mixed to make the cured product tougher and have a lower elastic modulus is an amino group or epoxy group that is incompatible with the epoxy resin, or a butadiene with a carboxyl group terminal.
An acrylonitrile-based copolymer, a terminal or side chain amino group, a hydroxyl group, an epoxy group, a carboxyl group-modified silicone resin-based softening agent and the like are used.

【００１５】上記材料を配合，混合，混練，粉砕し更に
必要に応じ造粒しエポキシ樹脂成形材料を得る。混練は
一般的には、熱ロールや押し出し機などによって行う。
本発明の樹脂封止型半導体装置は、このように得られた
エポキシ樹脂組成物を用いて半導体チップを封止するこ
とにより得られる。その製造方法は、低圧トランスファ
成形が、通常、用いられるが、場合によっては、圧縮成
形，注型等の方法によっても可能である。また、半導体
装置の信頼性を向上するため、エポキシ樹脂組成物によ
る成形後、１５０℃以上の温度で所定時間アフタキュア
を行うことが望ましい。The above materials are blended, mixed, kneaded, pulverized and further granulated as required to obtain an epoxy resin molding material. The kneading is generally performed with a hot roll or an extruder.
The resin-encapsulated semiconductor device of the present invention is obtained by encapsulating a semiconductor chip with the epoxy resin composition thus obtained. Low pressure transfer molding is usually used as the manufacturing method, but in some cases, compression molding, casting or the like may be used. Further, in order to improve the reliability of the semiconductor device, it is desirable to perform aftercure at a temperature of 150 ° C. or higher for a predetermined time after molding with the epoxy resin composition.

【００１６】本発明では以上のように化１，化２で示さ
れる化合物をエポキシ樹脂組成物中に配合して用いる
他、半導体素子やリードフレーム等のインサート単独あ
るいはそのいくつかに対して、化１，化２で示される化
合物を塗布し、インサートの表面を処理した後、エポキ
シ樹脂組成物を用いて封止することによっても、信頼性
に優れた半導体装置を得ることができる。この際、化
１，化２で示される化合物を適当な有機溶剤に溶解し用
いる事が望ましい。溶剤としては特に、各種シランカッ
プリング剤が接着性を高める上で好適である。これら溶
液を塗布した後のインサートは、高温で数分から数時間
の熱処理を行うことにより、エポキシ樹脂成形材料との
接着性を大きく高めることができる。In the present invention, the compounds represented by Chemical formulas 1 and 2 are blended in the epoxy resin composition as described above, and in addition to the inserts such as semiconductor elements and lead frames, or some of them, It is also possible to obtain a highly reliable semiconductor device by applying the compound represented by Chemical formula 1 and Chemical formula 2, treating the surface of the insert, and then sealing with an epoxy resin composition. At this time, it is desirable to dissolve and use the compounds represented by Chemical formulas 1 and 2 in a suitable organic solvent. As the solvent, various silane coupling agents are particularly suitable for improving the adhesiveness. By subjecting the insert after applying these solutions to a heat treatment at a high temperature for a few minutes to a few hours, the adhesiveness with the epoxy resin molding material can be greatly enhanced.

【００１７】[0017]

【作用】本発明で成形性および耐はんだリフロー性に優
れ、しかも他の信頼性も良好な樹脂封止型半導体装置が
得られる理由は、化１，化２で示されるアルミキレート
カップリング剤が、エポキシ樹脂成形材料の硬化中に接
着界面に滲みだしエポキシ樹脂とインサートとの濡れ性
が向上しさらには接着性も大きくなるためである。これ
は金属表面とアルミキレートの相互作用により接着性が
向上し、さらには、ポリイミドとアルミキレートの界面
の相互作用が、シランカップリング剤等に比較して大き
いため、エポキシ樹脂成形材料とポリイミド等のインサ
ートとの接着性が大幅に向上するためである。The reason why the resin-encapsulated semiconductor device of the present invention is excellent in moldability and solder reflow resistance and also has good reliability is that the aluminum chelate coupling agent shown in Chemical formula 1 or Chemical formula 2 is used. This is because the epoxy resin molding material seeps out to the adhesive interface during curing and the wettability between the epoxy resin and the insert is improved, and the adhesiveness is also increased. This is because the adhesiveness is improved by the interaction between the metal surface and the aluminum chelate, and further, the interaction at the interface between the polyimide and the aluminum chelate is larger than that of the silane coupling agent, so that the epoxy resin molding material and the polyimide etc. This is because the adhesiveness with the insert of is greatly improved.

【００１８】本発明の樹脂封止型半導体装置パッケージ
はプリント基板への実装時に２４０℃〜２６０℃の高温
にさらした場合にも、エポキシ樹脂成形材料と各インサ
ート間の接着力が大きい為、パッケージ内部の水分の急
激な気化によるパッケージ内のインサート界面が剥離を
生じない。また、吸湿水分の溜まり場所となる剥離等が
少なくなるため、パッケージのクラック等も低減し良好
な耐はんだリフロー性を示す。The resin-encapsulated semiconductor device package of the present invention has a large adhesive force between the epoxy resin molding material and each insert even when it is exposed to a high temperature of 240 ° C. to 260 ° C. when mounted on a printed circuit board. Peeling does not occur at the insert interface in the package due to rapid vaporization of moisture inside. Further, peeling or the like, which is a place where moisture absorbed is accumulated, is reduced, so that cracks and the like of the package are reduced and good solder reflow resistance is exhibited.

【００１９】[0019]

【実施例】以下、本発明について実施例１〜１１，比較
例１〜９に従い具体的に説明する。EXAMPLES The present invention will be specifically described below with reference to Examples 1 to 11 and Comparative Examples 1 to 9.

【００２０】下記に示すエポキシ樹脂並びにフェノール
樹脂硬化剤、及び硬化促進剤としてトリフェニルフォス
フィン、充填剤として平均粒径８μｍの溶融シリカの破
砕粉と平均粒径２８μｍの球形溶融シリカをそれぞれ３
／７の混合したものを用い、難燃助剤として三酸化アン
チモン、カップリング剤としてエポキシシラン、離型剤
としてモンタン酸エステル、着色剤としてカーボンブラ
ックを用い、表１に示す配合組成でエポキシ樹脂成形材
料を作製した。素材の混練は二軸の熱ロール（６５−８
５℃）を用い、１０分間行った。The following epoxy resin and phenol resin curing agents, triphenylphosphine as a curing accelerator, crushed powder of fused silica having an average particle size of 8 μm and spherical fused silica having an average particle size of 28 μm are used as fillers, respectively.
/ 7 mixture, antimony trioxide as a flame retardant aid, epoxysilane as a coupling agent, montanic acid ester as a release agent, carbon black as a colorant, and an epoxy resin with the composition shown in Table 1. A molding material was prepared. The kneading of the material is done by a biaxial hot roll (65-8
(5 ° C.) for 10 minutes.

【００２１】エポキシ樹脂 （ａ）エポキシ当量：１９５ｇ／ｅｑEpoxy resin (a) Epoxy equivalent: 195 g / eq

【００２２】[0022]

【化５】 [Chemical 5]

【００２３】（ｂ）エポキシ当量：１９５ｇ／ｅｑ(B) Epoxy equivalent: 195 g / eq

【００２４】[0024]

【化６】 [Chemical 6]

【００２５】（ｃ）エポキシ当量：２５７ｇ／ｅｑ(C) Epoxy equivalent: 257 g / eq

【００２６】[0026]

【化７】 [Chemical 7]

【００２７】（ｄ）エポキシ当量：２２１ｇ／ｅｑ(D) Epoxy equivalent: 221 g / eq

【００２８】[0028]

【化８】 Embedded image

【００２９】（ｅ）エポキシ当量：３７５ｇ／ｅｑ(E) Epoxy equivalent: 375 g / eq

【００３０】[0030]

【化９】 [Chemical 9]

【００３１】フェノール樹脂硬化剤 （ｆ）水酸基当量：１７１ｇ／ｅｑPhenolic resin curing agent (f) Hydroxyl equivalent: 171 g / eq

【００３２】[0032]

【化１０】 [Chemical 10]

【００３３】（ｇ）水酸基当量：１０６ｇ／ｅｑ(G) Hydroxyl equivalent: 106 g / eq

【００３４】[0034]

【化１１】 [Chemical 11]

【００３５】（ｈ）水酸基当量：１６４ｇ／ｅｑ(H) Hydroxyl equivalent: 164 g / eq

【００３６】[0036]

【化１２】 [Chemical 12]

【００３７】（ｉ）水酸基当量：１４０ｇ／ｅｑ(I) Hydroxyl equivalent: 140 g / eq

【００３８】[0038]

【化１３】 [Chemical 13]

【００３９】表中の特性測定は以下の方法で行った。The properties in the table were measured by the following methods.

【００４０】（１）スパイラルフロー：ＥＭＭＩ規格に
準じた金型を用い１８０℃、７０ｋｇ／cm2 の条件で行
った。(1) Spiral flow: It was carried out under the conditions of 180 ° C. and 70 kg / cm 2 using a mold conforming to the EMMI standard.

【００４１】（２）ガラス転移温度並びに線膨張係数：
熱物理試験機を用い、昇温速度５℃／min で測定した。(2) Glass transition temperature and linear expansion coefficient:
Using a thermophysical tester, measurement was performed at a temperature rising rate of 5 ° C / min.

【００４２】（３）曲げ強度および曲げ弾性率：ＪＩＳ
−Ｋ６９１１に準じて、室温並びに２５０℃で測定し
た。(3) Flexural strength and flexural modulus: JIS
According to K6911, it was measured at room temperature and 250 ° C.

【００４３】（４）吸湿率：直径９０mmφ、厚さ２mmｔ
の円盤を成形し、８５℃／８５％ＲＨの吸湿条件で３０
０時間吸湿させ、重量変化から求めた。(4) Moisture absorption rate: diameter 90 mmφ, thickness 2 mmt
Molded discs of 30 ° C under a humidity absorption condition of 85 ° C / 85% RH
It was allowed to absorb moisture for 0 hours, and the weight change was determined.

【００４４】（５）アルミ接着力：厚さ３０μｍのアル
ミ箔との接着力をピール強度から求めた。アルミ箔の引
っ張り速度は５０mm／分で測定した。(5) Adhesive strength to aluminum: The adhesive strength to an aluminum foil having a thickness of 30 μm was determined from the peel strength. The pulling speed of the aluminum foil was measured at 50 mm / min.

【００４５】（６）ポリイミド接着力：厚さ３０μｍの
アルミ箔にポリイミドをスピンコートし所定条件で硬化
させ、アルミテープ上に１０μｍのポリイミド膜を形成
した。ポリイミド膜上にエポキシ樹脂成形材料を成形し
引き剥がし速度５０mm／分でのピール強度を測定した。(6) Polyimide adhesive strength: A 30 μm thick aluminum foil was spin-coated with polyimide and cured under predetermined conditions to form a 10 μm polyimide film on the aluminum tape. An epoxy resin molding material was molded on the polyimide film, and the peel strength was measured at a peeling speed of 50 mm / min.

【００４６】次に、本発明を適用した半導体装置の構造
を図面を用いて説明する。Next, the structure of the semiconductor device to which the present invention is applied will be described with reference to the drawings.

【００４７】図１は半導体素子であるシリコンチップ６
をフィルム状の両面接着剤２を介してリードフレーム４
に固着した後、素子上の電極部とインナーリード４を金
ワイヤ１で電気的に接続した後、素子及びインナーリー
ドをエポキシ樹脂組成物硬化物３（封止材）で封止した
ＳＯＪの例である。FIG. 1 shows a silicon chip 6 which is a semiconductor element.
Through the film-shaped double-sided adhesive 2 to the lead frame 4
Example of SOJ in which the electrode portion on the element and the inner lead 4 are electrically connected to each other with the gold wire 1 and then the element and the inner lead are sealed with the cured epoxy resin composition 3 (sealing material) Is.

【００４８】図２は、リードフレームのダイパッド部１
２に半導体素子であるシリコンチップ１３を層間接着材
１１で固着し、素子上の電極部とインナーリード１０を
金ワイヤ９で電気的に接続した後、素子及びインナーリ
ードをエポキシ樹脂組成物８（封止材）で封止したＴＳ
ＯＰ（Thin Small Outline Plastic Package）の例であ
る。FIG. 2 shows the die pad portion 1 of the lead frame.
A silicon chip 13, which is a semiconductor device, is fixed to the semiconductor chip 2 by an interlayer adhesive 11, and the electrode portion on the device and the inner lead 10 are electrically connected by a gold wire 9, and then the device and the inner lead are bonded with an epoxy resin composition 8 ( TS sealed with (sealing material)
This is an example of OP (Thin Small Outline Plastic Package).

【００４９】図３は多層プリント配線基板上に半導体素
子であるシリコンチップ１７を層間接着材を用いて固着
し、素子上の電極部と多層プリント配線基板上の電極部
とを金ワイヤ１６で電気的に接続した後、多層プリント
配線基板１８のシリコンチップ搭載面上のシリコンチッ
プおよび多層プリント配線基板１８の電極部をエポキシ
樹脂組成物１５（封止材）で封止し、多層プリント配線
基板１８のシリコンチップ搭載面の裏側にシリコンチッ
プ１７と電気的な接続がとられたはんだボール１９が固
着されているＢＧＡパッケージ（Ball Grid Package ）
の例である。In FIG. 3, a silicon chip 17, which is a semiconductor element, is fixed on a multilayer printed wiring board using an interlayer adhesive, and an electrode portion on the element and an electrode portion on the multilayer printed wiring board are electrically connected by a gold wire 16. After the electrical connection, the silicon chip on the silicon chip mounting surface of the multilayer printed wiring board 18 and the electrode portion of the multilayer printed wiring board 18 are sealed with the epoxy resin composition 15 (sealing material). BGA package (Ball Grid Package) in which solder balls 19 electrically connected to the silicon chip 17 are fixed to the back side of the silicon chip mounting surface of
Is an example of.

【００５０】図４は半導体素子であるシリコンチップ２
１とはんだボール２３とを弾性を有する両面接着層２２
で電気的に接続した後、エポキシ樹脂組成物２０（封止
材）で封止した半導体装置の例である。FIG. 4 shows a silicon chip 2 which is a semiconductor element.
Double-sided adhesive layer 22 having elasticity between 1 and solder ball 23
It is an example of a semiconductor device which is electrically connected by the method and then sealed with the epoxy resin composition 20 (sealing material).

【００５１】表１から明らかなように、本発明における
半導体封止用のエポキシ樹脂組成物は比較例１〜９に示
すエポキシ樹脂組成物に比較して、アルミニウム，ポリ
イミドへの接着性が向上している。As is clear from Table 1, the epoxy resin composition for semiconductor encapsulation of the present invention has improved adhesiveness to aluminum and polyimide as compared with the epoxy resin compositions shown in Comparative Examples 1 to 9. ing.

【００５２】[0052]

【表１】 [Table 1]

【００５３】実施例１〜３と比較例１，実施例４と比較
例２，実施例５と比較例３，実施例６と比較例４，実施
例７と比較例５，実施例８と比較例６，実施例９と比較
例７，実施例１０と比較例８，実施例１１と比較例９の
ようにそれぞれの樹脂系ごとに比較すると、ガラス転移
温度，曲げ強度，曲げ弾性率，吸湿率等の物性を損なう
ことなくアルミピール強度，ＰＩＱピール強度が大きく
なるため、半導体装置内部のインサートと封止材との接
着力が増し、耐はんだリフロー性，温度サイクル性等の
信頼性の向上が期待できる。Examples 1 to 3 and Comparative Example 1, Example 4 and Comparative Example 2, Example 5 and Comparative Example 3, Example 6 and Comparative Example 4, Example 7 and Comparative Example 5, and Example 8 When comparing each resin system like Example 6, Example 9 and Comparative Example 7, Example 10 and Comparative Example 8, and Example 11 and Comparative Example 9, the glass transition temperature, bending strength, bending elastic modulus, moisture absorption Since the aluminum peel strength and PIQ peel strength are increased without deteriorating the physical properties such as rate, the adhesive force between the insert inside the semiconductor device and the sealing material is increased, and the reliability such as solder reflow resistance and temperature cycle property is improved. Can be expected.

【００５４】また、この材料を用いて、図１に示したＳ
ＯＪならびに図２に示したＴＳＯＰを作製した。耐はん
だリフロー性の信頼性試験はこの樹脂封止型半導体装置
を８５℃、８５％ＲＨ下で１６８時間放置後、直ちに２
４０℃の赤外線リフロー炉中で９０秒間加熱する試験を
行い、封止層のクラックしたものをクラック発生数とし
て調べた。また超音波探傷装置を用いて封止樹脂層と半
導体装置内の各インサートとの剥離状況を調べ、剥離し
たものを剥離発生数として数えた。これらの結果をまと
めて表２に示す。Using this material, the S shown in FIG.
OJ and TSOP shown in FIG. 2 were prepared. For the reliability test of solder reflow resistance, this resin-encapsulated semiconductor device was left at 85 ° C. and 85% RH for 168 hours and then immediately subjected to 2
A test of heating for 90 seconds in an infrared reflow furnace at 40 ° C. was performed, and the number of cracks in the sealing layer was examined as the number of cracks. Further, the state of peeling between the sealing resin layer and each insert in the semiconductor device was examined using an ultrasonic flaw detector, and the number of peeled pieces was counted as the number of peeling occurrences. The results are summarized in Table 2.

【００５５】[0055]

【表２】 [Table 2]

【００５６】表２から明らかなように、本発明の樹脂封
止半導体装置は高接着性であるため、リードフレームや
チップ等のインサートとの剥離数が減少することが分か
る。またこれにより、封止層自体のクラックも抑制され
ており、優れた耐はんだリフロー性を示すことが分か
る。また、インサートに対しては高接着性であるが、パ
ッケージ成形時の離型性は優れていることが分かった。As is clear from Table 2, since the resin-sealed semiconductor device of the present invention has high adhesiveness, the number of exfoliations from inserts such as lead frames and chips is reduced. Further, it can be seen that this also suppresses cracks in the sealing layer itself and exhibits excellent solder reflow resistance. Moreover, it was found that the adhesive has a high adhesiveness to the insert, but has an excellent releasability at the time of molding the package.

【００５７】[0057]

【発明の効果】本発明によって得られた樹脂封止型半導
体装置は、従来のものと比べてパッケージ内の各インサ
ートと封止材との間の接着性が大きいため、耐はんだリ
フロー性に優れ、また温度サイクル性，高温放置特性な
ど良好な特性を示す事ができる。The resin-encapsulated semiconductor device obtained by the present invention is superior in solder reflow resistance because the adhesiveness between each insert in the package and the encapsulant is larger than that of the conventional one. In addition, it can exhibit good characteristics such as temperature cycleability and high temperature storage characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図１】ＳＯＪの一実施例の断面図。FIG. 1 is a sectional view of an embodiment of SOJ.

【図２】ＴＳＯＰの一実施例の断面図。FIG. 2 is a cross-sectional view of one embodiment of TSOP.

【図３】ＢＧＡパッケージの一実施例の断面図。FIG. 3 is a sectional view of an example of a BGA package.

【図４】半導体装置の一実施例の断面図。FIG. 4 is a sectional view of an example of a semiconductor device.

【符号の説明】[Explanation of symbols]

１…金ワイヤ、２…接着剤、３…封止材、４…リードフ
レーム、５…パッシベーション膜、６…シリコンチッ
プ。1 ... Gold wire, 2 ... Adhesive, 3 ... Sealing material, 4 ... Lead frame, 5 ... Passivation film, 6 ... Silicon chip.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小角 博義 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyoshi Okano 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】エポキシ樹脂とフェノール性水酸基を有す
る硬化剤，硬化促進剤、更に化１及び化２で表されるア
ルミキレート剤を含有するエポキシ樹脂組成物で封止し
たことを特徴とする半導体装置。 【化１】 【化２】 1. A semiconductor which is encapsulated with an epoxy resin composition containing an epoxy resin, a curing agent having a phenolic hydroxyl group, a curing accelerator, and an aluminum chelating agent represented by Chemical formulas 1 and 2. apparatus. Embedded image Embedded image 【請求項２】リードフレームのインナーリードに固着さ
れた半導体素子表面の電極と前記インナーリード間が電
気的に接続された半導体素子及び前記リードフレームの
一部を化３及び化４で表されるアルミキレート剤を必須
成分として含むシリコーンカップリング剤溶液で表面処
理され、前記半導体素子と前記リードフレームの一部を
エポキシ樹脂とフェノール性水酸基を有する硬化剤，硬
化促進剤を含有するエポキシ樹脂組成物で封止したこと
を特徴とする半導体装置。 【化３】 【化４】 2. A semiconductor element in which an electrode on the surface of a semiconductor element fixed to an inner lead of a lead frame and the inner lead are electrically connected and a part of the lead frame are represented by chemical formulas 3 and 4. Epoxy resin composition surface-treated with a silicone coupling agent solution containing an aluminum chelating agent as an essential component, and containing a curing agent having epoxy resin, a phenolic hydroxyl group-containing curing agent, and a curing accelerator in the semiconductor element and part of the lead frame. A semiconductor device characterized by being sealed with. [Chemical 3] [Chemical 4] 【請求項３】請求項１または２において、無機質微粒子
からなる充填剤が全組成物に対し５０〜８５容量％含む
エポキシ樹脂組成物で封止した樹脂封止型半導体装置。3. A resin-encapsulated semiconductor device according to claim 1, which is encapsulated with an epoxy resin composition containing 50 to 85% by volume of the inorganic fine particle filler with respect to the total composition.
JP6198168A 1994-08-23 1994-08-23 Semiconductor device Pending JPH0859795A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6198168A JPH0859795A (en) 1994-08-23 1994-08-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6198168A JPH0859795A (en) 1994-08-23 1994-08-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0859795A true JPH0859795A (en) 1996-03-05

Family

ID=16386603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6198168A Pending JPH0859795A (en) 1994-08-23 1994-08-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0859795A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10265550A (en) * 1997-03-27 1998-10-06 Toray Ind Inc Epoxy resin composition and semiconductor device
KR100692171B1 (en) * 2005-01-18 2007-03-12 샤프 가부시키가이샤 Semiconductor Devices, Display Modules, and Manufacturing Methods of Semiconductor Devices
JP2012224869A (en) * 2005-07-11 2012-11-15 Sony Chemical & Information Device Corp Thermosetting epoxy resin composition
JP2017168723A (en) * 2016-03-17 2017-09-21 富士電機株式会社 Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10265550A (en) * 1997-03-27 1998-10-06 Toray Ind Inc Epoxy resin composition and semiconductor device
KR100692171B1 (en) * 2005-01-18 2007-03-12 샤프 가부시키가이샤 Semiconductor Devices, Display Modules, and Manufacturing Methods of Semiconductor Devices
JP2012224869A (en) * 2005-07-11 2012-11-15 Sony Chemical & Information Device Corp Thermosetting epoxy resin composition
JP5360348B2 (en) * 2005-07-11 2013-12-04 デクセリアルズ株式会社 Thermosetting epoxy resin composition
JP2017168723A (en) * 2016-03-17 2017-09-21 富士電機株式会社 Semiconductor device

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