JPH0851205A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a p-type diffused layer, which has a sharp profile, on the surface of a substrate in channel region, and suppressing the change of the impurity concentration in the diffused layer. CONSTITUTION:A gate insulating film 14 is one where a silicon oxide film is made by wet oxidizing method, and then it is nitrided by applying lamp annealing processing to it at 1050 deg.C in N2O atmosphere. A surface p-layer 13 is made by implanting boron at a rate of 1.8X10<12>/cm<2> with 5keV through the gate insulating film 14. This boron implantation is performed, with a stroke of implantation set in the gate insulating film 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOSFET element in a semiconductor integrated circuit device.

[0002]

P having an N-type polysilicon gate electrode
A buried channel structure is adopted for a channel type MOSFET (hereinafter referred to as PMOSFET). Further, in a CMOS semiconductor device, N-type polysilicon is commonly used as a gate electrode for a PMOSFET and an N-channel MOSFET (hereinafter referred to as NMOSFET).
The OSFET has a buried channel structure. However, it is not easy to suppress punch-through with a buried channel structure with a fine gate length called sub-half micron or less.

In a buried-channel PMOSFET, a low-concentration P-type diffusion layer (P ⁻ layer) is formed on the channel surface in order to adjust the threshold voltage, but a PMOSFET having a fine gate length is punched through. It is known that reducing the thickness of the surface P ⁻ layer is effective as a method of suppressing the above. In order to reduce the thickness of the P ⁻ layer and suppress punch-through, it is necessary to form a shallow and steep junction with an electrically active surface P ⁻ layer having a thickness of 0.05 μm or less. There is.

[0004] Such a shallow and steep P to channel surface ^-
As one of the methods of forming the layer, a method of forming a gate oxide film as a gate insulating film and then ion-implanting P-type impurities into the substrate surface of the channel region through the gate oxide film has been reported (IEEE Transactions on Electron
Devices, Vol. 40, No. 1, pp. 207-213 (1993)).

[0005]

When a P-type impurity such as boron is implanted into the substrate surface of the channel region through the gate oxide film, the implanted P-type impurity is absorbed in the gate oxide film by the thermal process of the subsequent steps. Therefore, there arises a problem that the impurity concentration of the P ⁻ layer on the substrate surface of the channel region is lowered. As a result, the shallowness and steep difference of the surface P ⁻ layer are impaired, and punch-through suppression is limited.

Also, a surface channel structure NMOSFET
Then, P-type impurities are introduced into the substrate surface of the channel region in order to adjust the threshold voltage, but in that case as well, the P-type impurities on the channel surface are sucked out into the gate oxide film to lower the impurity concentration. Therefore, it becomes a factor of fluctuation of the threshold voltage. It is an object of the present invention to provide a method for forming a P-type diffusion layer having a shallow and steep profile on a substrate surface in a channel region and suppressing a change in impurity concentration of the P-type diffusion layer.

[0007]

A feature of the present invention is that a nitride film or a nitrided oxide film is used as a gate insulating film, and in the steps after the gate insulating film is formed,
The point is that impurities are ion-implanted into the channel region through the gate insulating film. As a result, a P-type diffusion layer having a shallow and steep profile is formed in the substrate surface layer, and P-type impurities in the channel region are suppressed from being sucked into the gate insulating film.

The present invention is a buried channel structure PMOSF.
When it is applied to ET, it is applied to the P-type impurity introduction process of the P ⁻ layer on the channel surface. Further, when the present invention is applied to the NMOSFET having the surface channel structure, it is applied to the P-type impurity introduction process to the channel. It is sufficient that the interface with the substrate is nitrided to about 1 atomic% in the gate insulating film, and the entire gate insulating film does not necessarily have to be a nitride film. Can be fully reached.

When a silicon nitride film is used as the gate insulating film, it can be formed by a thermal CVD method. When a nitrided oxide film is used as the gate insulating film, for example, after forming a silicon oxide film, NH ₃ or N ₂ is formed.
Nitriding can be performed by heat treatment in an O 2 gas atmosphere. If a P-type impurity is introduced into the channel region after forming such a nitride film or a nitrided oxide film, the P-type impurity in the gate insulating film when the gate insulating film is an oxide film as in the conventional case Suction can be suppressed.

The above structure is applied to the buried channel structure PMOS.
When applied to the P-type impurity introduction process of the P ⁻ layer on the channel surface of the FET, a shallow and steep junction having a P ⁻ layer thickness of about 0.05 μm or less can be formed,
It is possible to improve the punch-through suppressing effect of a sub-half micron or smaller fine PMOSFET. When ion implantation is used as the P-type impurity implantation method, the implantation range (concentration peak) of the P-type impurity does not necessarily have to be set on the channel surface, but it is set in the gate insulating film and the tail portion of the impurity profile is set. It is also possible to form the channel surface P ⁻ layer with. By doing so, the P-type impurities are also present in the gate insulating film, and it is possible to further suppress the absorption of the P-type impurities into the gate insulating film, so that a shallower and steeper junction can be formed. . Also, when applied to the surface channel structure NMOSFET, one of the factors causing the fluctuation of the P-type impurity profile of the channel region can be eliminated in the same manner, which is effective in stabilizing the device characteristics.

[0011]

EXAMPLES The present invention will be described in more detail below with reference to examples, but the present invention is not limited to these examples.

Example 1 Two kinds of insulating films, Sample A and Sample B, were formed on a (100) silicon substrate. The insulating film of sample A was formed by forming a 70 Å silicon oxide film by a wet oxidation method at 920 ° C. and then N ₂
Lamp anneal treatment was performed at 1050 ° C. for 60 seconds in an O atmosphere to nitride the silicon oxide film. After that, it was further heat-treated at 920 ° C. for 10 minutes in an N ₂ atmosphere. The thickness of the formed insulating film was 90Å, and it was found from the analysis result of SIMS (Secondary Ion Mass Spectroscopy) that nitrogen atoms were present at about 1 atom% at the interface between the insulating film and the silicon substrate. The insulating film of the sample B is formed by forming a 90Å silicon oxide film by a wet oxidation method at 920 ° C and then performing a heat treatment at 920 ° C for 10 minutes in an N ₂ atmosphere. The silicon oxide film is not nitrided by this heat treatment. The final oxide film thickness is 90Å.

For these samples A and B, the implantation range was set in the silicon substrate and boron was set to 3.4 × 15 × 15 KeV.
Implantation of 10 ¹² atoms / cm ² and 900 ° C. in nitrogen atmosphere
After heat treatment for 60 minutes, the profile of boron atoms in the depth direction was examined by SIMS analysis. The profile of the surface P ⁻ layer of the sample A by SIMS analysis is as shown in FIG.

As a result of comparing the boron atom peak concentrations in the silicon substrate by the samples A and B, the result is 1.5 × for the sample B.
10 ¹⁷ / cm ³ whereas sample A according to the invention
Then, it was 1.9 × 10 ¹⁷ / cm ³ . As described above, it can be seen that the sample A according to the present invention has a higher boron atom peak concentration, and the sucking out into the insulating film is suppressed.

(Embodiment 2) P of a buried channel structure in which the same two kinds of insulating films as A and B as in Embodiment 1 are used as a gate insulating film.
A MOSFET was created. Its structure is shown in FIG. In FIG. 1, an N well 1 is formed on a silicon substrate.
The field oxide film 11 is formed by the 0 and LOCOS methods. The N-type impurity concentration of the N well 10 is 1.5 × 10 ¹⁷
/ Cm ³ . Then, the gate insulating film 14 is formed. The gate insulating film 14 is formed of the insulating films A and B shown in the first embodiment.
M according to the present invention, in which the insulating film A is formed.
MO with OSFET as device A and insulating film B formed
Let SFET be device B. After the gate insulating film 14 is formed, boron is added at 1.8 × 10 ¹² / cm ² at 5 KeV.
The surface P ⁻ layer 13 was formed by injection. This boron implantation is performed by setting an implantation range in the gate insulating film 14. The thickness Yj of the surface P ⁻ layer 13 is about 400Å.

Then, a phosphorus-doped polysilicon film is deposited by the LPCVD method (580 ° C.) and processed into the shape of the gate electrode 15 by lithography and etching,
The periphery of the gate electrode 15 was oxidized at 850 ° C. And
The sidewalls 16 are formed by depositing an oxide film and etching back by the LPCVD method (800 ° C.), and BF ₂ ions are 3 × 10 ¹⁵ atoms / cm ² at 30 KeV in order to form the P ⁺ regions 17 to be the source / drain. Ion-implanted. After the interlayer insulating film was formed, reflow and activation of implanted ions were performed at 850 ° C., and contact holes were opened to form wiring.

By the above process, PMOSFET devices A and B having a gate length of 0.3 μm were prepared and their characteristics were compared. As a result, the S factor is 8 for device A.
It was 5 mV / decade, and for device B it was 97 mV / decade. The S factor is the amount of change in the gate voltage required to increase the drain current by one digit, and here is the measured value when the drain voltage Vd is 3.3V. The off-leakage value was 0.1 pA / μm in the device A and 0.5 pA / μm in the device B. From these results, it was revealed that the device A according to the present invention has a smaller S factor and the off leak is suppressed to a lower value, and the present invention has the effect of suppressing punch through.

[0018]

According to the present invention, when a nitride film or a nitrided oxide film is used as the gate insulating film and P-type impurities are ion-implanted into the substrate surface portion of the channel region through the gate insulating film, the P-type impurity on the channel surface is obtained. It is possible to suppress a change in concentration due to being sucked into the gate insulating film. As a result, the punch-through suppressing effect can be improved when the present invention is applied to the P ⁻ layer forming process on the channel surface of a fine PMOSFET of sub-half micron or less. Further, when the present invention is applied to the channel P-type impurity introduction process of the NMOSFET having the surface channel structure, the characteristic variation can be suppressed.

[Brief description of drawings]

FIG. 1 is a PM of a surface channel structure to which an embodiment is applied.
It is sectional drawing which shows OSFET.

FIG. 2 is a diagram showing a profile of a surface P ⁻ layer in one example.

[Explanation of symbols]

12 deep channel dope layer 13 surface P ⁻ layer 14 gate insulating film 15 gate electrode 17 source / drain P ⁺ layer

Claims (4)

[Claims] 1. A method of manufacturing a MOSFET, comprising:
A semiconductor device characterized in that a nitride film or a nitrided oxide film is formed as a gate insulating film on the surface of a semiconductor substrate, and P-type impurities are ion-implanted into the surface of the substrate in the channel region through the gate insulating film in a subsequent step. Manufacturing method. 2. The manufactured MOSFET is a P-channel MOSFET having a buried channel structure, and the P-type impurities ion-implanted through the gate insulating film form a low-concentration P-type diffusion layer for adjusting the threshold voltage of the channel surface. The method for manufacturing a semiconductor device according to claim 1, which is for forming. 3. The manufactured MOSFET is an N-channel MOSFET having a surface channel structure, and the P-type impurity ion-implanted through the gate insulating film forms a P-type diffusion layer for adjusting the threshold voltage on the channel surface. The method for manufacturing a semiconductor device according to claim 1, wherein the method is for manufacturing a semiconductor device. 4. The semiconductor device according to claim 1, wherein the ion implantation energy is set so that the center of the implantation range of the P type impurity ion implantation performed through the gate insulating film is in the gate insulating film. Production method.