JPH08340047A - Structure for wiring layer of semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To flatten a wiring layer forming surface by suppressing the increases of plug losses and trenches in a tungsten etching back process and barrier metal sticking layer removing process. CONSTITUTION: A silicon nitride layer 14 is formed as a stopper on an SiO2 film 12 which is formed as an interlayer insulating film. Because of the film 14, the formation of TiSiOx due to the oxidation of Ti can be prevented during the course of heat treatment. Therefore, it becomes unnecessary to raise the etching rate at the etching back time of tungsten and removing time of a barrier metal sticking layer. In addition, since the generation of O2 from the SiO2 film 12 is inhibited by the silicon nitride film 14 covering the film 12, the dissociation of a reactive gas is suppressed and the increases of plug losses and trenches can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer wiring technique for semiconductor devices, and more particularly to a technique for reducing plug loss generated during etch back in a blanket tungsten process.

[0002]

2. Description of the Related Art A blanket tungsten process is a typical example of securing a contact coverage of an Al wiring layer in a high aspect ratio contact accompanying the miniaturization of the structure of a semiconductor device. In this process, TiN / T is usually used as an adhesion layer (barrier metal layer) between tungsten (W) and a base (Si substrate or lower wiring layer).
i is used. This TiN / Ti film is an interlayer insulating film S
also formed on iO ₂ film. In this case, keeping the adhesion between the underlayer and Ti, and although the heat treatment is performed in order to improve the ohmic contact, the time Ti layer is SiO ₂
A TiSiO _x layer is formed by reacting with the film.

In the final step of the blanket tungsten process, two steps of tungsten etchback and removal of the TiN / Ti barrier metal adhesion layer are performed. here,
Cl ₂ is mainly used as a reaction gas for the etching for removing the adhesion layer.
However, since the etching rate for TiSiO _x is low, the etching mode can be switched to a high etching rate. For this reason, the amount of overetching of the contact plug portion becomes large, the plug loss (tungsten drop from the contact upper surface) becomes large, a suitable flattening structure cannot be obtained, and the contact coverage of the Al wiring deteriorates.

The conventional blanket tungsten process will be further described with reference to FIGS.
FIG. 8 is a flow diagram of this process. First, in the first step S11, SiO _{2 is} formed as an interlayer insulating film on the Si substrate 51.
The film 52 is formed by CVD (see FIG. 5 (a)). Next, in the second step S12, the contact hole 53 is formed (see FIG. 5B).

Subsequently, in a third step S13, a TiN / Ti barrier metal adhesion layer 54 is formed on the entire surface by sputtering, and further heat treatment is performed to react Si and Ti.
The peeling of the SiO ₂ film 52 and the TiN / Ti adhesion layer 54 is prevented and the electric resistance value in the contact hole is reduced. However, due to this heat treatment, SiO ₂ and T
i reacts to form a TiSiO _x layer having a thickness of several tens of nm. TiN in the range indicated by symbol A in FIG. 5 (c)
The portion of the / Ti barrier metal adhesion layer 54 is enlarged and the state of change is shown in FIG.

That is, as shown in FIG. 7A, the first TiN / Ti barrier metal adhesion layer 54 formed is Ti
It consists of two layers, a layer 54a and a TiN layer 54b. By heat treatment, a TiSiO _x reaction layer 55 is formed as shown in FIG.

In the fourth step S14 shown in FIG. 5 (d), the blanket tungsten 56 is laminated, and in the next fifth step S15, tungsten etch back is performed using a fluorine-based gas (see FIG. 6 (e)). See).

Further, in the sixth step S16, the barrier metal adhesion layer 54 is subjected to chemical mode etching with a low sputter property by using Cl ₂ gas. However, at this time, the TiSiO _x layer 5 formed in the third step S13
For No. 5, since the etching rate is low, it is necessary to continue the etching in the sputter mode with high sputterability in the seventh step S17.

By the sputtering mode etching in the seventh step S17, as shown in FIG. 6 (f), a great amount of overetching is caused, and a large plug loss 57 and a large trenching 58 are generated. As a result, the coverage is deteriorated, and when the Al wiring layer 59 is formed in the eighth step S18, as shown in FIG.
A dip 60 on the order of 500 nm to 600 nm occurs on the surface of the wiring layer 59.

[0010]

As described above, it is necessary to remove the TiSiO _x layer which is hard to be etched and which is generated by the heat treatment for the purpose of securing the contact resistance value and improving the adhesiveness, and therefore, the tungsten overcoat is removed. There is no escape from increased etch. That is, the SiO ₂ film and the Ti
The TiSiO _x reaction layer formed between the N / Ti adhesion layer is less likely to be etched when the TiN / Ti adhesion layer is removed,
An increase in plug loss is unavoidable if a process having a strong sputter property is brought about due to an increase in the amount of overetch.

Further, at the time of this overetching, S
Since O ₂ is generated from iO _2, the dissociation degree of the reaction gas Cl ₂ advances to promote the growth of plug loss and trenching. Therefore, in order to reduce such plug loss and trenching, it is sufficient to prevent the Ti layer from becoming TiSiO _x .

Therefore, an object of the present invention is to prevent generation of TiSiO _x during heat treatment of the barrier metal adhesion layer, suppress tungsten etchback and increase in plug loss and trenching in removal of the barrier metal adhesion layer, and to remove the blanket tungsten removal surface. To obtain a reliable flattened structure.

[0013]

In order to solve the above-mentioned problems, a wiring layer structure of a semiconductor device and a method for manufacturing the same according to the present invention are provided with an interlayer insulating film made of a SiO ₂ film on the underlayer. In a semiconductor device including a contact hole formed in an insulating film, a contact plug made of a TiN / Ti barrier metal adhesion layer formed on the inner wall of the contact hole and the insulating film, and a blanket metal filled in the contact hole, Above SiO ₂
Provided is a wiring layer structure of a semiconductor device, which is characterized in that a silicon nitride film is provided on the film.

Further, according to the present invention, there is provided a method of manufacturing a wiring layer of a semiconductor device including a contact hole,
(1) SiO ₂ on the substrate Si or the underlying layer composed of the lower wiring layer
Forming a film to form a (2) above SiO ₂ film on the surface in the silicon nitride film (SiN), (3) the SiO ₂
A step of forming a contact hole in the film, and (4) TiN / T on the inner surface of the contact hole and on the chambered silicon film.
a step of forming an i-barrier metal adhesion layer and heat-treating,
(5) a step of laminating a blanket metal film, (6) a step of etching back this blanket metal film, and (7) the above T
Provided is a method for manufacturing a wiring layer of a semiconductor device, which comprises a step of etching back an iN / Ti barrier metal adhesion layer and a step (8) of forming a metal wiring layer.

In a preferred embodiment, the TiN /
The feature is that the step of etching back the Ti barrier metal adhesion layer is performed only in the chemical mode.

In a further preferred embodiment, the T
The step of etching back the iN / Ti barrier metal adhesion layer is characterized by including a chemical mode and then a sputtering mode.

[0017]

In the present invention, the introduction of the silicon nitride film as the stopper on the SiO ₂ film prevents the oxidation of Ti during the heat treatment. Therefore, it is possible to reduce the amount of overetching, which is one of the causes of increase in plug loss and trenching, without lowering the etching rate when removing the tungsten etchback and the barrier metal adhesion layer. Further, since SiO ₂ is covered with the silicon nitride film, generation of O ₂ from the SiO ₂ film is prevented. Therefore, dissociation of the reaction gas Cl ₂ can be suppressed, and also in this respect, increase in plug loss and trenching can be suppressed.

Further, by preventing the generation of O ₂ from the SiO ₂ film, the window allowable range for masking at the time of removing the barrier metal adhesion layer is widened, and the final shape can be easily controlled.

A summary of these is as follows.

1) Since Ti is not oxidized, etching can be performed in a process having low sputterability, and the amount of plug loss can be greatly reduced.

2) Since the generation of O ₂ from the SiO ₂ film is blocked by the silicon nitride film, the degree of reaction gas dissociation is suppressed, and trenching and plug loss are less likely to proceed. Therefore, the etching can be performed by a process having a strong sputter property, and the peripheral edge of the contact hole can be formed as a gently sloping shape with no step, so that the deterioration of the aluminum wiring coverage can be reduced.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 schematically show a manufacturing process of a wiring layer structure of a semiconductor device according to the present invention. 3 and 4 are flow charts of this manufacturing process. According to the flow chart of the first embodiment in FIG. 3, first, a SiO ₂ film 12 serving as an interlayer insulating film is formed on the silicon substrate indicated by reference numeral 10 in FIG.
It is formed to a thickness on the order of nm (first step S1).
Next, in a second step S2, as shown in FIG. 1B, a silicon nitride film (SiN) 14 having a thickness of 150 nm order is formed on the SiO ₂ film 12 by CVD.

The CVD conditions for forming the silicon nitride film (SiN) 14 are exemplified below.

[0024] 2) Pressure: 73.3 Pa (0.55 Torr) 3) Temperature: 760 ° C. Then, in the third step S3, the contact hole 16 is formed by RIE or the like (see FIG. 1 (c)). The inner diameter of the contact hole is 0.4 μm at the opening.
It has a large aspect ratio of 0.45 μm and about 0.35 μm at the bottom. Then, in the fourth step S4, T
The iN / Ti barrier metal adhesion layer 18 is formed by sputtering, and in order to maintain the adhesion between SiO ₂ and Ti and to improve ohmic contact, it is 850 ° to 860 ° in a rare gas atmosphere such as Ar or N ₂ . Heat treatment at C.
At this time, the silicon nitride film (SiN) 14 formed in the second step S2 serves as a stopper to suppress the oxidation of Ti (see FIG. 1 (d)).

Next, as shown in FIG. 2E, in the fifth step S5, the blanket tungsten layer 20 is formed by a known CVD method. Next, the sixth shown in FIG. 2 (f)
In step S6, tungsten etching back is performed based on the condition I shown in Table 1 below, which has a fast etching rate to shorten the time, and when the surface of the TiN layer is approached, the etching rate is switched to Condition II in Table 1 where the etching rate is low. Tungsten is over-etched to the TiN surface while controlling.

[0026]

[Table 1]

Then, in the seventh step S7, TiN / T
The etch back of the i barrier metal adhesion layer 18 was performed under the condition III (chemical mode etching condition) of Table 1 having low spattering property, as shown in FIG.
The / Ti film is removed to expose the SiN film 14, and a substantially flat final etching sectional shape is obtained.

In this case, since the etching rate by Ar + C1 ₂ has a low rate with respect to W and SiN, the W surface 24 is not deeply etched even if sufficient over-etching is performed, and some trenching 22 occurs, but plug loss occurs. There is no progress. In the final step S9, an Al wiring layer is formed based on a conventionally known technique.

The flow chart of the second embodiment shown in FIG. 4 is similar to that of the first embodiment in that the condition III in Table 1 is low in spatterability.
Then, the barrier metal is removed halfway (at a place where trenching does not start) by chemical etching (step S7). Up to this point, the operation is the same as in the first embodiment. Next, the etching is switched to the sputtering mode condition shown in the condition IV of Table 1 having high sputterability (eighth step S
8). As a result, sufficient overetching can be performed to ensure flatness, the W surface is etched (at this time, the etching rate is low), and is removed together with the edge portion of SiN, as shown in FIG. 2 (h). Smoothly changing final etching cross-sectional shape without trenching 2
Get 6. SiO ₂ of SiN, as described above this time
O ₂ gas is prevented from being generated and the etching reaction of W and TiN is not promoted.

Thereafter, an aluminum wiring layer is formed as in the first embodiment (step S9). At this time, since the step on the surface of the W plug is gentle, the fall of the aluminum wiring is alleviated and deterioration of the coverage is prevented. .

[0031]

As described above, according to the wiring layer structure of the semiconductor device and the method of manufacturing the same according to the present invention, the amount of plug loss and the amount of trenching can be reduced, so that sufficient flatness can be obtained on the wiring layer forming surface. To be Further, since the fall of the aluminum wiring layer in the contact portion is reduced, the step difference amount of the overlapping contact portions is reduced particularly in the stack contact structure, and the effect of improving the coverage is enhanced. Further, since the amount of overetching at the time of tungsten etchback is reduced, the throughput is improved. Furthermore, the window of the etching mask is widened in the tungsten etch back and barrier metal adhesion layer removal processes, and the shape controllability is improved.

[Brief description of drawings]

FIG. 1 is a sectional view sequentially showing a film forming process of a wiring layer structure of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating tungsten etchback in a process of forming a wiring layer structure of a semiconductor device according to the present invention.

FIG. 3 is a flow chart of a first embodiment relating to a manufacturing process of a wiring layer structure of a semiconductor device according to the present invention.

FIG. 4 is a flowchart of a second embodiment relating to a manufacturing process of a wiring layer structure of a semiconductor device according to the present invention.

5A to 5C are cross-sectional views sequentially showing a film forming process of a wiring layer structure of a conventional semiconductor device.

FIG. 6 is a cross-sectional view illustrating tungsten etchback in a film forming process of a wiring layer structure of a conventional semiconductor device.

FIG. 7 is an enlarged view of a portion indicated by reference symbol A in FIG. 5 (c).

FIG. 8 is a flowchart showing a manufacturing process of a conventional wiring layer structure of a semiconductor device.

[Explanation of symbols]

10: Silicon substrate, 12: SiO ₂ film, 14: Silicon nitride film (SiN), 16: Contact hole, 18:
TiN / Ti barrier metal adhesion layer, 20: blanket tungsten layer.

Claims (4)

[Claims] 1. An interlayer insulating film made of a SiO ₂ film is provided on a lower surface, a contact hole is provided in the interlayer insulating film, and a TiN / Ti barrier metal adhesion layer is formed on the inner wall of the contact hole and the insulating film. In a semiconductor device including a contact plug made of a blanket metal filled in the contact hole, the above-mentioned SiO ₂
A wiring layer structure of a semiconductor device, wherein a silicon nitride film is provided on the film. 2. A method of manufacturing a wiring layer of a semiconductor device including a contact hole, forming a SiO ₂ film on the underlying consisting (1) substrate Si or lower wiring layer, (2) the SiO ₂ A step of forming a silicon nitride film (SiN) on the film surface, (3) a step of forming a contact hole in the SiO ₂ film, and (4) a TiN / Ti barrier metal on the inner surface of the contact hole and on the chambered silicon film. Forming an adhesion layer and heat treating; (5) laminating a blanket metal film; (6) etching back this blanket metal film; (7) etching back the TiN / Ti barrier metal adhesion layer And a step (8) of forming a metal wiring layer. 3. The method according to claim 2, wherein the step of etching back the TiN / Ti barrier metal adhesion layer is performed only in chemical mode. 4. The method of claim 2 wherein the step of etching back the TiN / Ti barrier metal adhesion layer comprises chemical mode followed by sputter mode.